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/Linux-v6.1/drivers/gpu/drm/meson/
Dmeson_vclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
22 * - HDMI Pixel Clocks generation
26 * - Genenate Pixel clocks for 2K/4K 10bit formats
33 * | | | | | |--ENCI
34 * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
35 * |__________| |_________| \ | MUX |--ENCP
36 * --VCLK2-| |--VDAC
37 * |_____|--HDMI-TX
140 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
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/Linux-v6.1/sound/soc/codecs/
Dmax98090.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011-2012 Maxim Integrated Products
253 switch (reg) { in max98090_volatile_register()
266 switch (reg) { in max98090_readable_register()
280 /* Reset the codec by writing to this write-only reset register */ in max98090_reset()
281 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, in max98090_reset()
284 dev_err(max98090->component->dev, in max98090_reset()
301 -600, 600, 0);
304 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
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Dda7213.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 /* -54dB */
34 0x0, 0x11, TLV_DB_SCALE_ITEM(-5400, 0, 0),
35 /* -52.5dB to 15dB */
36 0x12, 0x3f, TLV_DB_SCALE_ITEM(-5250, 150, 0)
41 /* -78dB to 12dB */
42 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
51 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
52 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
53 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
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Dadav80x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Lars-Peter Clausen <lars@metafoo.de>
113 #define ADAV80X_PLL_OUTE_SYSCLKPD(x) BIT(2 - (x))
196 ADAV80X_MUX("Aux Capture Select", &adav80x_aux_capture_mux_ctrl),
197 ADAV80X_MUX("Capture Select", &adav80x_capture_mux_ctrl),
198 ADAV80X_MUX("DAC Select", &adav80x_dac_mux_ctrl),
214 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in adav80x_dapm_sysclk_check()
218 switch (adav80x->clk_src) { in adav80x_dapm_sysclk_check()
232 return strcmp(source->name, clk) == 0; in adav80x_dapm_sysclk_check()
238 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in adav80x_dapm_pll_check()
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Drt1019.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt1019.c -- RT1019 ALSA SoC audio amplifier driver
26 #include <sound/soc-dapm.h>
62 switch (reg) { in rt1019_volatile_register()
78 switch (reg) { in rt1019_readable_register()
109 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
123 SOC_ENUM("Mono LR Select", rt1019_mono_lr_sel),
129 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in r1019_dac_event()
131 switch (event) { in r1019_dac_event()
160 struct snd_soc_component *component = dai->component; in rt1019_hw_params()
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Dcs42l52.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs42l52.c -- CS42L52 ALSA SoC audio driver
28 #include <sound/soc-dapm.h>
60 { CS42L52_ADC_PGA_A, 0x80 }, /* r08 Input A Select */
61 { CS42L52_ADC_PGA_B, 0x80 }, /* r09 Input B Select */
63 { CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
80 { CS42L52_BEEP_FREQ, 0x00 }, /* r1C Beep Freq on Time */
108 switch (reg) { in cs42l52_readable_register()
118 switch (reg) { in cs42l52_volatile_register()
130 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
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Dsrc4xxx.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright 2021-2022 Deqx Pty Ltd
25 static const DECLARE_TLV_DB_SCALE(src_tlv, -12750, 50, 0);
41 SOC_DAPM_ENUM("Port A source select", porta_out_src_enum);
43 SOC_DAPM_ENUM("Port B source select", portb_out_src_enum);
55 SOC_DAPM_ENUM("SRC source select", src_in_enum);
156 struct snd_soc_component *component = dai->component; in src4xxx_set_dai_fmt()
160 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { in src4xxx_set_dai_fmt()
163 src4xxx->master[dai->id] = true; in src4xxx_set_dai_fmt()
167 src4xxx->master[dai->id] = false; in src4xxx_set_dai_fmt()
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Dwm8978.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8978.c -- WM8978 ALSA SoC Audio Codec driver
5 * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7 * Copyright 2006-2009 Wolfson Microelectronics PLC.
106 static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"};
133 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
134 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
135 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
136 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
137 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
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/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgf100.c33 u32 freq; member
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
72 switch (pll) { in read_pll()
75 sclk = device->crystal; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
100 struct nvkm_device *device = clk->base.subdev.device; in read_div()
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Dgk104.c33 u32 freq; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
74 switch (pll) { in read_pll()
77 sclk = device->crystal; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
112 switch (ssrc & 0x00000003) { in read_div()
115 return device->crystal; in read_div()
135 struct nvkm_device *device = clk->base.subdev.device; in read_mem()
136 switch (nvkm_rd32(device, 0x1373f4) & 0x0000000f) { in read_mem()
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Dnv50.c34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
35 switch (device->chipset) { in read_div()
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
55 struct nvkm_device *device = subdev->device; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
60 switch (device->chipset) { in read_pll_src()
63 switch (base) { in read_pll_src()
91 switch (base) { in read_pll_src()
101 switch (rsel) { in read_pll_src()
103 case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
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/Linux-v6.1/drivers/media/tuners/
Dfc0011.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
22 FC11_REG_VCOSEL, /* VCO select */
39 FC11_VCOSEL_2 = 0x08, /* VCO select 2 */
40 FC11_VCOSEL_1 = 0x10, /* VCO select 1 */
70 struct i2c_msg msg = { .addr = priv->addr, in fc0011_writereg()
73 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { in fc0011_writereg()
74 dev_err(&priv->i2c->dev, in fc0011_writereg()
77 return -EIO; in fc0011_writereg()
87 { .addr = priv->addr, in fc0011_readreg()
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Dfc0012.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
9 #include "fc0012-priv.h"
15 .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2 in fc0012_writereg()
18 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { in fc0012_writereg()
19 dev_err(&priv->i2c->dev, in fc0012_writereg()
22 return -EREMOTEIO; in fc0012_writereg()
30 { .addr = priv->cfg->i2c_address, .flags = 0, in fc0012_readreg()
32 { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, in fc0012_readreg()
36 if (i2c_transfer(priv->i2c, msg, 2) != 2) { in fc0012_readreg()
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/Linux-v6.1/drivers/iio/adc/
Dad7192.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2011-2015 Analog Devices Inc.
30 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
31 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
33 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
34 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
35 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
36 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
37 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
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/Linux-v6.1/sound/soc/mediatek/mt8186/
Dmt8186-dai-i2s.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "mt8186-afe-clk.h"
12 #include "mt8186-afe-common.h"
13 #include "mt8186-afe-gpio.h"
14 #include "mt8186-interconnection.h"
88 return -EINVAL; in get_i2s_id_by_name()
94 struct mt8186_afe_private *afe_priv = afe->platform_priv; in get_i2s_priv_by_name()
100 return afe_priv->dai_priv[dai_id]; in get_i2s_priv_by_name()
120 i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name); in mt8186_i2s_hd_get()
121 ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en; in mt8186_i2s_hd_get()
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/Linux-v6.1/drivers/media/radio/
Dradio-cadet.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* radio-cadet.c - A video4linux driver for the ADS Cadet AM/FM Radio Card
17 * 2000-04-29 Russell Kroll <rkroll@exploits.org>
20 * 2001-01-10 Russell Kroll <rkroll@exploits.org>
24 * 2002-01-17 Adam Belay <ambx1@neo.rr.com>
27 * 2003-01-31 Alan Cox <alan@lxorguk.ukuu.org.uk>
30 * 2006-07-30 Hans J. Koch <koch@hjk-az.de>
43 #include <media/v4l2-device.h>
44 #include <media/v4l2-ioctl.h>
45 #include <media/v4l2-ctrls.h>
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/Linux-v6.1/arch/m68k/mac/
Dmacboing.c1 // SPDX-License-Identifier: GPL-2.0
3 * Mac bong noise generator. Note - we ought to put a boingy noise
6 * ----------------------------------------------------------------------
10 * Juergen Mellinger (juergen.mellinger@t-online.de)
27 * (hint: interpolate or hardwire [0 -> Pi/2[, it's symmetric)
31 0, -39, -75, -103, -121, -127, -121, -103, -75, -39
44 static unsigned long mac_bell_phase; /* 0..2*Pi -> 0..0x800 (wavetable size) */
78 switch ( macintosh_config->ident ) in mac_init_asc()
106 * current location of the Apple Sound Chip--ASC--in other Macs.) The in mac_init_asc()
111 * Macintosh models have 16-bit audio input and output capability in mac_init_asc()
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/Linux-v6.1/Documentation/devicetree/bindings/regulator/
Drichtek,rt6245-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rt6245-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
13 The RT6245 is a high-performance, synchronous step-down converter
18 - $ref: regulator.yaml#
23 - richtek,rt6245
28 enable-gpios:
31 it will be treat as a default-on power.
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/Linux-v6.1/Documentation/devicetree/bindings/input/
Diqs269a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
28 "#address-cells":
31 "#size-cells":
34 azoteq,hall-enable:
37 Enables Hall-effect sensing on channels 6 and 7. In this case, keycodes
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/Linux-v6.1/sound/soc/sti/
Duniperif_player.c1 // SPDX-License-Identifier: GPL-2.0-only
17 * Some hardware-related definitions
27 #define UNIPERIF_PLAYER_CLK_ADJ_MIN -999999
68 spin_lock(&player->irq_lock); in uni_player_irq_handler()
69 if (!player->substream) in uni_player_irq_handler()
72 snd_pcm_stream_lock(player->substream); in uni_player_irq_handler()
73 if (player->state == UNIPERIF_STATE_STOPPED) in uni_player_irq_handler()
82 dev_err(player->dev, "FIFO underflow error detected\n"); in uni_player_irq_handler()
85 if (player->underflow_enabled) { in uni_player_irq_handler()
87 player->state = UNIPERIF_STATE_UNDERFLOW; in uni_player_irq_handler()
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/Linux-v6.1/kernel/time/
Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include "tick-internal.h"
24 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
59 sftacc--; in clocks_calc_mult_shift()
66 for (sft = 32; sft > 0; sft--) { in clocks_calc_mult_shift()
78 /*[Clocksource internal variables]---------
88 * Name of the user-specified clocksource.
100 * Also a default for cs->uncertainty_margin when registering clocks.
108 * a lower bound for cs->uncertainty_margin values when registering clocks.
168 cs->flags &= ~(CLOCK_SOURCE_VALID_FOR_HRES | CLOCK_SOURCE_WATCHDOG); in __clocksource_unstable()
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/Linux-v6.1/tools/power/x86/intel-speed-select/
Disst-config.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Speed Select -- Enumerate and control features
52 static int current_clos = -1;
53 static int clos_epp = -1;
54 static int clos_prop_prio = -1;
55 static int clos_min = -1;
56 static int clos_max = -1;
57 static int clos_desired = -1;
139 /* only three CascadeLake-N models are supported */ in update_cpu_model()
148 err(-1, "cannot open /proc/cpuinfo\n"); in update_cpu_model()
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/Linux-v6.1/tools/perf/Documentation/
Dperf-top.txt1 perf-top(1)
5 ----
6 perf-top - System profiling tool.
9 --------
11 'perf top' [-e <EVENT> | --event=EVENT] [<options>]
14 -----------
19 -------
20 -a::
21 --all-cpus::
22 System-wide collection. (default)
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/Linux-v6.1/drivers/iio/temperature/
Dmax31865.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * max31865.c - Maxim MAX31865 RTD-to-Digital Converter sensor driver
64 return spi_write_then_read(data->spi, &reg, 1, data->buf, read_size); in max31865_read()
69 return spi_write(data->spi, data->buf, len); in max31865_write()
81 cfg = data->buf[0]; in enable_bias()
83 data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT; in enable_bias()
84 data->buf[1] = cfg | MAX31865_CFG_VBIAS; in enable_bias()
98 cfg = data->buf[0]; in disable_bias()
101 data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT; in disable_bias()
102 data->buf[1] = cfg; in disable_bias()
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/Linux-v6.1/drivers/iio/frequency/
Dadf4350.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2013 Analog Devices Inc.
78 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) { in adf4350_sync_config()
79 if ((st->regs_hw[i] != st->regs[i]) || in adf4350_sync_config()
81 switch (i) { in adf4350_sync_config()
88 st->val = cpu_to_be32(st->regs[i] | i); in adf4350_sync_config()
89 ret = spi_write(st->spi, &st->val, 4); in adf4350_sync_config()
92 st->regs_hw[i] = st->regs[i]; in adf4350_sync_config()
93 dev_dbg(&st->spi->dev, "[%d] 0x%X\n", in adf4350_sync_config()
94 i, (u32)st->regs[i] | i); in adf4350_sync_config()
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