Lines Matching +full:switch +full:- +full:freq +full:- +full:select
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2011-2015 Analog Devices Inc.
30 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
31 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
33 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
34 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
35 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
36 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
37 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
38 /* (AD7792)/24-bit (AD7192)) */
39 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
40 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
59 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
60 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
63 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
64 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
70 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
76 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
77 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
78 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
79 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
80 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
94 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
95 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
96 #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
101 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
103 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
104 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
106 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
107 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
108 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
109 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
110 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
112 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
113 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
114 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
115 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
117 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
118 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
119 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
120 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
121 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
122 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
123 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
124 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
125 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
126 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
136 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
207 st->syscalib_mode[chan->channel] = mode; in ad7192_set_syscalib_mode()
217 return st->syscalib_mode[chan->channel]; in ad7192_get_syscalib_mode()
233 temp = st->syscalib_mode[chan->channel]; in ad7192_write_syscalib()
236 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, in ad7192_write_syscalib()
237 chan->address); in ad7192_write_syscalib()
239 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, in ad7192_write_syscalib()
240 chan->address); in ad7192_write_syscalib()
275 st->conf &= ~AD7192_CONF_CHAN_MASK; in ad7192_set_channel()
276 st->conf |= AD7192_CONF_CHAN(channel); in ad7192_set_channel()
278 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_channel()
286 st->mode &= ~AD7192_MODE_SEL_MASK; in ad7192_set_mode()
287 st->mode |= AD7192_MODE_SEL(mode); in ad7192_set_mode()
289 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_mode()
295 unsigned int mode = st->mode; in ad7192_append_status()
301 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode); in ad7192_append_status()
305 st->mode = mode; in ad7192_append_status()
313 u32 conf = st->conf; in ad7192_disable_all()
318 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); in ad7192_disable_all()
322 st->conf = conf; in ad7192_disable_all()
353 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, in ad7192_calibrate_all()
357 static inline bool ad7192_valid_external_frequency(u32 freq) in ad7192_valid_external_frequency() argument
359 return (freq >= AD7192_EXT_FREQ_MHZ_MIN && in ad7192_valid_external_frequency()
360 freq <= AD7192_EXT_FREQ_MHZ_MAX); in ad7192_valid_external_frequency()
365 struct device_node *np = st->sd.spi->dev.of_node; in ad7192_of_clock_select()
371 if (st->mclk) { in ad7192_of_clock_select()
372 if (of_property_read_bool(np, "adi,int-clock-output-enable")) in ad7192_of_clock_select()
375 if (of_property_read_bool(np, "adi,clock-xtal")) in ad7192_of_clock_select()
386 struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi); in ad7192_setup()
393 ret = ad_sd_reset(&st->sd, 48); in ad7192_setup()
399 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); in ad7192_setup()
405 if (id != st->chip_info->chip_id) in ad7192_setup()
406 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n", in ad7192_setup()
409 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) | in ad7192_setup()
410 AD7192_MODE_CLKSRC(st->clock_sel) | in ad7192_setup()
413 st->conf = AD7192_CONF_GAIN(0); in ad7192_setup()
415 rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable"); in ad7192_setup()
417 st->mode |= AD7192_MODE_REJ60; in ad7192_setup()
419 refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable"); in ad7192_setup()
420 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) in ad7192_setup()
421 st->conf |= AD7192_CONF_REFSEL; in ad7192_setup()
423 st->conf &= ~AD7192_CONF_CHOP; in ad7192_setup()
424 st->f_order = AD7192_NO_SYNC_FILTER; in ad7192_setup()
426 buf_en = of_property_read_bool(np, "adi,buffer-enable"); in ad7192_setup()
428 st->conf |= AD7192_CONF_BUF; in ad7192_setup()
432 st->conf |= AD7192_CONF_UNIPOLAR; in ad7192_setup()
435 "adi,burnout-currents-enable"); in ad7192_setup()
437 st->conf |= AD7192_CONF_BURN; in ad7192_setup()
439 dev_warn(&st->sd.spi->dev, in ad7192_setup()
443 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_setup()
447 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_setup()
456 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { in ad7192_setup()
457 scale_uv = ((u64)st->int_vref_mv * 100000000) in ad7192_setup()
458 >> (indio_dev->channels[0].scan_type.realbits - in ad7192_setup()
459 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1)); in ad7192_setup()
462 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; in ad7192_setup()
463 st->scale_avail[i][0] = scale_uv; in ad7192_setup()
476 return sysfs_emit(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX)); in ad7192_show_ac_excitation()
486 return sysfs_emit(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW)); in ad7192_show_bridge_switch()
508 switch ((u32)this_attr->address) { in ad7192_set()
511 st->gpocon |= AD7192_GPOCON_BPDSW; in ad7192_set()
513 st->gpocon &= ~AD7192_GPOCON_BPDSW; in ad7192_set()
515 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); in ad7192_set()
519 st->mode |= AD7192_MODE_ACX; in ad7192_set()
521 st->mode &= ~AD7192_MODE_ACX; in ad7192_set()
523 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set()
526 ret = -EINVAL; in ad7192_set()
535 int *freq) in ad7192_get_available_filter_freq() argument
540 fadc = DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_available_filter_freq()
541 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode)); in ad7192_get_available_filter_freq()
542 freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); in ad7192_get_available_filter_freq()
544 fadc = DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_available_filter_freq()
545 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode)); in ad7192_get_available_filter_freq()
546 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024); in ad7192_get_available_filter_freq()
548 fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode)); in ad7192_get_available_filter_freq()
549 freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024); in ad7192_get_available_filter_freq()
550 freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024); in ad7192_get_available_filter_freq()
565 len += scnprintf(buf + len, PAGE_SIZE - len, in ad7192_show_filter_avail()
569 buf[len - 1] = '\n'; in ad7192_show_filter_avail()
614 int freq_avail[4], i, ret, freq; in ad7192_set_3db_filter_freq() local
619 freq = val * 1000 + val2; in ad7192_set_3db_filter_freq()
624 diff_new = abs(freq - freq_avail[i]); in ad7192_set_3db_filter_freq()
631 switch (idx) { in ad7192_set_3db_filter_freq()
633 st->f_order = AD7192_SYNC4_FILTER; in ad7192_set_3db_filter_freq()
634 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
636 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
639 st->f_order = AD7192_SYNC3_FILTER; in ad7192_set_3db_filter_freq()
640 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
642 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
645 st->f_order = AD7192_NO_SYNC_FILTER; in ad7192_set_3db_filter_freq()
646 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
648 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
651 st->f_order = AD7192_NO_SYNC_FILTER; in ad7192_set_3db_filter_freq()
652 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
654 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
658 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_3db_filter_freq()
662 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_3db_filter_freq()
669 fadc = DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_3db_filter_freq()
670 st->f_order * AD7192_MODE_RATE(st->mode)); in ad7192_get_3db_filter_freq()
672 if (st->conf & AD7192_CONF_CHOP) in ad7192_get_3db_filter_freq()
674 if (st->mode & AD7192_MODE_SINC3) in ad7192_get_3db_filter_freq()
687 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR); in ad7192_read_raw()
689 switch (m) { in ad7192_read_raw()
693 switch (chan->type) { in ad7192_read_raw()
695 mutex_lock(&st->lock); in ad7192_read_raw()
696 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; in ad7192_read_raw()
697 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1]; in ad7192_read_raw()
698 mutex_unlock(&st->lock); in ad7192_read_raw()
705 return -EINVAL; in ad7192_read_raw()
709 *val = -(1 << (chan->scan_type.realbits - 1)); in ad7192_read_raw()
713 if (chan->type == IIO_TEMP) in ad7192_read_raw()
714 *val -= 273 * ad7192_get_temp_scale(unipolar); in ad7192_read_raw()
717 *val = st->fclk / in ad7192_read_raw()
718 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)); in ad7192_read_raw()
726 return -EINVAL; in ad7192_read_raw()
743 switch (mask) { in ad7192_write_raw()
745 ret = -EINVAL; in ad7192_write_raw()
746 mutex_lock(&st->lock); in ad7192_write_raw()
747 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) in ad7192_write_raw()
748 if (val2 == st->scale_avail[i][1]) { in ad7192_write_raw()
750 tmp = st->conf; in ad7192_write_raw()
751 st->conf &= ~AD7192_CONF_GAIN(-1); in ad7192_write_raw()
752 st->conf |= AD7192_CONF_GAIN(i); in ad7192_write_raw()
753 if (tmp == st->conf) in ad7192_write_raw()
755 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, in ad7192_write_raw()
756 3, st->conf); in ad7192_write_raw()
760 mutex_unlock(&st->lock); in ad7192_write_raw()
764 ret = -EINVAL; in ad7192_write_raw()
768 div = st->fclk / (val * st->f_order * 1024); in ad7192_write_raw()
770 ret = -EINVAL; in ad7192_write_raw()
774 st->mode &= ~AD7192_MODE_RATE(-1); in ad7192_write_raw()
775 st->mode |= AD7192_MODE_RATE(div); in ad7192_write_raw()
776 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_write_raw()
782 ret = -EINVAL; in ad7192_write_raw()
794 switch (mask) { in ad7192_write_raw_get_fmt()
802 return -EINVAL; in ad7192_write_raw_get_fmt()
813 switch (mask) { in ad7192_read_avail()
815 *vals = (int *)st->scale_avail; in ad7192_read_avail()
818 *length = ARRAY_SIZE(st->scale_avail) * 2; in ad7192_read_avail()
823 return -EINVAL; in ad7192_read_avail()
829 u32 conf = st->conf; in ad7192_update_scan_mode()
837 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); in ad7192_update_scan_mode()
841 st->conf = conf; in ad7192_update_scan_mode()
870 .differential = ((_channel2) == -1 ? 0 : 1), \
898 __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \
902 __AD719x_CHANNEL(_si, _channel1, -1, _address, "shorted", IIO_VOLTAGE, \
906 __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL)
961 switch (st->chip_info->chip_id) { in ad7192_channels_config()
963 indio_dev->channels = ad7193_channels; in ad7192_channels_config()
964 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels); in ad7192_channels_config()
967 indio_dev->channels = ad7192_channels; in ad7192_channels_config()
968 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels); in ad7192_channels_config()
991 if (!spi->irq) { in ad7192_probe()
992 dev_err(&spi->dev, "no IRQ?\n"); in ad7192_probe()
993 return -ENODEV; in ad7192_probe()
996 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); in ad7192_probe()
998 return -ENOMEM; in ad7192_probe()
1002 mutex_init(&st->lock); in ad7192_probe()
1004 st->avdd = devm_regulator_get(&spi->dev, "avdd"); in ad7192_probe()
1005 if (IS_ERR(st->avdd)) in ad7192_probe()
1006 return PTR_ERR(st->avdd); in ad7192_probe()
1008 ret = regulator_enable(st->avdd); in ad7192_probe()
1010 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n"); in ad7192_probe()
1014 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd); in ad7192_probe()
1018 st->dvdd = devm_regulator_get(&spi->dev, "dvdd"); in ad7192_probe()
1019 if (IS_ERR(st->dvdd)) in ad7192_probe()
1020 return PTR_ERR(st->dvdd); in ad7192_probe()
1022 ret = regulator_enable(st->dvdd); in ad7192_probe()
1024 dev_err(&spi->dev, "Failed to enable specified DVdd supply\n"); in ad7192_probe()
1028 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->dvdd); in ad7192_probe()
1032 ret = regulator_get_voltage(st->avdd); in ad7192_probe()
1034 dev_err(&spi->dev, "Device tree error, reference voltage undefined\n"); in ad7192_probe()
1037 st->int_vref_mv = ret / 1000; in ad7192_probe()
1039 st->chip_info = of_device_get_match_data(&spi->dev); in ad7192_probe()
1040 indio_dev->name = st->chip_info->name; in ad7192_probe()
1041 indio_dev->modes = INDIO_DIRECT_MODE; in ad7192_probe()
1047 if (st->chip_info->chip_id == CHIPID_AD7195) in ad7192_probe()
1048 indio_dev->info = &ad7195_info; in ad7192_probe()
1050 indio_dev->info = &ad7192_info; in ad7192_probe()
1052 ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info); in ad7192_probe()
1054 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); in ad7192_probe()
1058 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_probe()
1060 st->mclk = devm_clk_get_optional(&spi->dev, "mclk"); in ad7192_probe()
1061 if (IS_ERR(st->mclk)) in ad7192_probe()
1062 return PTR_ERR(st->mclk); in ad7192_probe()
1064 st->clock_sel = ad7192_of_clock_select(st); in ad7192_probe()
1066 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 || in ad7192_probe()
1067 st->clock_sel == AD7192_CLK_EXT_MCLK2) { in ad7192_probe()
1068 ret = clk_prepare_enable(st->mclk); in ad7192_probe()
1072 ret = devm_add_action_or_reset(&spi->dev, ad7192_clk_disable, in ad7192_probe()
1073 st->mclk); in ad7192_probe()
1077 st->fclk = clk_get_rate(st->mclk); in ad7192_probe()
1078 if (!ad7192_valid_external_frequency(st->fclk)) { in ad7192_probe()
1079 dev_err(&spi->dev, in ad7192_probe()
1081 return -EINVAL; in ad7192_probe()
1085 ret = ad7192_setup(st, spi->dev.of_node); in ad7192_probe()
1089 return devm_iio_device_register(&spi->dev, indio_dev); in ad7192_probe()