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/Linux-v5.4/Documentation/devicetree/bindings/spi/
Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Generic Binding
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-[0-9a-f])*$"
[all …]
Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
4 memory register, which acts as an SPI master device.
6 The device uses the standard MicroWire half-duplex transfer timing.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
19 - reg: should provide IO memory address
21 Requirements to SPI slave nodes:
23 - There can be only one slave device.
[all …]
Dspi-bcm63xx-hsspi.txt1 Binding for Broadcom BCM6328 High Speed SPI controller
4 - compatible: must contain of "brcm,bcm6328-hsspi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandles of the SPI clock and the PLL clock.
8 - clock-names: must be "hsspi", "pll".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
16 Child nodes as per the generic SPI binding.
[all …]
Dspi-nxp-fspi.txt4 - compatible : Should be "nxp,lx2160a-fspi"
5 - reg : First contains the register location and length,
7 - reg-names : Should contain the resource reg names:
8 - fspi_base: configuration register address space
9 - fspi_mmap: memory mapped address space
10 - interrupts : Should contain the interrupt for the device
12 Required SPI slave node properties:
13 - reg : There are two buses (A and B) with two chip selects each.
14 This encodes to which bus and CS the flash is connected:
15 - <0>: Bus A, CS 0
[all …]
Dqcom,spi-qup.txt1 Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
6 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
10 - compatible: Should contain:
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
15 - reg: Should contain base register location and length
16 - interrupts: Interrupt number used by this controller
18 - clocks: Should contain the core clock and the AHB clock.
[all …]
Dsh-msiof.txt1 Renesas MSIOF spi controller
4 - compatible : "renesas,msiof-r8a7743" (RZ/G1M)
5 "renesas,msiof-r8a7744" (RZ/G1N)
6 "renesas,msiof-r8a7745" (RZ/G1E)
7 "renesas,msiof-r8a77470" (RZ/G1C)
8 "renesas,msiof-r8a774a1" (RZ/G2M)
9 "renesas,msiof-r8a774c0" (RZ/G2E)
10 "renesas,msiof-r8a7790" (R-Car H2)
11 "renesas,msiof-r8a7791" (R-Car M2-W)
12 "renesas,msiof-r8a7792" (R-Car V2H)
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/rtc/
Depson,rx6110.txt4 The Epson RX6110 can be used with SPI or I2C busses. The kind of
8 --------
11 - compatible: should be: "epson,rx6110"
12 - reg : the I2C address of the device for I2C
21 SPI mode
22 --------
25 - compatible: should be: "epson,rx6110"
26 - reg: chip select number
27 - spi-cs-high: RX6110 needs chipselect high
28 - spi-cpha: RX6110 works with SPI shifted clock phase
[all …]
Dnxp,rtc-2123.txt1 NXP PCF2123 SPI Real Time Clock
4 - compatible: should be: "nxp,pcf2123"
6 - reg: should be the SPI slave chipselect address
9 - spi-cs-high: PCF2123 needs chipselect high
16 spi-cs-high;
Dmaxim-ds1302.txt1 * Maxim/Dallas Semiconductor DS-1302 RTC
5 The device uses the standard MicroWire half-duplex transfer timing.
12 - compatible : Should be "maxim,ds1302"
14 Required SPI properties:
16 - reg : Should be address of the device chip select within
19 - spi-max-frequency : DS-1302 has 500 kHz if powered at 2.2V,
22 - spi-3wire : The device has a shared signal IN/OUT line.
24 - spi-lsb-first : DS-1302 requires least significant bit first
27 - spi-cs-high: DS-1302 has active high chip select line. This is
32 spi@901c {
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/gpio/
Dspear_spics.txt1 === ST Microelectronics SPEAr SPI CS Driver ===
4 Cell spi controller through its system registers, which otherwise remains under
7 desired by some of the device protocols above spi which expect (multiple)
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/mfd/
Dmotorola-cpcap.txt4 - compatible : One or both of "motorola,cpcap" or "ste,6556002"
5 - reg : SPI chip select
6 - interrupts : The interrupt line the device is connected to
7 - interrupt-controller : Marks the device node as an interrupt controller
8 - #interrupt-cells : The number of cells to describe an IRQ, should be 2
9 - #address-cells : Child device offset number of cells, should be 1
10 - #size-cells : Child device size number of cells, should be 0
11 - spi-max-frequency : Typically set to 3000000
12 - spi-cs-high : SPI chip select direction
16 The sub-functions of CPCAP get their own node with their own compatible values,
[all …]
Dcros-ec.txt3 Google's ChromeOS EC is a Cortex-M device which talks to the AP and
6 The EC can be connect through various means (I2C, SPI, LPC, RPMSG) and the
8 its own driver which connects to the top level interface-agnostic EC driver.
9 Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to
10 the top-level driver.
13 - compatible: "google,cros-ec-i2c"
14 - reg: I2C slave address
16 Required properties (SPI):
17 - compatible: "google,cros-ec-spi"
18 - reg: SPI chip select
[all …]
/Linux-v5.4/drivers/gpio/
Dgpiolib-of.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2007-2008 MontaVista Software, Inc.
24 #include "gpiolib-of.h"
40 snprintf(propname, sizeof(propname), "%s-%s", in of_gpio_get_count()
46 ret = of_gpio_named_count(dev->of_node, propname); in of_gpio_get_count()
50 return ret ? ret : -ENOENT; in of_gpio_get_count()
57 return chip->gpiodev->dev.of_node == gpiospec->np && in of_gpiochip_match_node_and_xlate()
58 chip->of_xlate && in of_gpiochip_match_node_and_xlate()
59 chip->of_xlate(chip, gpiospec, NULL) >= 0; in of_gpiochip_match_node_and_xlate()
74 if (chip->of_gpio_n_cells != gpiospec->args_count) in of_xlate_and_get_gpiod_flags()
[all …]
Dgpio-spear-spics.c2 * SPEAr platform SPI chipselect abstraction over gpiolib
24 * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
25 * through system registers. This register lies outside spi (pl022)
28 * It provides control for spi chip select lines so that any chipselect
34 * struct spear_spics - represents spi chip select control
38 * @cs_value_bit: bit to program high or low chipselect
41 * @use_count: use count of a spi controller cs lines
60 return -ENXIO; in spics_get_value()
69 tmp = readl_relaxed(spics->base + spics->perip_cfg); in spics_set_value()
70 if (spics->last_off != offset) { in spics_set_value()
[all …]
/Linux-v5.4/drivers/spi/
Dspi-ppc4xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI_PPC4XX SPI controller driver.
9 * Based in part on drivers/spi/spi_s3c24xx.c
17 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
18 * generate an interrupt to the CPU. This can cause high CPU utilization.
20 * during SPI transfers by setting max_speed_hz via the device tree.
36 #include <linux/spi/spi.h>
37 #include <linux/spi/spi_bitbang.h>
41 #include <asm/dcr-regs.h>
43 /* bits in mode register - bit 0 is MSb */
[all …]
Dspi-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * polling/bitbanging SPI master controller driver utilities
15 #include <linux/spi/spi.h>
16 #include <linux/spi/spi_bitbang.h>
21 /*----------------------------------------------------------------------*/
24 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
25 * Use this for GPIO or shift-register level hardware APIs.
27 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
29 * used, though maybe they're called from controller-aware code.
31 * chipselect() and friends may use spi_device->controller_data and
[all …]
Dspi-bcm63xx-hsspi.c2 * Broadcom BCM63XX High Speed SPI Controller driver
4 * Copyright 2000-2010 Broadcom Corporation
5 * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
17 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
96 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
112 static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs, in bcm63xx_hsspi_set_cs() argument
117 mutex_lock(&bs->bus_mutex); in bcm63xx_hsspi_set_cs()
118 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); in bcm63xx_hsspi_set_cs()
120 reg &= ~BIT(cs); in bcm63xx_hsspi_set_cs()
[all …]
Dspi-dln2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the Diolan DLN-2 USB-SPI adapter
12 #include <linux/spi/spi.h>
19 /* SPI commands */
87 * needed because all SPI communication is serialized by the SPI core.
94 u8 cs; member
98 * Enable/Disable SPI module. The disable command will wait for transfers to
110 tx.port = dln2->port; in dln2_spi_enable()
114 len -= sizeof(tx.wait_for_completion); in dln2_spi_enable()
120 return dln2_transfer_tx(dln2->pdev, cmd, &tx, len); in dln2_spi_enable()
[all …]
Dspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // SPI init/core code
11 #include <linux/dma-mapping.h>
16 #include <linux/clk/clk-conf.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi-mem.h>
38 #include <trace/events/spi.h>
48 struct spi_device *spi = to_spi_device(dev); in spidev_release() local
50 /* spi controllers may cleanup for released devices */ in spidev_release()
51 if (spi->controller->cleanup) in spidev_release()
[all …]
Dspi-orion.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell Orion SPI controller driver
6 * Copyright (C) 2007-2008 Marvell Ltd.
14 #include <linux/spi/spi.h>
64 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \ argument
76 * have both is for managing the armada-370-spi case with old
108 return orion_spi->base + reg; in spi_reg()
133 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) in orion_spi_baudrate_set() argument
142 orion_spi = spi_master_get_devdata(spi->master); in orion_spi_baudrate_set()
143 devdata = orion_spi->devdata; in orion_spi_baudrate_set()
[all …]
Dspi-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SPI master driver using generic bitbanged GPIO
15 #include <linux/spi/spi.h>
16 #include <linux/spi/spi_bitbang.h>
17 #include <linux/spi/spi_gpio.h>
21 * This bitbanging SPI master driver should help make systems usable
22 * when a native hardware SPI engine is not available, perhaps because
26 * platform_device->driver_data ... points to spi_gpio
28 * spi->controller_state ... reserved for bitbang framework code
30 * spi->master->dev.driver_data ... points to spi_gpio->bitbang
[all …]
/Linux-v5.4/drivers/platform/chrome/
Dcros_ec_spi.c1 // SPDX-License-Identifier: GPL-2.0
2 // SPI interface for ChromeOS Embedded Controller
14 #include <linux/spi/spi.h>
22 * about 400-500us for the EC to respond there is not a lot of
26 * SPI transfer size is 256 bytes, so at 5MHz we need a response
48 * for this, clocking in at 2-3ms.
53 * Time between raising the SPI chip select (for the end of a
62 * struct cros_ec_spi - information about a SPI-connected EC
64 * @spi: SPI device we are connected to
67 * is sent when we want to turn on CS at the start of a transaction.
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/misc/
Deeprom-93xx46.txt1 EEPROMs (SPI) compatible with Microchip Technology 93xx46 family.
4 - compatible : shall be one of:
6 "eeprom-93xx46"
7 - data-size : number of data bits per word (either 8 or 16)
10 - read-only : parameter-less property which disables writes to the EEPROM
11 - select-gpios : if present, specifies the GPIO that will be asserted prior to
12 each access to the EEPROM (e.g. for SPI bus multiplexing)
14 Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt
15 apply. In particular, "reg" and "spi-max-frequency" properties must be given.
19 compatible = "eeprom-93xx46";
[all …]
/Linux-v5.4/arch/powerpc/boot/dts/
Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 bank-width = <2>;
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/display/panel/
Dkingdisplay,kd035g6-54nt.txt1 King Display KD035G6-54NT 3.5" (320x240 pixels) 24-bit TFT LCD panel
4 - compatible: should be "kingdisplay,kd035g6-54nt"
5 - power-supply: See panel-common.txt
6 - reset-gpios: See panel-common.txt
9 - backlight: see panel-common.txt
11 The generic bindings for the SPI slaves documented in [1] also apply.
17 [1]: Documentation/devicetree/bindings/spi/spi-bus.txt
22 &spi {
24 compatible = "kingdisplay,kd035g6-54nt";
27 spi-max-frequency = <3125000>;
[all …]

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