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/Linux-v6.6/Documentation/devicetree/bindings/sifive/
Dsifive-blocks-ip-versioning.txt1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
16 Until these IP blocks (or IP integration) support version
17 auto-discovery, the maintainers of these IP blocks intend to increment
19 interface to these IP blocks changes, or when the functionality of the
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/Linux-v6.6/Documentation/devicetree/bindings/pwm/
Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 SiFive, Inc.
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive PWM controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 Unlike most other PWM controllers, the SiFive PWM controller currently
19 numbers can be found here -
21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
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/Linux-v6.6/Documentation/devicetree/bindings/spi/
Dspi-sifive.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive SPI controller
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: spi-controller.yaml#
20 - enum:
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/Linux-v6.6/Documentation/devicetree/bindings/serial/
Dsifive-serial.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: serial.yaml#
20 - enum:
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/Linux-v6.6/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive Core Local Interruptor
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
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/Linux-v6.6/drivers/tty/serial/
Dsifive.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SiFive UART driver
5 * Copyright (C) 2018-2019 SiFive
8 * - drivers/tty/serial/pxa.c
9 * - drivers/tty/serial/amba-pl011.c
10 * - drivers/tty/serial/uartlite.c
11 * - drivers/tty/serial/omap-serial.c
12 * - drivers/pwm/pwm-sifive.c
15 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
16 * SiFive FE310-G000 v2p3
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/Linux-v6.6/drivers/edac/
DKconfig16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
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/Linux-v6.6/drivers/clk/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
66 This driver supports NCO (Numerically Controlled Oscillator) blocks
67 found on Apple SoCs such as t8103 (M1). The blocks are typically
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
129 be pre-programmed to support other configurations and features not yet
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
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/Linux-v6.6/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
145 supports spi-mem interface.
224 this code to manage the per-word or per-transfer accesses to the
254 Flash over 1/2/4-bit wide bus. Enable this option if you have a
266 Flash over up to 8-bit wide bus. Enable this option if you have a
274 This enables dedicated general purpose SPI/Microwire1-compatible
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/Linux-v6.6/drivers/gpio/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
47 this symbol, but new drivers should use the generic gpio-regmap
57 non-sleeping contexts. They can make bitbanged serial protocols
118 Enables support for the idio-16 library functions. The idio-16 library
120 ACCES IDIO-16 family such as the 104-IDIO-16 and the PCI-IDIO-16.
122 If built as a module its name will be gpio-idio-16.
128 tristate "GPIO driver for 74xx-ICs with MMIO access"
132 Say yes here to support GPIO functionality for 74xx-compatible ICs
149 If driver is built as a module it will be called gpio-altera.
310 tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"
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