1 // SPDX-License-Identifier: GPL-2.0+
3  * SiFive UART driver
5  * Copyright (C) 2018-2019 SiFive
8  * - drivers/tty/serial/pxa.c
9  * - drivers/tty/serial/amba-pl011.c
10  * - drivers/tty/serial/uartlite.c
11  * - drivers/tty/serial/omap-serial.c
12  * - drivers/pwm/pwm-sifive.c
15  * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
16  *   SiFive FE310-G000 v2p3
17  * - The tree/master/src/main/scala/devices/uart directory of
18  *   https://github.com/sifive/sifive-blocks/
20  * The SiFive UART design is not 8250-compatible.  The following common
22  * - Word lengths other than 8 bits
23  * - Break handling
24  * - Parity
25  * - Flow control
26  * - Modem signals (DSR, RI, etc.)
117 #define SIFIVE_SERIAL_NAME			"sifive-serial"
119 /* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
137  * struct sifive_serial_port - driver-specific data extension to struct uart_port
145  * Configuration data specific to this SiFive UART.
157  * Structure container-of macros
178  * __ssp_early_writel() - write to a SiFive serial port register (early)
191 	writel_relaxed(v, port->membase + offs);  in __ssp_early_writel()
195  * __ssp_early_readl() - read from a SiFive serial port register (early)
211 	return readl_relaxed(port->membase + offs);  in __ssp_early_readl()
215  * __ssp_writel() - write to a SiFive serial port register
227 	__ssp_early_writel(v, offs, &ssp->port);  in __ssp_writel()
231  * __ssp_readl() - read from a SiFive serial port register
244 	return __ssp_early_readl(&ssp->port, offs);  in __ssp_readl()
248  * sifive_serial_is_txfifo_full() - is the TXFIFO full?
251  * Read the transmit FIFO "full" bit, returning a non-zero value if the
255  * Returns: SIFIVE_SERIAL_TXDATA_FULL_MASK (non-zero) if the transmit FIFO
265  * __ssp_transmit_char() - enqueue a byte to transmit onto the TX FIFO
281  * __ssp_transmit_chars() - enqueue multiple bytes onto the TX FIFO
285  * transmit buffer to the SiFive UART TX FIFO.
287  * Context: Any context.  Expects @ssp->port.lock to be held by caller.
293 	uart_port_tx_limited(&ssp->port, ch, SIFIVE_TX_FIFO_DEPTH,  in __ssp_transmit_chars()
300  * __ssp_enable_txwm() - enable transmit watermark interrupts
304  * on the SiFive UART referred to by @ssp.
308 	if (ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK)  in __ssp_enable_txwm()
311 	ssp->ier |= SIFIVE_SERIAL_IE_TXWM_MASK;  in __ssp_enable_txwm()
312 	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);  in __ssp_enable_txwm()
316  * __ssp_enable_rxwm() - enable receive watermark interrupts
320  * on the SiFive UART referred to by @ssp.
324 	if (ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK)  in __ssp_enable_rxwm()
327 	ssp->ier |= SIFIVE_SERIAL_IE_RXWM_MASK;  in __ssp_enable_rxwm()
328 	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);  in __ssp_enable_rxwm()
332  * __ssp_disable_txwm() - disable transmit watermark interrupts
340 	if (!(ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK))  in __ssp_disable_txwm()
343 	ssp->ier &= ~SIFIVE_SERIAL_IE_TXWM_MASK;  in __ssp_disable_txwm()
344 	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);  in __ssp_disable_txwm()
348  * __ssp_disable_rxwm() - disable receive watermark interrupts
356 	if (!(ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK))  in __ssp_disable_rxwm()
359 	ssp->ier &= ~SIFIVE_SERIAL_IE_RXWM_MASK;  in __ssp_disable_rxwm()
360 	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);  in __ssp_disable_rxwm()
364  * __ssp_receive_char() - receive a byte from the UART
368  * Try to read a byte from the SiFive UART RX FIFO, referenced by
395  * __ssp_receive_chars() - receive multiple bytes from the UART
398  * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
401  * Context: Expects ssp->port.lock to be held by caller.
409 	for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) {  in __ssp_receive_chars()
414 		ssp->port.icount.rx++;  in __ssp_receive_chars()
415 		uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL);  in __ssp_receive_chars()
418 	tty_flip_buffer_push(&ssp->port.state->port);  in __ssp_receive_chars()
422  * __ssp_update_div() - calculate the divisor setting by the line rate
433 	div = DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1;  in __ssp_update_div()
439  * __ssp_update_baud_rate() - set the UART "baud rate"
444  * SiFive UART described by @ssp and program it into the UART.  There may
451 	if (ssp->baud_rate == rate)  in __ssp_update_baud_rate()
454 	ssp->baud_rate = rate;  in __ssp_update_baud_rate()
459  * __ssp_set_stop_bits() - set the number of stop bits
463  * Program the SiFive UART referred to by @ssp to use @nstop stop bits.
476 	v |= (nstop - 1) << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT;  in __ssp_set_stop_bits()
481  * __ssp_wait_for_xmitr() - wait for an empty slot on the TX FIFO
524 	spin_lock(&ssp->port.lock);  in sifive_serial_irq()
528 		spin_unlock(&ssp->port.lock);  in sifive_serial_irq()
537 	spin_unlock(&ssp->port.lock);  in sifive_serial_irq()
580  * sifive_serial_clk_notifier() - clock post-rate-change notifier
586  * after a synchronous divide-by-two divider, so any CPU clock rate change
602 		 * left in the TX queue -- in other words, when the TX FIFO is  in sifive_serial_clk_notifier()
615 		udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate));  in sifive_serial_clk_notifier()
618 	if (event == POST_RATE_CHANGE && ssp->port.uartclk != cnd->new_rate) {  in sifive_serial_clk_notifier()
619 		ssp->port.uartclk = cnd->new_rate;  in sifive_serial_clk_notifier()
636 	if ((termios->c_cflag & CSIZE) != CS8) {  in sifive_serial_set_termios()
637 		dev_err_once(ssp->port.dev, "only 8-bit words supported\n");  in sifive_serial_set_termios()
638 		termios->c_cflag &= ~CSIZE;  in sifive_serial_set_termios()
639 		termios->c_cflag |= CS8;  in sifive_serial_set_termios()
641 	if (termios->c_iflag & (INPCK | PARMRK))  in sifive_serial_set_termios()
642 		dev_err_once(ssp->port.dev, "parity checking not supported\n");  in sifive_serial_set_termios()
643 	if (termios->c_iflag & BRKINT)  in sifive_serial_set_termios()
644 		dev_err_once(ssp->port.dev, "BREAK detection not supported\n");  in sifive_serial_set_termios()
645 	termios->c_iflag &= ~(INPCK|PARMRK|BRKINT);  in sifive_serial_set_termios()
648 	nstop = (termios->c_cflag & CSTOPB) ? 2 : 1;  in sifive_serial_set_termios()
653 				  ssp->port.uartclk / 16);  in sifive_serial_set_termios()
656 	spin_lock_irqsave(&ssp->port.lock, flags);  in sifive_serial_set_termios()
658 	/* Update the per-port timeout */  in sifive_serial_set_termios()
659 	uart_update_timeout(port, termios->c_cflag, rate);  in sifive_serial_set_termios()
661 	ssp->port.read_status_mask = 0;  in sifive_serial_set_termios()
666 	if ((termios->c_cflag & CREAD) == 0)  in sifive_serial_set_termios()
673 	spin_unlock_irqrestore(&ssp->port.lock, flags);  in sifive_serial_set_termios()
689 	ssp->port.type = PORT_SIFIVE_V0;  in sifive_serial_config_port()
695 	return -EINVAL;  in sifive_serial_verify_port()
700 	return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL;  in sifive_serial_type()
743 	struct earlycon_device *dev = con->data;  in early_sifive_serial_write()
744 	struct uart_port *port = &dev->port;  in early_sifive_serial_write()
752 	struct uart_port *port = &dev->port;  in early_sifive_serial_setup()
754 	if (!port->membase)  in early_sifive_serial_setup()
755 		return -ENODEV;  in early_sifive_serial_setup()
757 	dev->con->write = early_sifive_serial_write;  in early_sifive_serial_setup()
762 OF_EARLYCON_DECLARE(sifive, "sifive,uart0", early_sifive_serial_setup);
763 OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart0",
786 	struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index];  in sifive_serial_console_write()
795 	if (ssp->port.sysrq)  in sifive_serial_console_write()
798 		locked = spin_trylock(&ssp->port.lock);  in sifive_serial_console_write()
800 		spin_lock(&ssp->port.lock);  in sifive_serial_console_write()
805 	uart_console_write(&ssp->port, s, count, sifive_serial_console_putchar);  in sifive_serial_console_write()
810 		spin_unlock(&ssp->port.lock);  in sifive_serial_console_write()
822 	if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS)  in sifive_serial_console_setup()
823 		return -ENODEV;  in sifive_serial_console_setup()
825 	ssp = sifive_serial_console_ports[co->index];  in sifive_serial_console_setup()
827 		return -ENODEV;  in sifive_serial_console_setup()
832 	return uart_set_options(&ssp->port, co, baud, parity, bits, flow);  in sifive_serial_console_setup()
843 	.index		= -1,
857 	sifive_serial_console_ports[ssp->port.line] = ssp;  in __ssp_add_console_port()
862 	sifive_serial_console_ports[ssp->port.line] = NULL;  in __ssp_remove_console_port()
918 		return -EPROBE_DEFER;  in sifive_serial_probe()
924 	clk = devm_clk_get_enabled(&pdev->dev, NULL);  in sifive_serial_probe()
926 		dev_err(&pdev->dev, "unable to find controller clock\n");  in sifive_serial_probe()
930 	id = of_alias_get_id(pdev->dev.of_node, "serial");  in sifive_serial_probe()
932 		dev_err(&pdev->dev, "missing aliases entry\n");  in sifive_serial_probe()
938 		dev_err(&pdev->dev, "too many UARTs (%d)\n", id);  in sifive_serial_probe()
939 		return -EINVAL;  in sifive_serial_probe()
943 	ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL);  in sifive_serial_probe()
945 		return -ENOMEM;  in sifive_serial_probe()
947 	ssp->port.dev = &pdev->dev;  in sifive_serial_probe()
948 	ssp->port.type = PORT_SIFIVE_V0;  in sifive_serial_probe()
949 	ssp->port.iotype = UPIO_MEM;  in sifive_serial_probe()
950 	ssp->port.irq = irq;  in sifive_serial_probe()
951 	ssp->port.fifosize = SIFIVE_TX_FIFO_DEPTH;  in sifive_serial_probe()
952 	ssp->port.ops = &sifive_serial_uops;  in sifive_serial_probe()
953 	ssp->port.line = id;  in sifive_serial_probe()
954 	ssp->port.mapbase = mem->start;  in sifive_serial_probe()
955 	ssp->port.membase = base;  in sifive_serial_probe()
956 	ssp->dev = &pdev->dev;  in sifive_serial_probe()
957 	ssp->clk = clk;  in sifive_serial_probe()
958 	ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier;  in sifive_serial_probe()
960 	r = clk_notifier_register(ssp->clk, &ssp->clk_notifier);  in sifive_serial_probe()
962 		dev_err(&pdev->dev, "could not register clock notifier: %d\n",  in sifive_serial_probe()
968 	ssp->port.uartclk = clk_get_rate(ssp->clk);  in sifive_serial_probe()
969 	ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;  in sifive_serial_probe()
984 	r = request_irq(ssp->port.irq, sifive_serial_irq, ssp->port.irqflags,  in sifive_serial_probe()
985 			dev_name(&pdev->dev), ssp);  in sifive_serial_probe()
987 		dev_err(&pdev->dev, "could not attach interrupt: %d\n", r);  in sifive_serial_probe()
993 	r = uart_add_one_port(&sifive_serial_uart_driver, &ssp->port);  in sifive_serial_probe()
995 		dev_err(&pdev->dev, "could not add uart: %d\n", r);  in sifive_serial_probe()
1003 	free_irq(ssp->port.irq, ssp);  in sifive_serial_probe()
1005 	clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);  in sifive_serial_probe()
1015 	uart_remove_one_port(&sifive_serial_uart_driver, &ssp->port);  in sifive_serial_remove()
1016 	free_irq(ssp->port.irq, ssp);  in sifive_serial_remove()
1017 	clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);  in sifive_serial_remove()
1026 	return uart_suspend_port(&sifive_serial_uart_driver, &ssp->port);  in sifive_serial_suspend()
1033 	return uart_resume_port(&sifive_serial_uart_driver, &ssp->port);  in sifive_serial_resume()
1040 	{ .compatible = "sifive,fu540-c000-uart0" },
1041 	{ .compatible = "sifive,uart0" },
1085 MODULE_DESCRIPTION("SiFive UART serial driver");