Lines Matching +full:sifive +full:- +full:blocks

16 	  EDAC is a subsystem along with hardware-specific drivers designed to
17 	  report hardware errors. These are low-level errors that are reported
22 	  The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 	  levels are 0-4 (from low to high) and by default it is set to 2.
44 	tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 	  occurring on your machine in human-readable form.
60 	  Not all machines support hardware-driven error report. Some of those
61 	  provide a BIOS-driven error report mechanism via ACPI, using the
65 	  When this option is enabled, it will disable the hardware-driven
69 	  It should be noticed that keeping both GHES and a hardware-driven
96 	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 	  - inject_word (0..8, 16-bit word of 16-byte section),
98 	  - inject_ecc_vector (hex ecc vector: select bits of inject word)
172 	  E3-1200 based DRAM controllers.
234 	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
249 	  system has non-volatile DIMMs you should also manually
261 	  system has non-volatile DIMMs you should also manually
272 	  micro-server but may appear on others in the future.
280 	  client SoC Integrated Memory Controller using In-Band ECC IP.
281 	  This In-Band ECC is first used on the Elkhart Lake SoC but
323 	tristate "AMD8131 HyperTransport PCI-X Tunnel"
327 	  AMD8131 HyperTransport PCI-X Tunnel chip.
399 	  blocks (TAD, CBC, MCI).
427 	bool "Altera On-Chip RAM ECC"
431 	  Altera On-Chip RAM Memory for Altera SoCs.
476 	bool "Sifive platform EDAC driver"
479 	  Support for error detection and correction on the SiFive SoCs.
496 	tristate "APM X-Gene SoC"
500 	  APM X-Gene family of SOCs.
539 	tristate "ARM DMC-520 ECC"
543 	  SoCs with ARM DMC-520 DRAM controller.
561 	  error detection (in-line ECC in which a section 1/8th of the memory