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/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dmvebu-gated-clock.txt12 -----------------------------------
18 5 pex0 PCIe Cntrl 0
21 17 sdio SDHCI Host
29 -----------------------------------
33 5 pex0 PCIe 0 Clock out
40 17 sdio SDHCI Host
56 -----------------------------------
61 5 pex1 PCIe 1
83 -----------------------------------
84 5 pex1 PCIe 1
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/dma/
Dmoxa,moxart-dma.txt7 - compatible : Must be "moxa,moxart-dma"
8 - reg : Should contain registers location and length
9 - interrupts : Should contain an interrupt-specifier for the sole
11 - #dma-cells : Should be 1, a single cell holding a line request number
16 compatible = "moxa,moxart-dma";
19 #dma-cells = <1>;
26 described in the dma.txt file, using a two-cell specifier for each channel:
35 For example, MMC request line is 5
37 sdhci: sdhci@98e00000 {
38 compatible = "moxa,moxart-sdhci";
[all …]
/Linux-v5.10/drivers/mmc/host/
Dsdhci-of-hlwd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/mmc/host/sdhci-of-hlwd.c
9 * Based on sdhci-of-esdhc.c
21 #include "sdhci-pltfm.h"
24 * Ops and quirks for the Nintendo Wii SDHCI controllers.
30 #define SDHCI_HLWD_WRITE_DELAY 5 /* usecs */
75 { .compatible = "nintendo,hollywood-sdhci" },
82 .name = "sdhci-hlwd",
93 MODULE_DESCRIPTION("Nintendo Wii SDHCI OF driver");
Dsdhci-sirf.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SDHCI support for SiRF primaII and marco SoCs
13 #include <linux/mmc/slot-gpio.h>
14 #include "sdhci-pltfm.h"
29 * 8bit-width enable bit of CSR SD hosts is 3, in sdhci_sirf_set_bus_width()
30 * while stardard hosts use bit 5 in sdhci_sirf_set_bus_width()
42 u32 val = readl(host->ioaddr + reg); in sdhci_sirf_readl_le()
45 (host->mmc->caps & MMC_CAP_UHS_SDR50))) { in sdhci_sirf_readl_le()
64 ret = readw(host->ioaddr + reg); in sdhci_sirf_readw_le()
67 ret = readw(host->ioaddr + SDHCI_HOST_VERSION); in sdhci_sirf_readw_le()
[all …]
Dsdhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
27 #include "sdhci-pltfm.h"
36 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5)
98 #define NVQUIRK_ENABLE_DDR50 BIT(5)
176 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_readw()
178 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && in tegra_sdhci_readw()
184 return readw(host->ioaddr + reg); in tegra_sdhci_readw()
197 pltfm_host->xfer_mode_shadow = val; in tegra_sdhci_writew()
[all …]
/Linux-v5.10/arch/arm/mach-s3c/
Dsetup-sdhci-gpio-s3c24xx.c1 // SPDX-License-Identifier: GPL-2.0
6 // S3C2416 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
8 // Based on mach-s3c64xx/setup-sdhci-gpio.c
17 #include "regs-gpio.h"
18 #include "gpio-samsung.h"
19 #include "gpio-cfg.h"
20 #include "sdhci.h"
24 s3c_gpio_cfgrange_nopull(S3C2410_GPE(5), 2 + width, S3C_GPIO_SFN(2)); in s3c2416_setup_sdhci0_cfg_gpio()
Ds3c6400.c1 // SPDX-License-Identifier: GPL-2.0
31 #include "regs-clock.h"
35 #include "sdhci.h"
36 #include "iic-core.h"
39 #include "onenand-core-s3c64xx.h"
43 /* setup SDHCI */ in s3c6400_map_io()
50 s3c_i2c0_setname("s3c2440-i2c"); in s3c6400_map_io()
52 s3c_device_nand.name = "s3c6400-nand"; in s3c6400_map_io()
54 s3c_onenand_setname("s3c6400-onenand"); in s3c6400_map_io()
55 s3c64xx_onenand1_setname("s3c6400-onenand"); in s3c6400_map_io()
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dmoxart.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* moxart.dtsi - Device Tree Include file for MOXA ART family SoC
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 #address-cells = <1>;
29 #size-cells = <0>;
[all …]
Ds3c64xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,arm1176jzf-s";
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
[all …]
Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
Dqcom-apq8084.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&intc>;
15 reserved-memory {
16 #address-cells = <1>;
[all …]
Darmada-388-helios4.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 /dts-v1/;
11 #include "armada-388.dtsi"
12 #include "armada-38x-solidrun-microsom.dtsi"
25 /* So that mvebu u-boot can update the MAC addresses */
30 stdout-path = "serial0:115200n8";
33 reg_12v: regulator-12v {
34 compatible = "regulator-fixed";
35 regulator-name = "power_brick_12V";
36 regulator-min-microvolt = <12000000>;
[all …]
Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
Dstih418-b2199.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "st,stih418-b2199", "st,stih418";
15 stdout-path = &sbc_serial0;
29 compatible = "gpio-leds";
33 linux,default-trigger = "heartbeat";
37 default-state = "off";
70 clock-frequency = <100000>;
71 st,i2c-min-scl-pulse-width-us = <0>;
[all …]
/Linux-v5.10/arch/arm/mach-mmp/
Dmmp2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-mmp/mmp2.c
18 #include <asm/hardware/cache-tauros2.h>
21 #include "addr-map.h"
22 #include "regs-apbc.h"
28 #include "pm-mmp2.h"
137 /* on-chip devices */
138 MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5);
139 MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21);
140 MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23);
[all …]
/Linux-v5.10/drivers/clk/samsung/
Dclk-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
17 #include "clk-pll.h"
98 /* S3C6400-specific parent clocks. */
103 /* S3C6410-specific parent clocks. */
142 MUX(MOUT_UHOST, "mout_uhost", uhost_p6400, CLK_SRC, 5, 2),
150 MUX(MOUT_UHOST, "mout_uhost", uhost_p6410, CLK_SRC, 5, 2),
216 GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5),
240 GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5),
[all …]
Dclk-s3c2443.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/s3c2443.h>
18 #include "clk-pll.h"
89 { .val = 2, .div = 5 },
92 { .val = 5, .div = 11 },
121 GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0),
122 GATE(HCLK_USBH, "usb-host", "hclk", HCLKCON, 11, 0, 0),
124 GATE(HCLK_DMA5, "dma5", "hclk", HCLKCON, 5, CLK_IGNORE_UNUSED, 0),
152 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
[all …]
/Linux-v5.10/arch/arm64/boot/dts/marvell/
Darmada-37xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
34 psci-area@4000000 {
[all …]
/Linux-v5.10/drivers/staging/mt7621-dts/
Dmt7621.dtsi1 #include <dt-bindings/interrupt-controller/mips-gic.h>
2 #include <dt-bindings/gpio/gpio.h>
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mediatek,mt7621-soc";
20 #address-cells = <0>;
21 #interrupt-cells = <1>;
22 interrupt-controller;
23 compatible = "mti,cpu-interrupt-controller";
31 #clock-cells = <0>;
[all …]
/Linux-v5.10/arch/powerpc/boot/dts/
Dwii.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2008-2009 The GameCube Linux Team
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
15 * This is commented-out for now.
25 #address-cells = <1>;
26 #size-cells = <1>;
29 bootargs = "root=/dev/mmcblk0p2 rootwait udbg-immortal";
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/pinctrl/
Dpinctrl_spear.txt4 - compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
9 - reg : Address range of the pinctrl registers
10 - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
11 - Its values for SPEAr300:
12 - NAND_MODE : <0>
13 - NOR_MODE : <1>
[all …]
/Linux-v5.10/include/linux/platform_data/
Dpxa_sdhci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * PXA Platform - SDHCI platform data definitions
17 /* card always wired to host, like on-chip emmc */
19 /* Board design supports 8-bit data on SD/SDIO BUS */
23 * struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
26 * mmp2: each step is roughly 100ps, 5bits width
/Linux-v5.10/arch/arm64/boot/dts/nvidia/
Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/reset/tegra234-reset.h>
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 compatible = "simple-bus";
16 #address-cells = <1>;
[all …]
/Linux-v5.10/drivers/phy/intel/
Dphy-intel-keembay-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #define DLL_RDY_MASK BIT(5)
66 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
69 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in keembay_emmc_phy_power()
73 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
99 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
106 udelay(5); in keembay_emmc_phy_power()
108 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
[all …]
Dphy-intel-lgm-emmc.c1 // SPDX-License-Identifier: GPL-2.0
64 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
67 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
75 rate = clk_get_rate(priv->emmcclk); in intel_emmc_phy_power()
78 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); in intel_emmc_phy_power()
86 udelay(5); in intel_emmc_phy_power()
88 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
91 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
96 * According to the user manual, it asks driver to wait 5us for in intel_emmc_phy_power()
102 ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG, in intel_emmc_phy_power()
[all …]

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