Lines Matching +full:sdhci +full:- +full:5
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
21 compatible = "nvidia,tegra30-pcie";
26 reg-names = "pads", "afi", "cs";
29 interrupt-names = "intr", "msi";
31 #interrupt-cells = <1>;
32 interrupt-map-mask = <0 0 0 0>;
33 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
35 bus-range = <0x00 0xff>;
36 #address-cells = <3>;
37 #size-cells = <2>;
43 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
50 clock-names = "pex", "afi", "pll_e", "cml";
54 reset-names = "pex", "afi", "pcie_x";
59 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
61 bus-range = <0x00 0xff>;
64 #address-cells = <3>;
65 #size-cells = <2>;
68 nvidia,num-lanes = <2>;
73 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
75 bus-range = <0x00 0xff>;
78 #address-cells = <3>;
79 #size-cells = <2>;
82 nvidia,num-lanes = <2>;
87 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
89 bus-range = <0x00 0xff>;
92 #address-cells = <3>;
93 #size-cells = <2>;
96 nvidia,num-lanes = <2>;
101 compatible = "mmio-sram";
103 #address-cells = <1>;
104 #size-cells = <1>;
114 compatible = "nvidia,tegra30-host1x";
118 interrupt-names = "syncpt", "host1x";
120 clock-names = "host1x";
122 reset-names = "host1x";
125 #address-cells = <1>;
126 #size-cells = <1>;
131 compatible = "nvidia,tegra30-mpe";
136 reset-names = "mpe";
142 compatible = "nvidia,tegra30-vi";
147 reset-names = "vi";
153 compatible = "nvidia,tegra30-epp";
158 reset-names = "epp";
164 compatible = "nvidia,tegra30-isp";
169 reset-names = "isp";
175 compatible = "nvidia,tegra30-gr2d";
180 reset-names = "2d";
186 compatible = "nvidia,tegra30-gr3d";
190 clock-names = "3d", "3d2";
193 reset-names = "3d", "3d2";
200 compatible = "nvidia,tegra30-dc";
205 clock-names = "dc", "parent";
207 reset-names = "dc";
219 compatible = "nvidia,tegra30-dc";
224 clock-names = "dc", "parent";
226 reset-names = "dc";
238 compatible = "nvidia,tegra30-hdmi";
243 clock-names = "hdmi", "parent";
245 reset-names = "hdmi";
250 compatible = "nvidia,tegra30-tvo";
258 compatible = "nvidia,tegra30-dsi";
262 clock-names = "dsi", "parent";
264 reset-names = "dsi";
269 compatible = "nvidia,tegra30-dsi";
273 clock-names = "dsi", "parent";
275 reset-names = "dsi";
281 compatible = "arm,cortex-a9-twd-timer";
283 interrupt-parent = <&intc>;
289 intc: interrupt-controller@50041000 {
290 compatible = "arm,cortex-a9-gic";
293 interrupt-controller;
294 #interrupt-cells = <3>;
295 interrupt-parent = <&intc>;
298 cache-controller@50043000 {
299 compatible = "arm,pl310-cache";
301 arm,data-latency = <6 6 2>;
302 arm,tag-latency = <5 5 2>;
303 cache-unified;
304 cache-level = <2>;
307 lic: interrupt-controller@60004000 {
308 compatible = "nvidia,tegra30-ictlr";
314 interrupt-controller;
315 #interrupt-cells = <3>;
316 interrupt-parent = <&intc>;
320 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
332 compatible = "nvidia,tegra30-car";
334 #clock-cells = <1>;
335 #reset-cells = <1>;
338 flow-controller@60007000 {
339 compatible = "nvidia,tegra30-flowctrl";
344 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
380 reset-names = "dma";
381 #dma-cells = <1>;
385 compatible = "nvidia,tegra30-ahb";
390 compatible = "nvidia,tegra30-actmon";
395 clock-names = "actmon", "emc";
397 reset-names = "actmon";
401 compatible = "nvidia,tegra30-gpio";
411 #gpio-cells = <2>;
412 gpio-controller;
413 #interrupt-cells = <2>;
414 interrupt-controller;
416 gpio-ranges = <&pinmux 0 0 248>;
421 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
425 <0x6001c200 0x100>, /* Post-processing Engine */
431 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
435 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
437 interrupt-names = "sync-token", "bsev", "sxe";
439 reset-names = "vde", "mc";
445 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
451 compatible = "nvidia,tegra30-pinmux";
460 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
462 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
465 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
467 reg-shift = <2>;
471 reset-names = "serial";
473 dma-names = "rx", "tx";
478 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
480 reg-shift = <2>;
484 reset-names = "serial";
486 dma-names = "rx", "tx";
491 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
493 reg-shift = <2>;
497 reset-names = "serial";
499 dma-names = "rx", "tx";
504 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
506 reg-shift = <2>;
510 reset-names = "serial";
512 dma-names = "rx", "tx";
517 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
519 reg-shift = <2>;
523 reset-names = "serial";
525 dma-names = "rx", "tx";
530 compatible = "nvidia,tegra30-gmi";
532 #address-cells = <2>;
533 #size-cells = <1>;
536 clock-names = "gmi";
538 reset-names = "gmi";
543 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
545 #pwm-cells = <2>;
548 reset-names = "pwm";
553 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
560 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
563 #address-cells = <1>;
564 #size-cells = <0>;
567 clock-names = "div-clk", "fast-clk";
569 reset-names = "i2c";
571 dma-names = "rx", "tx";
576 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
579 #address-cells = <1>;
580 #size-cells = <0>;
583 clock-names = "div-clk", "fast-clk";
585 reset-names = "i2c";
587 dma-names = "rx", "tx";
592 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
595 #address-cells = <1>;
596 #size-cells = <0>;
599 clock-names = "div-clk", "fast-clk";
601 reset-names = "i2c";
603 dma-names = "rx", "tx";
608 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
611 #address-cells = <1>;
612 #size-cells = <0>;
616 reset-names = "i2c";
617 clock-names = "div-clk", "fast-clk";
619 dma-names = "rx", "tx";
624 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
627 #address-cells = <1>;
628 #size-cells = <0>;
631 clock-names = "div-clk", "fast-clk";
633 reset-names = "i2c";
635 dma-names = "rx", "tx";
640 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
643 #address-cells = <1>;
644 #size-cells = <0>;
647 reset-names = "spi";
649 dma-names = "rx", "tx";
654 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
657 #address-cells = <1>;
658 #size-cells = <0>;
661 reset-names = "spi";
663 dma-names = "rx", "tx";
668 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
671 #address-cells = <1>;
672 #size-cells = <0>;
675 reset-names = "spi";
677 dma-names = "rx", "tx";
682 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
685 #address-cells = <1>;
686 #size-cells = <0>;
689 reset-names = "spi";
691 dma-names = "rx", "tx";
696 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
699 #address-cells = <1>;
700 #size-cells = <0>;
703 reset-names = "spi";
705 dma-names = "rx", "tx";
710 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
713 #address-cells = <1>;
714 #size-cells = <0>;
717 reset-names = "spi";
719 dma-names = "rx", "tx";
724 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
729 reset-names = "kbc";
734 compatible = "nvidia,tegra30-pmc";
737 clock-names = "pclk", "clk32k_in";
738 #clock-cells = <1>;
741 mc: memory-controller@7000f000 {
742 compatible = "nvidia,tegra30-mc";
745 clock-names = "mc";
749 #iommu-cells = <1>;
750 #reset-cells = <1>;
753 memory-controller@7000f400 {
754 compatible = "nvidia,tegra30-emc";
759 nvidia,memory-controller = <&mc>;
763 compatible = "nvidia,tegra30-efuse";
766 clock-names = "fuse";
768 reset-names = "fuse";
772 compatible = "nvidia,tegra30-hda";
778 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
782 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
787 compatible = "nvidia,tegra30-ahub";
793 clock-names = "d_audio", "apbif";
805 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
812 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
815 #address-cells = <1>;
816 #size-cells = <1>;
819 compatible = "nvidia,tegra30-i2s";
821 nvidia,ahub-cif-ids = <4 4>;
824 reset-names = "i2s";
829 compatible = "nvidia,tegra30-i2s";
831 nvidia,ahub-cif-ids = <5 5>;
834 reset-names = "i2s";
839 compatible = "nvidia,tegra30-i2s";
841 nvidia,ahub-cif-ids = <6 6>;
844 reset-names = "i2s";
849 compatible = "nvidia,tegra30-i2s";
851 nvidia,ahub-cif-ids = <7 7>;
854 reset-names = "i2s";
859 compatible = "nvidia,tegra30-i2s";
861 nvidia,ahub-cif-ids = <8 8>;
864 reset-names = "i2s";
870 compatible = "nvidia,tegra30-sdhci";
874 clock-names = "sdhci";
876 reset-names = "sdhci";
881 compatible = "nvidia,tegra30-sdhci";
885 clock-names = "sdhci";
887 reset-names = "sdhci";
892 compatible = "nvidia,tegra30-sdhci";
896 clock-names = "sdhci";
898 reset-names = "sdhci";
903 compatible = "nvidia,tegra30-sdhci";
907 clock-names = "sdhci";
909 reset-names = "sdhci";
914 compatible = "nvidia,tegra30-ehci", "usb-ehci";
920 reset-names = "usb";
921 nvidia,needs-double-reset;
926 phy1: usb-phy@7d000000 {
927 compatible = "nvidia,tegra30-usb-phy";
934 clock-names = "reg", "pll_u", "utmi-pads";
936 reset-names = "usb", "utmi-pads";
937 #phy-cells = <0>;
938 nvidia,hssync-start-delay = <9>;
939 nvidia,idle-wait-delay = <17>;
940 nvidia,elastic-limit = <16>;
941 nvidia,term-range-adj = <6>;
942 nvidia,xcvr-setup = <51>;
943 nvidia,xcvr-setup-use-fuses;
944 nvidia,xcvr-lsfslew = <1>;
945 nvidia,xcvr-lsrslew = <1>;
946 nvidia,xcvr-hsslew = <32>;
947 nvidia,hssquelch-level = <2>;
948 nvidia,hsdiscon-level = <5>;
949 nvidia,has-utmi-pad-registers;
954 compatible = "nvidia,tegra30-ehci", "usb-ehci";
960 reset-names = "usb";
965 phy2: usb-phy@7d004000 {
966 compatible = "nvidia,tegra30-usb-phy";
973 clock-names = "reg", "pll_u", "utmi-pads";
975 reset-names = "usb", "utmi-pads";
976 #phy-cells = <0>;
977 nvidia,hssync-start-delay = <9>;
978 nvidia,idle-wait-delay = <17>;
979 nvidia,elastic-limit = <16>;
980 nvidia,term-range-adj = <6>;
981 nvidia,xcvr-setup = <51>;
982 nvidia,xcvr-setup-use-fuses;
983 nvidia,xcvr-lsfslew = <2>;
984 nvidia,xcvr-lsrslew = <2>;
985 nvidia,xcvr-hsslew = <32>;
986 nvidia,hssquelch-level = <2>;
987 nvidia,hsdiscon-level = <5>;
992 compatible = "nvidia,tegra30-ehci", "usb-ehci";
998 reset-names = "usb";
1003 phy3: usb-phy@7d008000 {
1004 compatible = "nvidia,tegra30-usb-phy";
1011 clock-names = "reg", "pll_u", "utmi-pads";
1013 reset-names = "usb", "utmi-pads";
1014 #phy-cells = <0>;
1015 nvidia,hssync-start-delay = <0>;
1016 nvidia,idle-wait-delay = <17>;
1017 nvidia,elastic-limit = <16>;
1018 nvidia,term-range-adj = <6>;
1019 nvidia,xcvr-setup = <51>;
1020 nvidia,xcvr-setup-use-fuses;
1021 nvidia,xcvr-lsfslew = <2>;
1022 nvidia,xcvr-lsrslew = <2>;
1023 nvidia,xcvr-hsslew = <32>;
1024 nvidia,hssquelch-level = <2>;
1025 nvidia,hsdiscon-level = <5>;
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1035 compatible = "arm,cortex-a9";
1042 compatible = "arm,cortex-a9";
1049 compatible = "arm,cortex-a9";
1056 compatible = "arm,cortex-a9";
1063 compatible = "arm,cortex-a9-pmu";
1068 interrupt-affinity = <&{/cpus/cpu@0}>,