Lines Matching +full:sdhci +full:- +full:5
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
21 compatible = "nvidia,tegra114-host1x";
25 interrupt-names = "syncpt", "host1x";
27 clock-names = "host1x";
29 reset-names = "host1x";
32 #address-cells = <1>;
33 #size-cells = <1>;
38 compatible = "nvidia,tegra114-gr2d";
43 reset-names = "2d";
49 compatible = "nvidia,tegra114-gr3d";
53 reset-names = "3d";
59 compatible = "nvidia,tegra114-dc";
64 clock-names = "dc", "parent";
66 reset-names = "dc";
78 compatible = "nvidia,tegra114-dc";
83 clock-names = "dc", "parent";
85 reset-names = "dc";
97 compatible = "nvidia,tegra114-hdmi";
102 clock-names = "hdmi", "parent";
104 reset-names = "hdmi";
109 compatible = "nvidia,tegra114-dsi";
114 clock-names = "dsi", "lp", "parent";
116 reset-names = "dsi";
117 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
120 #address-cells = <1>;
121 #size-cells = <0>;
125 compatible = "nvidia,tegra114-dsi";
130 clock-names = "dsi", "lp", "parent";
132 reset-names = "dsi";
133 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
136 #address-cells = <1>;
137 #size-cells = <0>;
141 gic: interrupt-controller@50041000 {
142 compatible = "arm,cortex-a15-gic";
143 #interrupt-cells = <3>;
144 interrupt-controller;
151 interrupt-parent = <&gic>;
154 lic: interrupt-controller@60004000 {
155 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
161 interrupt-controller;
162 #interrupt-cells = <3>;
163 interrupt-parent = <&gic>;
167 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
179 compatible = "nvidia,tegra114-car";
181 #clock-cells = <1>;
182 #reset-cells = <1>;
185 flow-controller@60007000 {
186 compatible = "nvidia,tegra114-flowctrl";
191 compatible = "nvidia,tegra114-apbdma";
227 reset-names = "dma";
228 #dma-cells = <1>;
232 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
237 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
247 #gpio-cells = <2>;
248 gpio-controller;
249 #interrupt-cells = <2>;
250 interrupt-controller;
252 gpio-ranges = <&pinmux 0 0 246>;
257 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
263 compatible = "nvidia,tegra114-pinmux";
272 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
274 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
277 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
279 reg-shift = <2>;
283 reset-names = "serial";
285 dma-names = "rx", "tx";
290 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
292 reg-shift = <2>;
296 reset-names = "serial";
298 dma-names = "rx", "tx";
303 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
305 reg-shift = <2>;
309 reset-names = "serial";
311 dma-names = "rx", "tx";
316 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
318 reg-shift = <2>;
322 reset-names = "serial";
324 dma-names = "rx", "tx";
329 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
331 #pwm-cells = <2>;
334 reset-names = "pwm";
339 compatible = "nvidia,tegra114-i2c";
342 #address-cells = <1>;
343 #size-cells = <0>;
345 clock-names = "div-clk";
347 reset-names = "i2c";
349 dma-names = "rx", "tx";
354 compatible = "nvidia,tegra114-i2c";
357 #address-cells = <1>;
358 #size-cells = <0>;
360 clock-names = "div-clk";
362 reset-names = "i2c";
364 dma-names = "rx", "tx";
369 compatible = "nvidia,tegra114-i2c";
372 #address-cells = <1>;
373 #size-cells = <0>;
375 clock-names = "div-clk";
377 reset-names = "i2c";
379 dma-names = "rx", "tx";
384 compatible = "nvidia,tegra114-i2c";
387 #address-cells = <1>;
388 #size-cells = <0>;
390 clock-names = "div-clk";
392 reset-names = "i2c";
394 dma-names = "rx", "tx";
399 compatible = "nvidia,tegra114-i2c";
402 #address-cells = <1>;
403 #size-cells = <0>;
405 clock-names = "div-clk";
407 reset-names = "i2c";
409 dma-names = "rx", "tx";
414 compatible = "nvidia,tegra114-spi";
417 #address-cells = <1>;
418 #size-cells = <0>;
420 clock-names = "spi";
422 reset-names = "spi";
424 dma-names = "rx", "tx";
429 compatible = "nvidia,tegra114-spi";
432 #address-cells = <1>;
433 #size-cells = <0>;
435 clock-names = "spi";
437 reset-names = "spi";
439 dma-names = "rx", "tx";
444 compatible = "nvidia,tegra114-spi";
447 #address-cells = <1>;
448 #size-cells = <0>;
450 clock-names = "spi";
452 reset-names = "spi";
454 dma-names = "rx", "tx";
459 compatible = "nvidia,tegra114-spi";
462 #address-cells = <1>;
463 #size-cells = <0>;
465 clock-names = "spi";
467 reset-names = "spi";
469 dma-names = "rx", "tx";
474 compatible = "nvidia,tegra114-spi";
477 #address-cells = <1>;
478 #size-cells = <0>;
480 clock-names = "spi";
482 reset-names = "spi";
484 dma-names = "rx", "tx";
489 compatible = "nvidia,tegra114-spi";
492 #address-cells = <1>;
493 #size-cells = <0>;
495 clock-names = "spi";
497 reset-names = "spi";
499 dma-names = "rx", "tx";
504 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
511 compatible = "nvidia,tegra114-kbc";
516 reset-names = "kbc";
521 compatible = "nvidia,tegra114-pmc";
524 clock-names = "pclk", "clk32k_in";
525 #clock-cells = <1>;
529 compatible = "nvidia,tegra114-efuse";
532 clock-names = "fuse";
534 reset-names = "fuse";
537 mc: memory-controller@70019000 {
538 compatible = "nvidia,tegra114-mc";
541 clock-names = "mc";
545 #iommu-cells = <1>;
549 compatible = "nvidia,tegra114-ahub";
556 clock-names = "d_audio", "apbif";
570 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
583 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
588 #address-cells = <1>;
589 #size-cells = <1>;
592 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
594 nvidia,ahub-cif-ids = <4 4>;
597 reset-names = "i2s";
602 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
604 nvidia,ahub-cif-ids = <5 5>;
607 reset-names = "i2s";
612 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
614 nvidia,ahub-cif-ids = <6 6>;
617 reset-names = "i2s";
622 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
624 nvidia,ahub-cif-ids = <7 7>;
627 reset-names = "i2s";
632 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
634 nvidia,ahub-cif-ids = <8 8>;
637 reset-names = "i2s";
643 compatible = "nvidia,tegra114-mipi";
646 #nvidia,mipi-calibrate-cells = <1>;
650 compatible = "nvidia,tegra114-sdhci";
654 clock-names = "sdhci";
656 reset-names = "sdhci";
661 compatible = "nvidia,tegra114-sdhci";
665 clock-names = "sdhci";
667 reset-names = "sdhci";
672 compatible = "nvidia,tegra114-sdhci";
676 clock-names = "sdhci";
678 reset-names = "sdhci";
683 compatible = "nvidia,tegra114-sdhci";
687 clock-names = "sdhci";
689 reset-names = "sdhci";
694 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
700 reset-names = "usb";
705 phy1: usb-phy@7d000000 {
706 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
713 clock-names = "reg", "pll_u", "utmi-pads";
715 reset-names = "usb", "utmi-pads";
716 #phy-cells = <0>;
717 nvidia,hssync-start-delay = <0>;
718 nvidia,idle-wait-delay = <17>;
719 nvidia,elastic-limit = <16>;
720 nvidia,term-range-adj = <6>;
721 nvidia,xcvr-setup = <9>;
722 nvidia,xcvr-lsfslew = <0>;
723 nvidia,xcvr-lsrslew = <3>;
724 nvidia,hssquelch-level = <2>;
725 nvidia,hsdiscon-level = <5>;
726 nvidia,xcvr-hsslew = <12>;
727 nvidia,has-utmi-pad-registers;
732 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
738 reset-names = "usb";
743 phy3: usb-phy@7d008000 {
744 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
751 clock-names = "reg", "pll_u", "utmi-pads";
753 reset-names = "usb", "utmi-pads";
754 #phy-cells = <0>;
755 nvidia,hssync-start-delay = <0>;
756 nvidia,idle-wait-delay = <17>;
757 nvidia,elastic-limit = <16>;
758 nvidia,term-range-adj = <6>;
759 nvidia,xcvr-setup = <9>;
760 nvidia,xcvr-lsfslew = <0>;
761 nvidia,xcvr-lsrslew = <3>;
762 nvidia,hssquelch-level = <2>;
763 nvidia,hsdiscon-level = <5>;
764 nvidia,xcvr-hsslew = <12>;
769 #address-cells = <1>;
770 #size-cells = <0>;
774 compatible = "arm,cortex-a15";
780 compatible = "arm,cortex-a15";
786 compatible = "arm,cortex-a15";
792 compatible = "arm,cortex-a15";
798 compatible = "arm,armv7-timer";
808 interrupt-parent = <&gic>;