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/Linux-v5.10/Documentation/devicetree/bindings/display/rockchip/
Drockchip-vop.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC display controller (VOP)
10 VOP (Video Output Processor) is the display controller for the Rockchip
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,px30-vop-big
22 - rockchip,px30-vop-lit
[all …]
Drockchip-drm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-drm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DRM master device
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The Rockchip DRM master device is a virtual device needed to list all
15 vop devices or other display interface nodes that comprise the
20 const: rockchip,display-subsystem
[all …]
Drockchip-lvds.txt1 Rockchip RK3288 LVDS interface
5 - compatible: matching the soc type, one of
6 - "rockchip,rk3288-lvds";
7 - "rockchip,px30-lvds";
9 - reg: physical base address of the controller and length
11 - clocks: must include clock specifiers corresponding to entries in the
12 clock-names property.
13 - clock-names: must contain "pclk_lvds"
15 - avdd1v0-supply: regulator phandle for 1.0V analog power
16 - avdd1v8-supply: regulator phandle for 1.8V analog power
[all …]
Danalogix_dp-rockchip.txt1 Rockchip RK3288 specific extensions to the Analogix Display Port
5 - compatible: "rockchip,rk3288-dp",
6 "rockchip,rk3399-edp";
8 - reg: physical base address of the controller and length
10 - clocks: from common clock binding: handle to dp clock.
13 - clock-names: from common clock binding:
16 - resets: Must contain an entry for each entry in reset-names.
19 - pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
20 - pinctrl-0: pin-control mode. should be <&edp_hpd>
22 - reset-names: Must include the name "dp"
[all …]
Dcdn-dp-rockchip.txt1 Rockchip RK3399 specific extensions to the cdn Display Port
5 - compatible: must be "rockchip,rk3399-cdn-dp"
7 - reg: physical base address of the controller and length
9 - clocks: from common clock binding: handle to dp clock.
11 - clock-names: from common clock binding:
12 Required elements: "core-clk" "pclk" "spdif" "grf"
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string of reset names
17 - power-domains : power-domain property defined with a phandle
19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
[all …]
Ddw_mipi_dsi_rockchip.txt1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
5 - #address-cells: Should be <1>.
6 - #size-cells: Should be <0>.
7 - compatible: one of
8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11 - reg: Represent the physical address range of the controller.
12 - interrupts: Represent the controller's interrupt to the CPU(s).
13 - clocks, clock-names: Phandles to the controller's pll reference
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/pwm/
Dpwm-rockchip.txt1 Rockchip PWM controller
4 - compatible: should be "rockchip,<name>-pwm"
5 "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs
6 "rockchip,rk3288-pwm": found on RK3288 SOC
7 "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC
8 "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC
9 - reg: physical base address and length of the controller's registers
10 - clocks: See ../clock/clock-bindings.txt
11 - For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399):
12 - There is one clock that's used both to derive the functional clock
[all …]
/Linux-v5.10/drivers/gpu/drm/rockchip/
Danalogix_dp-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip SoC DP (Display Port) interface driver.
5 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
46 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
48 * @lcdsel_big: reg value of selecting vop big for eDP
49 * @lcdsel_lit: reg value of selecting vop little for eDP
78 reset_control_assert(dp->rst); in rockchip_dp_pre_init()
[all …]
Drockchip_vop_reg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
424 * hs_start interrupt fires at frame-start, so serves
520 * hs_start interrupt fires at frame-start, so serves
884 * rk3399 vop big windows register layout is same as rk3288, but we
1039 { .compatible = "rockchip,rk3036-vop",
1041 { .compatible = "rockchip,rk3126-vop",
1043 { .compatible = "rockchip,px30-vop-big",
1045 { .compatible = "rockchip,px30-vop-lit",
[all …]
Drockchip_lvds.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
5 * Mark Yao <mark.yao@rock-chips.com>
6 * Sandy Huang <hjc@rock-chips.com>
45 * rockchip_lvds_soc_data - rockchip lvds Soc private data
74 writel_relaxed(val, lvds->regs + offset); in rk3288_writel()
75 if (lvds->output == DISPLAY_OUTPUT_LVDS) in rk3288_writel()
77 writel_relaxed(val, lvds->regs + offset + RK3288_LVDS_CH1_OFFSET); in rk3288_writel()
82 if (strncmp(s, "jeida-18", 8) == 0) in rockchip_lvds_name_to_format()
84 else if (strncmp(s, "jeida-24", 8) == 0) in rockchip_lvds_name_to_format()
[all …]
Drockchip_drm_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
9 #include <linux/dma-mapping.h>
10 #include <linux/dma-iommu.h>
31 #define DRIVER_NAME "rockchip"
32 #define DRIVER_DESC "RockChip Soc DRM"
48 struct rockchip_drm_private *private = drm_dev->dev_private; in rockchip_drm_dma_attach_device()
54 ret = iommu_attach_device(private->domain, dev); in rockchip_drm_dma_attach_device()
66 struct rockchip_drm_private *private = drm_dev->dev_private; in rockchip_drm_dma_detach_device()
[all …]
Drockchip_drm_vop.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
42 #define VOP_WIN_SET(vop, win, name, v) \ argument
43 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
44 #define VOP_SCL_SET(vop, win, name, v) \ argument
45 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
46 #define VOP_SCL_SET_EXT(vop, win, name, v) \ argument
47 vop_reg_set(vop, &win->phy->scl->ext->name, \
48 win->base, ~0, v, #name)
[all …]
Ddw_hdmi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
56 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
58 * @lcdsel_big: reg value of selecting vop big for HDMI
59 * @lcdsel_lit: reg value of selecting vop little for HDMI
191 struct device_node *np = hdmi->dev->of_node; in rockchip_hdmi_parse_dt()
193 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_hdmi_parse_dt()
194 if (IS_ERR(hdmi->regmap)) { in rockchip_hdmi_parse_dt()
195 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n"); in rockchip_hdmi_parse_dt()
196 return PTR_ERR(hdmi->regmap); in rockchip_hdmi_parse_dt()
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
14 compatible = "rockchip,rk3188";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
[all …]
Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
14 compatible = "rockchip,rk3066a";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
[all …]
Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 compatible = "rockchip,rk3036";
[all …]
Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
[all …]
Drk322x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
[all …]
Drk3036-kylin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
8 model = "Rockchip RK3036 KylinBoard";
9 compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";
16 leds: gpio-leds {
17 compatible = "gpio-leds";
19 work_led: led-0 {
22 pinctrl-names = "default";
23 pinctrl-0 = <&led_ctl>;
27 sdio_pwrseq: sdio-pwrseq {
[all …]
Drk3229-xms6.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/input/input.h>
10 compatible = "mecer,xms6", "rockchip,rk3229";
17 dc_12v: dc-12v-regulator {
18 compatible = "regulator-fixed";
19 regulator-name = "dc_12v";
20 regulator-always-on;
21 regulator-boot-on;
22 regulator-min-microvolt = <12000000>;
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/power/
Drockchip-io-domain.txt1 Rockchip SRAM for IO Voltage Domains:
2 -------------------------------------
4 IO domain voltages on some Rockchip SoCs are variable but need to be
9 - If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then
18 - any logic for deciding what voltage we should set regulators to
19 - any logic for deciding whether regulators (or internal SoC blocks)
33 - compatible: should be one of:
34 - "rockchip,px30-io-voltage-domain" for px30
35 - "rockchip,px30-pmu-io-voltage-domain" for px30 pmu-domains
36 - "rockchip,rk3188-io-voltage-domain" for rk3188
[all …]
/Linux-v5.10/arch/arm64/boot/dts/rockchip/
Drk3368-r88.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
11 model = "Rockchip R88";
12 compatible = "rockchip,r88", "rockchip,rk3368";
15 stdout-path = "serial2:115200n8";
23 emmc_pwrseq: emmc-pwrseq {
24 compatible = "mmc-pwrseq-emmc";
25 pinctrl-0 = <&emmc_reset>;
26 pinctrl-names = "default";
[all …]
Drk3318-a95x-z2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include <dt-bindings/input/input.h>
9 compatible = "zkmagic,a95x-z2", "rockchip,rk3318";
12 stdout-path = "serial2:1500000n8";
15 adc-keys {
16 compatible = "adc-keys";
17 io-channels = <&saradc 0>;
18 io-channel-names = "buttons";
19 keyup-threshold-microvolt = <1800000>;
[all …]
Drk3328-a1.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
2 // Copyright (c) 2017-2019 Arm Ltd.
4 /dts-v1/;
9 compatible = "azw,beelink-a1", "rockchip,rk3328";
15 * /-------
16 * L / o <- Gnd
17 * e / o <-- Rx
18 * f / o <--- Tx
19 * t / o <---- +3.3v
23 stdout-path = "serial2:1500000n8";
[all …]
Drk3328-rock64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "pine64,rock64", "rockchip,rk3328";
14 stdout-path = "serial2:1500000n8";
17 gmac_clkin: external-gmac-clock {
18 compatible = "fixed-clock";
19 clock-frequency = <125000000>;
20 clock-output-names = "gmac_clkin";
21 #clock-cells = <0>;
24 vcc_sd: sdmmc-regulator {
[all …]

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