1Rockchip specific extensions to the Synopsys Designware MIPI DSI
2================================
3
4Required properties:
5- #address-cells: Should be <1>.
6- #size-cells: Should be <0>.
7- compatible: one of
8	"rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9	"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10	"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11- reg: Represent the physical address range of the controller.
12- interrupts: Represent the controller's interrupt to the CPU(s).
13- clocks, clock-names: Phandles to the controller's pll reference
14  clock(ref) when using an internal dphy and APB clock(pclk).
15  For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
16  are required. As described in [1].
17- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
18- ports: contain a port node with endpoint definitions as defined in [2].
19  For vopb,set the reg = <0> and set the reg = <1> for vopl.
20- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
21- video port 1 for either a panel or subsequent encoder
22
23Optional properties:
24- phys: from general PHY binding: the phandle for the PHY device.
25- phy-names: Should be "dphy" if phys references an external phy.
26- power-domains: a phandle to mipi dsi power domain node.
27- resets: list of phandle + reset specifier pairs, as described in [3].
28- reset-names: string reset name, must be "apb".
29
30[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
31[2] Documentation/devicetree/bindings/media/video-interfaces.txt
32[3] Documentation/devicetree/bindings/reset/reset.txt
33
34Example:
35	mipi_dsi: mipi@ff960000 {
36		#address-cells = <1>;
37		#size-cells = <0>;
38		compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
39		reg = <0xff960000 0x4000>;
40		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
41		clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
42		clock-names = "ref", "pclk";
43		resets = <&cru SRST_MIPIDSI0>;
44		reset-names = "apb";
45		rockchip,grf = <&grf>;
46
47		ports {
48			#address-cells = <1>;
49			#size-cells = <0>;
50
51			mipi_in: port@0 {
52				reg = <0>;
53				#address-cells = <1>;
54				#size-cells = <0>;
55
56				mipi_in_vopb: endpoint@0 {
57					reg = <0>;
58					remote-endpoint = <&vopb_out_mipi>;
59				};
60				mipi_in_vopl: endpoint@1 {
61					reg = <1>;
62					remote-endpoint = <&vopl_out_mipi>;
63				};
64			};
65
66			mipi_out: port@1 {
67				reg = <1>;
68				#address-cells = <1>;
69				#size-cells = <0>;
70
71				mipi_out_panel: endpoint {
72					remote-endpoint = <&panel_in_mipi>;
73				};
74			};
75		};
76
77		panel {
78			compatible ="boe,tv080wum-nl0";
79			reg = <0>;
80
81			enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
82			pinctrl-names = "default";
83			pinctrl-0 = <&lcd_en>;
84			backlight = <&backlight>;
85
86			port {
87				panel_in_mipi: endpoint {
88					remote-endpoint = <&mipi_out_panel>;
89				};
90			};
91		};
92	};
93