Lines Matching +full:rockchip +full:- +full:vop
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
14 compatible = "rockchip,rk3188";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
26 clock-latency = <40000>;
28 operating-points-v2 = <&cpu0_opp_table>;
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
36 operating-points-v2 = <&cpu0_opp_table>;
41 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
44 operating-points-v2 = <&cpu0_opp_table>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
52 operating-points-v2 = <&cpu0_opp_table>;
58 compatible = "operating-points-v2";
59 opp-shared;
61 opp-312000000 {
62 opp-hz = /bits/ 64 <312000000>;
63 opp-microvolt = <875000>;
64 clock-latency-ns = <40000>;
66 opp-504000000 {
67 opp-hz = /bits/ 64 <504000000>;
68 opp-microvolt = <925000>;
70 opp-600000000 {
71 opp-hz = /bits/ 64 <600000000>;
72 opp-microvolt = <950000>;
73 opp-suspend;
75 opp-816000000 {
76 opp-hz = /bits/ 64 <816000000>;
77 opp-microvolt = <975000>;
79 opp-1008000000 {
80 opp-hz = /bits/ 64 <1008000000>;
81 opp-microvolt = <1075000>;
83 opp-1200000000 {
84 opp-hz = /bits/ 64 <1200000000>;
85 opp-microvolt = <1150000>;
87 opp-1416000000 {
88 opp-hz = /bits/ 64 <1416000000>;
89 opp-microvolt = <1250000>;
91 opp-1608000000 {
92 opp-hz = /bits/ 64 <1608000000>;
93 opp-microvolt = <1350000>;
97 display-subsystem {
98 compatible = "rockchip,display-subsystem";
103 compatible = "mmio-sram";
105 #address-cells = <1>;
106 #size-cells = <1>;
109 smp-sram@0 {
110 compatible = "rockchip,rk3066-smp-sram";
115 vop0: vop@1010c000 {
116 compatible = "rockchip,rk3188-vop";
120 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
121 power-domains = <&power RK3188_PD_VIO>;
123 reset-names = "axi", "ahb", "dclk";
127 #address-cells = <1>;
128 #size-cells = <0>;
132 vop1: vop@1010e000 {
133 compatible = "rockchip,rk3188-vop";
137 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
138 power-domains = <&power RK3188_PD_VIO>;
140 reset-names = "axi", "ahb", "dclk";
144 #address-cells = <1>;
145 #size-cells = <0>;
150 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
154 clock-names = "timer", "pclk";
158 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
162 clock-names = "timer", "pclk";
166 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
169 pinctrl-names = "default";
170 pinctrl-0 = <&i2s0_bus>;
172 clock-names = "i2s_clk", "i2s_hclk";
174 dma-names = "tx", "rx";
175 rockchip,playback-channels = <2>;
176 rockchip,capture-channels = <2>;
177 #sound-dai-cells = <0>;
182 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
184 #sound-dai-cells = <0>;
186 clock-names = "mclk", "hclk";
188 dma-names = "tx";
190 pinctrl-names = "default";
191 pinctrl-0 = <&spdif_tx>;
195 cru: clock-controller@20000000 {
196 compatible = "rockchip,rk3188-cru";
198 rockchip,grf = <&grf>;
200 #clock-cells = <1>;
201 #reset-cells = <1>;
205 compatible = "rockchip,rk3188-efuse";
207 #address-cells = <1>;
208 #size-cells = <1>;
210 clock-names = "pclk_efuse";
218 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
219 rockchip,grf = <&grf>;
220 #address-cells = <1>;
221 #size-cells = <0>;
224 usbphy0: usb-phy@10c {
225 #phy-cells = <0>;
228 clock-names = "phyclk";
229 #clock-cells = <0>;
232 usbphy1: usb-phy@11c {
233 #phy-cells = <0>;
236 clock-names = "phyclk";
237 #clock-cells = <0>;
242 compatible = "rockchip,rk3188-pinctrl";
243 rockchip,grf = <&grf>;
244 rockchip,pmu = <&pmu>;
246 #address-cells = <1>;
247 #size-cells = <1>;
251 compatible = "rockchip,rk3188-gpio-bank0";
256 gpio-controller;
257 #gpio-cells = <2>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
264 compatible = "rockchip,gpio-bank";
269 gpio-controller;
270 #gpio-cells = <2>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
277 compatible = "rockchip,gpio-bank";
282 gpio-controller;
283 #gpio-cells = <2>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
290 compatible = "rockchip,gpio-bank";
295 gpio-controller;
296 #gpio-cells = <2>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
303 bias-pull-up;
307 bias-pull-down;
311 bias-disable;
315 emmc_clk: emmc-clk {
316 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
319 emmc_cmd: emmc-cmd {
320 rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>;
323 emmc_rst: emmc-rst {
324 rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>;
331 * flash/emmc is the boot-device.
336 emac_xfer: emac-xfer {
337 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */
347 emac_mdio: emac-mdio {
348 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
354 i2c0_xfer: i2c0-xfer {
355 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
361 i2c1_xfer: i2c1-xfer {
362 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>,
368 i2c2_xfer: i2c2-xfer {
369 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>,
375 i2c3_xfer: i2c3-xfer {
376 rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>,
382 i2c4_xfer: i2c4-xfer {
383 rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>,
389 lcdc1_dclk: lcdc1-dclk {
390 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>;
393 lcdc1_den: lcdc1-den {
394 rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>;
397 lcdc1_hsync: lcdc1-hsync {
398 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
401 lcdc1_vsync: lcdc1-vsync {
402 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
405 lcdc1_rgb24: ldcd1-rgb24 {
406 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
434 pwm0_out: pwm0-out {
435 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
440 pwm1_out: pwm1-out {
441 rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>;
446 pwm2_out: pwm2-out {
447 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>;
452 pwm3_out: pwm3-out {
453 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>;
458 spi0_clk: spi0-clk {
459 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>;
461 spi0_cs0: spi0-cs0 {
462 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>;
464 spi0_tx: spi0-tx {
465 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>;
467 spi0_rx: spi0-rx {
468 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>;
470 spi0_cs1: spi0-cs1 {
471 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>;
476 spi1_clk: spi1-clk {
477 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>;
479 spi1_cs0: spi1-cs0 {
480 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>;
482 spi1_rx: spi1-rx {
483 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>;
485 spi1_tx: spi1-tx {
486 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>;
488 spi1_cs1: spi1-cs1 {
489 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
494 uart0_xfer: uart0-xfer {
495 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
499 uart0_cts: uart0-cts {
500 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>;
503 uart0_rts: uart0-rts {
504 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>;
509 uart1_xfer: uart1-xfer {
510 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
514 uart1_cts: uart1-cts {
515 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
518 uart1_rts: uart1-rts {
519 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>;
524 uart2_xfer: uart2-xfer {
525 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
532 uart3_xfer: uart3-xfer {
533 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>,
537 uart3_cts: uart3-cts {
538 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>;
541 uart3_rts: uart3-rts {
542 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>;
547 sd0_clk: sd0-clk {
548 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>;
551 sd0_cmd: sd0-cmd {
552 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
555 sd0_cd: sd0-cd {
556 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>;
559 sd0_wp: sd0-wp {
560 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>;
563 sd0_pwr: sd0-pwr {
564 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
567 sd0_bus1: sd0-bus-width1 {
568 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
571 sd0_bus4: sd0-bus-width4 {
572 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
580 sd1_clk: sd1-clk {
581 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
584 sd1_cmd: sd1-cmd {
585 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>;
588 sd1_cd: sd1-cd {
589 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>;
592 sd1_wp: sd1-wp {
593 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>;
596 sd1_bus1: sd1-bus-width1 {
597 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>;
600 sd1_bus4: sd1-bus-width4 {
601 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>,
609 i2s0_bus: i2s0-bus {
610 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
620 spdif_tx: spdif-tx {
621 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>;
628 compatible = "rockchip,rk3188-emac";
641 compatible = "rockchip,rk3188-mali", "arm,mali-400";
652 interrupt-names = "gp",
662 power-domains = <&power RK3188_PD_GPU>;
666 compatible = "rockchip,rk3188-i2c";
667 pinctrl-names = "default";
668 pinctrl-0 = <&i2c0_xfer>;
672 compatible = "rockchip,rk3188-i2c";
673 pinctrl-names = "default";
674 pinctrl-0 = <&i2c1_xfer>;
678 compatible = "rockchip,rk3188-i2c";
679 pinctrl-names = "default";
680 pinctrl-0 = <&i2c2_xfer>;
684 compatible = "rockchip,rk3188-i2c";
685 pinctrl-names = "default";
686 pinctrl-0 = <&i2c3_xfer>;
690 compatible = "rockchip,rk3188-i2c";
691 pinctrl-names = "default";
692 pinctrl-0 = <&i2c4_xfer>;
696 power: power-controller {
697 compatible = "rockchip,rk3188-power-controller";
698 #power-domain-cells = <1>;
699 #address-cells = <1>;
700 #size-cells = <0>;
742 pinctrl-names = "default";
743 pinctrl-0 = <&pwm0_out>;
747 pinctrl-names = "default";
748 pinctrl-0 = <&pwm1_out>;
752 pinctrl-names = "default";
753 pinctrl-0 = <&pwm2_out>;
757 pinctrl-names = "default";
758 pinctrl-0 = <&pwm3_out>;
762 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
763 pinctrl-names = "default";
764 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
768 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
769 pinctrl-names = "default";
770 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
774 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
775 pinctrl-names = "default";
776 pinctrl-0 = <&uart0_xfer>;
780 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
781 pinctrl-names = "default";
782 pinctrl-0 = <&uart1_xfer>;
786 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
787 pinctrl-names = "default";
788 pinctrl-0 = <&uart2_xfer>;
792 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
793 pinctrl-names = "default";
794 pinctrl-0 = <&uart3_xfer>;
798 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";