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12

/Linux-v5.10/Documentation/devicetree/bindings/net/
Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
[all …]
Dti,k3-am654-cpts.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpts.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
17 - selection of multiple external clock sources
18 - Software control of time sync events via interrupt or polling
19 - 64-bit timestamp mode in ns with PPM and nudge adjustment.
20 - hardware timestamp push inputs (HWx_TS_PUSH)
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/Linux-v5.10/drivers/phy/ti/
Dphy-j721e-wiz.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
11 #include <linux/clk-provider.h>
16 #include <linux/mux/consumer.h>
22 #include <linux/reset-controller.h>
140 * Mux value to be configured for each of the input clocks
144 .node_name = "pll0-refclk",
148 .node_name = "pll1-refclk",
152 .node_name = "refclk-dig",
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Dphy-am654-serdes.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
11 #include <linux/clk-provider.h>
15 #include <linux/mux/consumer.h>
142 /* Mid-speed initial calibration control */
145 /* High-speed initial calibration control */
148 /* Mid-speed recalibration control */
151 /* High-speed recalibration control */
172 /* Mid-speed rate change calibration control */
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/Linux-v5.10/drivers/net/ethernet/ti/
Dcpts.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
32 #define cpts_read32(c, r) readl_relaxed(&c->reg->r)
33 #define cpts_write32(c, v, r) writel_relaxed(v, &c->reg->r)
37 return (event->high >> PORT_NUMBER_SHIFT) & PORT_NUMBER_MASK; in cpts_event_port()
42 return time_after(jiffies, event->tmo); in event_expired()
47 return (event->high >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; in event_type()
60 return -1; in cpts_fifo_pop()
69 list_for_each_safe(this, next, &cpts->events) { in cpts_purge_events()
72 list_del_init(&event->list); in cpts_purge_events()
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Dam65-cpts.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
9 #include <linux/clk-provider.h>
23 #include "am65-cpts.h"
164 struct clk *refclk; member
186 #define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r)
187 #define am65_cpts_read32(c, r) readl(&(c)->reg->r)
204 cpts->ts_add_val = (NSEC_PER_SEC / cpts->refclk_freq - 1) & 0x7; in am65_cpts_set_add_val()
206 am65_cpts_write32(cpts, cpts->ts_add_val, ts_add_val); in am65_cpts_set_add_val()
217 return (event->event1 & AM65_CPTS_EVENT_1_PORT_NUMBER_MASK) >> in am65_cpts_event_get_port()
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/Linux-v5.10/Documentation/devicetree/bindings/phy/
Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
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/Linux-v5.10/arch/arm64/boot/dts/ti/
Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/mux/ti-serdes.h>
13 compatible = "mmio-sram";
15 #address-cells = <1>;
16 #size-cells = <1>;
19 atf-sram@0 {
24 scm_conf: scm-conf@100000 {
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Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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Dk3-am65-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
9 mcu_conf: scm-conf@40f00000 {
10 compatible = "syscon", "simple-mfd";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 compatible = "ti,am654-phy-gmii-sel";
19 #phy-cells = <1>;
24 compatible = "ti,am654-uart";
26 reg-shift = <2>;
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/Linux-v5.10/sound/soc/codecs/
Dmadera.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
18 #include <linux/irqchip/irq-madera.h>
22 #include <sound/madera-pdata.h>
24 #include <dt-bindings/sound/madera.h>
143 dev_err(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
145 dev_warn(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
147 dev_dbg(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
150 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
152 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
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/Linux-v5.10/arch/arm/boot/dts/
Dkeystone-k2e-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
[all …]
Dkeystone-k2l-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
[all …]
Dkeystone-k2hk-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x4000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
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Dimx6q-h100.dts4 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
45 #include "imx6qdl-sr-som.dtsi"
46 #include "imx6qdl-sr-som-brcm.dtsi"
64 stdout-path = &uart2;
67 hdmi_osc: hdmi-osc {
68 compatible = "fixed-clock";
69 clock-output-names = "hdmi-osc";
70 clock-frequency = <27000000>;
71 #clock-cells = <0>;
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Dvexpress-v2m.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * V2M-P1
8 * HBI-0190D
14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
24 model = "V2M-P1";
27 compatible = "arm,vexpress,v2m-p1", "simple-bus";
28 #address-cells = <2>; /* SMB chipselect number and offset */
29 #size-cells = <1>;
30 #interrupt-cells = <1>;
[all …]
Dam437x-gp-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/pinctrl/am43xx.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
24 stdout-path = &uart0;
27 evm_v3_3d: fixedregulator-v3_3d {
28 compatible = "regulator-fixed";
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/Linux-v5.10/arch/mips/cavium-octeon/
Docteon-platform.c6 * Copyright (C) 2004-2017 Cavium, Inc.
16 #include <asm/octeon/cvmx-helper-board.h>
22 #include <asm/octeon/cvmx-uctlx-defs.h>
76 if (dev->of_node) { in octeon2_usb_clocks_start()
80 uctl_node = of_get_parent(dev->of_node); in octeon2_usb_clocks_start()
86 "refclk-frequency", &clock_rate); in octeon2_usb_clocks_start()
88 dev_err(dev, "No UCTL \"refclk-frequency\"\n"); in octeon2_usb_clocks_start()
92 "refclk-type", &clock_type); in octeon2_usb_clocks_start()
200 * Step 4: Program the power-on reset field in the UCTL in octeon2_usb_clocks_start()
201 * clock-reset-control register. in octeon2_usb_clocks_start()
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/Linux-v5.10/arch/arm64/boot/dts/amlogic/
Dmeson-axg.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
[all …]
/Linux-v5.10/drivers/clk/
Dclk-asm9260.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Oleksij Rempel <linux@rempel-privat.de>.
10 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/alphascale,asm9260.h>
267 clk_data->num = MAX_CLKS; in asm9260_acc_init()
268 hws = clk_data->hws; in asm9260_acc_init()
270 base = of_io_request_and_map(np, 0, np->name); in asm9260_acc_init()
284 panic("%pOFn: can't register REFCLK. Check DT!", np); in asm9260_acc_init()
289 mc->parent_names[0] = ref_clk; in asm9260_acc_init()
290 mc->parent_names[1] = pll_clk; in asm9260_acc_init()
[all …]
Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
[all …]
/Linux-v5.10/drivers/phy/marvell/
Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
19 /* Relative to priv->base */
107 /* Relative to priv->regmap */
129 * [ 1- 0]: COMPHY polarity invertion
130 * [ 2- 7]: COMPHY speed
131 * [ 5-11]: COMPHY port index
132 * [12-16]: COMPHY mode
134 * [18-20]: PCIe width (x1, x2, x4)
[all …]
/Linux-v5.10/arch/arm64/boot/dts/exynos/
Dexynos7-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include <dt-bindings/pinctrl/samsung.h>
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
33 gpio-controller;
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/Linux-v5.10/drivers/pinctrl/ti/
Dpinctrl-ti-iodelay.c5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
19 #include <linux/pinctrl/pinconf-generic.h>
27 #define DRIVER_NAME "ti-iodelay"
30 * struct ti_iodelay_reg_data - Describes the registers for the iodelay instance
38 * @reg_refclk_offset: Refclk register offset
39 * @refclk_period_mask: Refclk mask
86 * struct ti_iodelay_reg_values - Computed io_reg configuration values (see TRM)
109 * struct ti_iodelay_cfg - Description of each configuration parameters
121 * struct ti_iodelay_pingroup - Structure that describes one group
124 * @config: pinconf "Config" - currently a dummy value
[all …]
/Linux-v5.10/drivers/gpu/drm/i915/display/
Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
29 #include <linux/intel-iommu.h>
32 #include <linux/dma-resv.h>
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
222 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
241 dev_priv->czclk_freq); in intel_update_czclk()
[all …]

12