Lines Matching +full:refclk +full:- +full:mux

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (c) 2014 Oleksij Rempel <linux@rempel-privat.de>.
10 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/alphascale,asm9260.h>
267 	clk_data->num = MAX_CLKS;  in asm9260_acc_init()
268 	hws = clk_data->hws;  in asm9260_acc_init()
270 	base = of_io_request_and_map(np, 0, np->name);  in asm9260_acc_init()
284 		panic("%pOFn: can't register REFCLK. Check DT!", np);  in asm9260_acc_init()
289 		mc->parent_names[0] = ref_clk;  in asm9260_acc_init()
290 		mc->parent_names[1] = pll_clk;  in asm9260_acc_init()
291 		hw = clk_hw_register_mux_table(NULL, mc->name, mc->parent_names,  in asm9260_acc_init()
292 				mc->num_parents, mc->flags, base + mc->offset,  in asm9260_acc_init()
293 				0, mc->mask, 0, mc->table, &asm9260_clk_lock);  in asm9260_acc_init()
296 	/* clock mux gate cells */  in asm9260_acc_init()
300 		hw = clk_hw_register_gate(NULL, gd->name,  in asm9260_acc_init()
301 			gd->parent_name, gd->flags | CLK_SET_RATE_PARENT,  in asm9260_acc_init()
302 			base + gd->reg, gd->bit_idx, 0, &asm9260_clk_lock);  in asm9260_acc_init()
309 		hws[dc->idx] = clk_hw_register_divider(NULL, dc->name,  in asm9260_acc_init()
310 				dc->parent_name, CLK_SET_RATE_PARENT,  in asm9260_acc_init()
311 				base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED,  in asm9260_acc_init()
319 		hws[gd->idx] = clk_hw_register_gate(NULL, gd->name,  in asm9260_acc_init()
320 				gd->parent_name, gd->flags, base + gd->reg,  in asm9260_acc_init()
321 				gd->bit_idx, 0, &asm9260_clk_lock);  in asm9260_acc_init()
334 	/* register clk-provider */  in asm9260_acc_init()
340 CLK_OF_DECLARE(asm9260_acc, "alphascale,asm9260-clock-controller",