5  * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
19 #include <linux/pinctrl/pinconf-generic.h>
27 #define DRIVER_NAME	"ti-iodelay"
30  * struct ti_iodelay_reg_data - Describes the registers for the iodelay instance
38  * @reg_refclk_offset: Refclk register offset
39  * @refclk_period_mask: Refclk mask
86  * struct ti_iodelay_reg_values - Computed io_reg configuration values (see TRM)
109  * struct ti_iodelay_cfg - Description of each configuration parameters
121  * struct ti_iodelay_pingroup - Structure that describes one group
124  * @config: pinconf "Config" - currently a dummy value
133  * struct ti_iodelay_device - Represents information for a iodelay instance
159  * ti_iodelay_extract() - extract bits for a field
171  * ti_iodelay_compute_dpe() - Compute equation for delay parameter
193  * ti_iodelay_pinconf_set() - Configure the pin configuration
209 	const struct ti_iodelay_reg_data *reg = iod->reg_data;  in ti_iodelay_pinconf_set()
210 	struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values;  in ti_iodelay_pinconf_set()
211 	struct device *dev = iod->dev;  in ti_iodelay_pinconf_set()
220 	g_delay_coarse = cfg->g_delay / 920;  in ti_iodelay_pinconf_set()
221 	g_delay_fine = ((cfg->g_delay % 920) * 10) / 60;  in ti_iodelay_pinconf_set()
223 	a_delay_coarse = cfg->a_delay / ival->cdpe;  in ti_iodelay_pinconf_set()
224 	a_delay_fine = ((cfg->a_delay % ival->cdpe) * 10) / ival->fdpe;  in ti_iodelay_pinconf_set()
230 		total_delay = c_elements * ival->cdpe + f_elements * ival->fdpe;  in ti_iodelay_pinconf_set()
231 		c_elements = total_delay / ival->cdpe;  in ti_iodelay_pinconf_set()
232 		f_elements = (total_delay % ival->cdpe) / ival->fdpe;  in ti_iodelay_pinconf_set()
235 	reg_mask = reg->signature_mask;  in ti_iodelay_pinconf_set()
236 	reg_val = reg->signature_value << __ffs(reg->signature_mask);  in ti_iodelay_pinconf_set()
238 	reg_mask |= reg->binary_data_coarse_mask;  in ti_iodelay_pinconf_set()
239 	tmp_val = c_elements << __ffs(reg->binary_data_coarse_mask);  in ti_iodelay_pinconf_set()
240 	if (tmp_val & ~reg->binary_data_coarse_mask) {  in ti_iodelay_pinconf_set()
243 		tmp_val &= reg->binary_data_coarse_mask;  in ti_iodelay_pinconf_set()
247 	reg_mask |= reg->binary_data_fine_mask;  in ti_iodelay_pinconf_set()
248 	tmp_val = f_elements << __ffs(reg->binary_data_fine_mask);  in ti_iodelay_pinconf_set()
249 	if (tmp_val & ~reg->binary_data_fine_mask) {  in ti_iodelay_pinconf_set()
252 		tmp_val &= reg->binary_data_fine_mask;  in ti_iodelay_pinconf_set()
257 	 * NOTE: we leave the iodelay values unlocked - this is to work around  in ti_iodelay_pinconf_set()
262 	reg_mask |= reg->lock_mask;  in ti_iodelay_pinconf_set()
263 	reg_val |= reg->unlock_val << __ffs(reg->lock_mask);  in ti_iodelay_pinconf_set()
264 	r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val);  in ti_iodelay_pinconf_set()
267 		cfg->offset, cfg->a_delay, cfg->g_delay, c_elements,  in ti_iodelay_pinconf_set()
274  * ti_iodelay_pinconf_init_dev() - Initialize IODelay device
283 	const struct ti_iodelay_reg_data *reg = iod->reg_data;  in ti_iodelay_pinconf_init_dev()
284 	struct device *dev = iod->dev;  in ti_iodelay_pinconf_init_dev()
285 	struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values;  in ti_iodelay_pinconf_init_dev()
290 	r = regmap_update_bits(iod->regmap, reg->reg_global_lock_offset,  in ti_iodelay_pinconf_init_dev()
291 			       reg->global_lock_mask, reg->global_unlock_val);  in ti_iodelay_pinconf_init_dev()
296 	r = regmap_read(iod->regmap, reg->reg_refclk_offset, &val);  in ti_iodelay_pinconf_init_dev()
299 	ival->ref_clk_period = ti_iodelay_extract(val, reg->refclk_period_mask);  in ti_iodelay_pinconf_init_dev()
300 	dev_dbg(dev, "refclk_period=0x%04x\n", ival->ref_clk_period);  in ti_iodelay_pinconf_init_dev()
302 	r = regmap_read(iod->regmap, reg->reg_coarse_offset, &val);  in ti_iodelay_pinconf_init_dev()
305 	ival->coarse_ref_count =  in ti_iodelay_pinconf_init_dev()
306 	    ti_iodelay_extract(val, reg->coarse_ref_count_mask);  in ti_iodelay_pinconf_init_dev()
307 	ival->coarse_delay_count =  in ti_iodelay_pinconf_init_dev()
308 	    ti_iodelay_extract(val, reg->coarse_delay_count_mask);  in ti_iodelay_pinconf_init_dev()
309 	if (!ival->coarse_delay_count) {  in ti_iodelay_pinconf_init_dev()
312 		return -EINVAL;  in ti_iodelay_pinconf_init_dev()
314 	ival->cdpe = ti_iodelay_compute_dpe(ival->ref_clk_period,  in ti_iodelay_pinconf_init_dev()
315 					    ival->coarse_ref_count,  in ti_iodelay_pinconf_init_dev()
316 					    ival->coarse_delay_count, 88);  in ti_iodelay_pinconf_init_dev()
317 	if (!ival->cdpe) {  in ti_iodelay_pinconf_init_dev()
319 			ival->ref_clk_period, ival->coarse_ref_count,  in ti_iodelay_pinconf_init_dev()
320 			ival->coarse_delay_count);  in ti_iodelay_pinconf_init_dev()
321 		return -EINVAL;  in ti_iodelay_pinconf_init_dev()
323 	dev_dbg(iod->dev, "coarse: ref=0x%04x delay=0x%04x cdpe=0x%08x\n",  in ti_iodelay_pinconf_init_dev()
324 		ival->coarse_ref_count, ival->coarse_delay_count, ival->cdpe);  in ti_iodelay_pinconf_init_dev()
326 	r = regmap_read(iod->regmap, reg->reg_fine_offset, &val);  in ti_iodelay_pinconf_init_dev()
329 	ival->fine_ref_count =  in ti_iodelay_pinconf_init_dev()
330 	    ti_iodelay_extract(val, reg->fine_ref_count_mask);  in ti_iodelay_pinconf_init_dev()
331 	ival->fine_delay_count =  in ti_iodelay_pinconf_init_dev()
332 	    ti_iodelay_extract(val, reg->fine_delay_count_mask);  in ti_iodelay_pinconf_init_dev()
333 	if (!ival->fine_delay_count) {  in ti_iodelay_pinconf_init_dev()
336 		return -EINVAL;  in ti_iodelay_pinconf_init_dev()
338 	ival->fdpe = ti_iodelay_compute_dpe(ival->ref_clk_period,  in ti_iodelay_pinconf_init_dev()
339 					    ival->fine_ref_count,  in ti_iodelay_pinconf_init_dev()
340 					    ival->fine_delay_count, 264);  in ti_iodelay_pinconf_init_dev()
341 	if (!ival->fdpe) {  in ti_iodelay_pinconf_init_dev()
343 			ival->ref_clk_period, ival->fine_ref_count,  in ti_iodelay_pinconf_init_dev()
344 			ival->fine_delay_count);  in ti_iodelay_pinconf_init_dev()
345 		return -EINVAL;  in ti_iodelay_pinconf_init_dev()
347 	dev_dbg(iod->dev, "fine: ref=0x%04x delay=0x%04x fdpe=0x%08x\n",  in ti_iodelay_pinconf_init_dev()
348 		ival->fine_ref_count, ival->fine_delay_count, ival->fdpe);  in ti_iodelay_pinconf_init_dev()
354  * ti_iodelay_pinconf_deinit_dev() - deinit the iodelay device
361 	const struct ti_iodelay_reg_data *reg = iod->reg_data;  in ti_iodelay_pinconf_deinit_dev()
364 	regmap_update_bits(iod->regmap, reg->reg_global_lock_offset,  in ti_iodelay_pinconf_deinit_dev()
365 			   reg->global_lock_mask, reg->global_lock_val);  in ti_iodelay_pinconf_deinit_dev()
369  * ti_iodelay_get_pingroup() - Find the group mapped by a group selector
380 	g = pinctrl_generic_get_group(iod->pctl, selector);  in ti_iodelay_get_pingroup()
382 		dev_err(iod->dev, "%s could not find pingroup %i\n", __func__,  in ti_iodelay_get_pingroup()
388 	return g->data;  in ti_iodelay_get_pingroup()
392  * ti_iodelay_offset_to_pin() - get a pin index based on the register offset
399 	const struct ti_iodelay_reg_data *r = iod->reg_data;  in ti_iodelay_offset_to_pin()
402 	if (offset > r->regmap_config->max_register) {  in ti_iodelay_offset_to_pin()
403 		dev_err(iod->dev, "mux offset out of range: 0x%x (0x%x)\n",  in ti_iodelay_offset_to_pin()
404 			offset, r->regmap_config->max_register);  in ti_iodelay_offset_to_pin()
405 		return -EINVAL;  in ti_iodelay_offset_to_pin()
408 	index = (offset - r->reg_start_offset) / r->regmap_config->reg_stride;  in ti_iodelay_offset_to_pin()
409 	index /= r->reg_nr_per_pin;  in ti_iodelay_offset_to_pin()
415  * ti_iodelay_node_iterator() - Iterate iodelay node
437 		return -EINVAL;  in ti_iodelay_node_iterator()
439 	r = iod->reg_data;  in ti_iodelay_node_iterator()
441 	if (pinctrl_spec->args_count < r->reg_nr_per_pin) {  in ti_iodelay_node_iterator()
442 		dev_err(iod->dev, "invalid args_count for spec: %i\n",  in ti_iodelay_node_iterator()
443 			pinctrl_spec->args_count);  in ti_iodelay_node_iterator()
445 		return -EINVAL;  in ti_iodelay_node_iterator()
449 	cfg[pin_index].offset = pinctrl_spec->args[0];  in ti_iodelay_node_iterator()
450 	cfg[pin_index].a_delay = pinctrl_spec->args[1] & 0xffff;  in ti_iodelay_node_iterator()
451 	cfg[pin_index].g_delay = pinctrl_spec->args[2] & 0xffff;  in ti_iodelay_node_iterator()
455 		dev_err(iod->dev, "could not add functions for %pOFn %ux\n",  in ti_iodelay_node_iterator()
457 		return -ENODEV;  in ti_iodelay_node_iterator()
461 	pd = &iod->pa[pin];  in ti_iodelay_node_iterator()
462 	pd->drv_data = &cfg[pin_index];  in ti_iodelay_node_iterator()
464 	dev_dbg(iod->dev, "%pOFn offset=%x a_delay = %d g_delay = %d\n",  in ti_iodelay_node_iterator()
472  * ti_iodelay_dt_node_to_map() - Map a device tree node to appropriate group
491 	const char *name = "pinctrl-pin-array";  in ti_iodelay_dt_node_to_map()
492 	int rows, *pins, error = -EINVAL, i;  in ti_iodelay_dt_node_to_map()
496 		return -EINVAL;  in ti_iodelay_dt_node_to_map()
502 	*map = devm_kzalloc(iod->dev, sizeof(**map), GFP_KERNEL);  in ti_iodelay_dt_node_to_map()
504 		return -ENOMEM;  in ti_iodelay_dt_node_to_map()
507 	g = devm_kzalloc(iod->dev, sizeof(*g), GFP_KERNEL);  in ti_iodelay_dt_node_to_map()
509 		error = -ENOMEM;  in ti_iodelay_dt_node_to_map()
513 	pins = devm_kcalloc(iod->dev, rows, sizeof(*pins), GFP_KERNEL);  in ti_iodelay_dt_node_to_map()
517 	cfg = devm_kcalloc(iod->dev, rows, sizeof(*cfg), GFP_KERNEL);  in ti_iodelay_dt_node_to_map()
519 		error = -ENOMEM;  in ti_iodelay_dt_node_to_map()
537 	g->cfg = cfg;  in ti_iodelay_dt_node_to_map()
538 	g->ncfg = i;  in ti_iodelay_dt_node_to_map()
539 	g->config = PIN_CONFIG_END;  in ti_iodelay_dt_node_to_map()
541 	error = pinctrl_generic_add_group(iod->pctl, np->name, pins, i, g);  in ti_iodelay_dt_node_to_map()
545 	(*map)->type = PIN_MAP_TYPE_CONFIGS_GROUP;  in ti_iodelay_dt_node_to_map()
546 	(*map)->data.configs.group_or_pin = np->name;  in ti_iodelay_dt_node_to_map()
547 	(*map)->data.configs.configs = &g->config;  in ti_iodelay_dt_node_to_map()
548 	(*map)->data.configs.num_configs = 1;  in ti_iodelay_dt_node_to_map()
554 	devm_kfree(iod->dev, cfg);  in ti_iodelay_dt_node_to_map()
556 	devm_kfree(iod->dev, pins);  in ti_iodelay_dt_node_to_map()
558 	devm_kfree(iod->dev, g);  in ti_iodelay_dt_node_to_map()
560 	devm_kfree(iod->dev, *map);  in ti_iodelay_dt_node_to_map()
566  * ti_iodelay_pinconf_group_get() - Get the group configuration
571  * Return: The configuration if the group is valid, else returns -EINVAL
584 		return -EINVAL;  in ti_iodelay_pinconf_group_get()
586 	*config = group->config;  in ti_iodelay_pinconf_group_get()
591  * ti_iodelay_pinconf_group_set() - Configure the groups of pins
610 	dev = iod->dev;  in ti_iodelay_pinconf_group_set()
616 		return -EINVAL;  in ti_iodelay_pinconf_group_set()
621 		return -EINVAL;  in ti_iodelay_pinconf_group_set()
624 	for (i = 0; i < group->ncfg; i++) {  in ti_iodelay_pinconf_group_set()
625 		if (ti_iodelay_pinconf_set(iod, &group->cfg[i]))  in ti_iodelay_pinconf_group_set()
626 			return -ENOTSUPP;  in ti_iodelay_pinconf_group_set()
634  * ti_iodelay_pin_to_offset() - get pin register offset based on the pin index
641 	const struct ti_iodelay_reg_data *r = iod->reg_data;  in ti_iodelay_pin_to_offset()
644 	offset = selector * r->regmap_config->reg_stride;  in ti_iodelay_pin_to_offset()
645 	offset *= r->reg_nr_per_pin;  in ti_iodelay_pin_to_offset()
646 	offset += r->reg_start_offset;  in ti_iodelay_pin_to_offset()
663 	r = iod->reg_data;  in ti_iodelay_pin_dbg_show()
666 	pd = &iod->pa[pin];  in ti_iodelay_pin_dbg_show()
667 	cfg = pd->drv_data;  in ti_iodelay_pin_dbg_show()
669 	regmap_read(iod->regmap, offset, &in);  in ti_iodelay_pin_dbg_show()
670 	regmap_read(iod->regmap, offset + r->regmap_config->reg_stride, &oen);  in ti_iodelay_pin_dbg_show()
671 	regmap_read(iod->regmap, offset + r->regmap_config->reg_stride * 2,  in ti_iodelay_pin_dbg_show()
675 		   iod->phys_base + offset,  in ti_iodelay_pin_dbg_show()
676 		   cfg ? cfg->a_delay : -1,  in ti_iodelay_pin_dbg_show()
677 		   cfg ? cfg->g_delay : -1,  in ti_iodelay_pin_dbg_show()
682  * ti_iodelay_pinconf_group_dbg_show() - show the group information
702 	for (i = 0; i < group->ncfg; i++) {  in ti_iodelay_pinconf_group_dbg_show()
706 		cfg = &group->cfg[i];  in ti_iodelay_pinconf_group_dbg_show()
707 		regmap_read(iod->regmap, cfg->offset, &reg),  in ti_iodelay_pinconf_group_dbg_show()
709 				   cfg->offset, reg, cfg->a_delay,  in ti_iodelay_pinconf_group_dbg_show()
710 				   cfg->g_delay);  in ti_iodelay_pinconf_group_dbg_show()
734  * ti_iodelay_alloc_pins() - Allocate structures needed for pins for iodelay
744 	const struct ti_iodelay_reg_data *r = iod->reg_data;  in ti_iodelay_alloc_pins()
749 	nr_pins = ti_iodelay_offset_to_pin(iod, r->regmap_config->max_register);  in ti_iodelay_alloc_pins()
752 	iod->pa = devm_kcalloc(dev, nr_pins, sizeof(*iod->pa), GFP_KERNEL);  in ti_iodelay_alloc_pins()
753 	if (!iod->pa)  in ti_iodelay_alloc_pins()
754 		return -ENOMEM;  in ti_iodelay_alloc_pins()
756 	iod->desc.pins = iod->pa;  in ti_iodelay_alloc_pins()
757 	iod->desc.npins = nr_pins;  in ti_iodelay_alloc_pins()
759 	phy_reg = r->reg_start_offset + base_phy;  in ti_iodelay_alloc_pins()
762 		pin = &iod->pa[i];  in ti_iodelay_alloc_pins()
763 		pin->number = i;  in ti_iodelay_alloc_pins()
807 	{.compatible = "ti,dra7-iodelay", .data = &dra7_iodelay_data},
813  * ti_iodelay_probe() - Standard probe
820 	struct device *dev = &pdev->dev;  in ti_iodelay_probe()
821 	struct device_node *np = of_node_get(dev->of_node);  in ti_iodelay_probe()
828 		ret = -EINVAL;  in ti_iodelay_probe()
835 		ret = -EINVAL;  in ti_iodelay_probe()
842 		ret = -ENOMEM;  in ti_iodelay_probe()
845 	iod->dev = dev;  in ti_iodelay_probe()
846 	iod->reg_data = match->data;  in ti_iodelay_probe()
852 		ret = -ENODEV;  in ti_iodelay_probe()
856 	iod->phys_base = res->start;  in ti_iodelay_probe()
857 	iod->reg_base = devm_ioremap_resource(dev, res);  in ti_iodelay_probe()
858 	if (IS_ERR(iod->reg_base)) {  in ti_iodelay_probe()
859 		ret = PTR_ERR(iod->reg_base);  in ti_iodelay_probe()
863 	iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base,  in ti_iodelay_probe()
864 					    iod->reg_data->regmap_config);  in ti_iodelay_probe()
865 	if (IS_ERR(iod->regmap)) {  in ti_iodelay_probe()
867 		ret = PTR_ERR(iod->regmap);  in ti_iodelay_probe()
874 	ret = ti_iodelay_alloc_pins(dev, iod, res->start);  in ti_iodelay_probe()
878 	iod->desc.pctlops = &ti_iodelay_pinctrl_ops;  in ti_iodelay_probe()
879 	/* no pinmux ops - we are pinconf */  in ti_iodelay_probe()
880 	iod->desc.confops = &ti_iodelay_pinctrl_pinconf_ops;  in ti_iodelay_probe()
881 	iod->desc.name = dev_name(dev);  in ti_iodelay_probe()
882 	iod->desc.owner = THIS_MODULE;  in ti_iodelay_probe()
884 	ret = pinctrl_register_and_init(&iod->desc, dev, iod, &iod->pctl);  in ti_iodelay_probe()
892 	return pinctrl_enable(iod->pctl);  in ti_iodelay_probe()
900  * ti_iodelay_remove() - standard remove
912 	if (iod->pctl)  in ti_iodelay_remove()
913 		pinctrl_unregister(iod->pctl);  in ti_iodelay_remove()