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/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dallwinner,sun4i-a10-pll1-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
21 - allwinner,sun4i-a10-pll1-clk
22 - allwinner,sun6i-a31-pll1-clk
23 - allwinner,sun8i-a23-pll1-clk
47 compatible = "allwinner,sun4i-a10-pll1";
56 compatible = "allwinner,sun6i-a31-pll1-clk";
59 clock-output-names = "pll1";
65 compatible = "allwinner,sun8i-a23-pll1-clk";
68 clock-output-names = "pll1";
Dqoriq-clock.txt167 pll1: pll1@820 {
172 clock-output-names = "pll1", "pll1-div2";
179 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
180 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
188 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
189 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dsilabs,si5351.txt82 /* connect xtal input as source of pll0 and pll1 */
105 * - pll1 as clock source of multisynth1
107 * - multisynth1 can change pll1
/Linux-v5.10/include/linux/iio/frequency/
Dad9523.h117 * @refa_r_div: PLL1 10-bit REFA R divider.
118 * @refb_r_div: PLL1 10-bit REFB R divider.
119 * @pll1_feedback_div: PLL1 10-bit Feedback N divider.
120 * @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA).
122 * @osc_in_feedback_en: PLL1 feedback path, local feedback from
124 * @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection.
160 /* PLL1 Setting */
/Linux-v5.10/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
15 - for "ti,da850-pll1", shall be "clksrc"
80 pll1: clock-controller@21a000 {
81 compatible = "ti,da850-pll1";
/Linux-v5.10/drivers/clk/renesas/
Dclk-sh73a0.c49 { "m3", "pll1", CPG_FRQCRA, 12 },
50 { "b", "pll1", CPG_FRQCRA, 8 },
51 { "m1", "pll1", CPG_FRQCRA, 4 },
52 { "m2", "pll1", CPG_FRQCRA, 0 },
53 { "zx", "pll1", CPG_FRQCRB, 12 },
54 { "hp", "pll1", CPG_FRQCRB, 4 },
113 /* handle CFG bit for PLL1 and PLL2 */ in sh73a0_cpg_register_clock()
Dr8a77470-cpg-mssr.c45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
173 * MD EXTAL PLL0 PLL1 PLL3
182 * *2 : Table 7.4 indicates VCO output (PLL1 = VCO)
188 /* EXTAL div PLL1 mult x2 PLL3 mult */
Dr8a7745-cpg-mssr.c45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
190 * MD EXTAL PLL0 PLL1 PLL3
199 * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
205 /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
/Linux-v5.10/drivers/clk/mmp/
Dclk-pxa910.c107 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa910_clk_init()
108 clk_register_clkdev(clk, "pll1", NULL); in pxa910_clk_init()
110 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa910_clk_init()
146 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", in pxa910_clk_init()
150 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", in pxa910_clk_init()
154 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", in pxa910_clk_init()
158 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", in pxa910_clk_init()
Dclk-pxa168.c102 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa168_clk_init()
103 clk_register_clkdev(clk, "pll1", NULL); in pxa168_clk_init()
105 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa168_clk_init()
141 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", in pxa168_clk_init()
145 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", in pxa168_clk_init()
149 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", in pxa168_clk_init()
153 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", in pxa168_clk_init()
Dclk-mmp2.c72 static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
73 static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
109 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000); in mmp2_clk_init()
110 clk_register_clkdev(clk, "pll1", NULL); in mmp2_clk_init()
118 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in mmp2_clk_init()
138 clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1", in mmp2_clk_init()
Dclk-of-mmp2.c107 {MMP2_CLK_PLL1, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0},
112 …{MMP2_CLK_PLL2, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0, 26000000…
120 {MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
125 {MMP2_CLK_PLL1_3, "pll1_3", "pll1", 1, 3, 0},
301 static const char * const sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
312 static const char * const disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
324 static const char * const mmp3_gpu_gc_parent_names[] = {"pll1", "pll2", "pll1_p", "pll2_p"};
Dclk-of-pxa168.c61 {PXA168_CLK_PLL1, "pll1", NULL, 0, 624000000},
66 {PXA168_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
76 {PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
79 {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
/Linux-v5.10/arch/c6x/platforms/
Dplldata.c26 /* Default input for PLL1 */
38 .name = "pll1",
155 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
193 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
233 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
289 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
338 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
/Linux-v5.10/Documentation/arm/sunxi/
Dclocks.rst20 PLL1
31 PLL1 |
/Linux-v5.10/drivers/gpu/drm/nouveau/dispnv04/
Dhw.c132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
[all …]
/Linux-v5.10/drivers/gpu/drm/hisilicon/hibmc/
Dhibmc_drm_de.c285 u32 *pll1, u32 *pll2) in get_pll_config() argument
293 *pll1 = hibmc_pll_table[i].pll1_config_value; in get_pll_config()
300 *pll1 = CRT_PLL1_HS_25MHZ; in get_pll_config()
316 u32 pll1; /* bit[31:0] of PLL */ in display_ctrl_adjust() local
323 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
325 set_vclock_hisilicon(dev, pll1); in display_ctrl_adjust()
/Linux-v5.10/drivers/media/i2c/
Dov7251.c125 { 0x30b0, 0x0a }, /* pll1 pix divider */
126 { 0x30b1, 0x01 }, /* pll1 divider */
127 { 0x30b3, 0x64 }, /* pll1 multiplier */
128 { 0x30b4, 0x03 }, /* pll1 pre divider */
129 { 0x30b5, 0x05 }, /* pll1 mipi divider */
263 { 0x30b0, 0x0a }, /* pll1 pix divider */
264 { 0x30b1, 0x01 }, /* pll1 divider */
265 { 0x30b3, 0x64 }, /* pll1 multiplier */
266 { 0x30b4, 0x03 }, /* pll1 pre divider */
267 { 0x30b5, 0x05 }, /* pll1 mipi divider */
[all …]
/Linux-v5.10/drivers/gpu/drm/tegra/
Dhdmi.c37 u32 pll1; member
132 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
147 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
165 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
179 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
193 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
210 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
228 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
247 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
266 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
[all …]
/Linux-v5.10/drivers/clk/sunxi/
Dclk-sunxi.c27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
28 * PLL1 rate is calculated as follows
41 /* m is always zero for pll1 */ in sun4i_get_pll1_factors()
75 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
76 * PLL1 rate is calculated as follows
151 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
152 * PLL1 rate is calculated as follows
165 /* m is always zero for pll1 */ in sun8i_a23_get_pll1_factors()
575 CLK_OF_DECLARE(sun4i_pll1, "allwinner,sun4i-a10-pll1-clk",
582 CLK_OF_DECLARE(sun6i_pll1, "allwinner,sun6i-a31-pll1-clk",
[all …]
/Linux-v5.10/sound/soc/codecs/
Dadav80x.c206 SND_SOC_DAPM_SUPPLY("PLL1", ADAV80X_PLL_CTRL1, 2, 1, NULL, 0),
220 clk = "PLL1"; in adav80x_dapm_sysclk_check()
269 { "SYSCLK", NULL, "PLL1", adav80x_dapm_sysclk_check },
272 { "PLL1", NULL, "OSC", adav80x_dapm_pll_check },
604 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL1"); in adav80x_set_sysclk()
606 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL1"); in adav80x_set_sysclk()
808 snd_soc_dapm_force_enable_pin(dapm, "PLL1"); in adav80x_probe()
Dak4642.c115 #define PLL1 (1 << 5) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
/Linux-v5.10/drivers/clk/mxs/
Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
230 clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock); in mx28_clocks_init()
/Linux-v5.10/arch/sh/boards/mach-hp6xx/
Dpm.c54 /* disable PLL1 */ in pm_enter()
84 /* enable PLL1 */ in pm_enter()

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