1 /*
2 * pxa910 clock framework source file
3 *
4 * Copyright (C) 2012 Marvell
5 * Chao Xie <xiechao.mail@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/clk/mmp.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/spinlock.h>
17 #include <linux/io.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20
21 #include "clk.h"
22
23 #define APBC_RTC 0x28
24 #define APBC_TWSI0 0x2c
25 #define APBC_KPC 0x18
26 #define APBC_UART0 0x0
27 #define APBC_UART1 0x4
28 #define APBC_GPIO 0x8
29 #define APBC_PWM0 0xc
30 #define APBC_PWM1 0x10
31 #define APBC_PWM2 0x14
32 #define APBC_PWM3 0x18
33 #define APBC_SSP0 0x1c
34 #define APBC_SSP1 0x20
35 #define APBC_SSP2 0x4c
36 #define APBCP_TWSI1 0x28
37 #define APBCP_UART2 0x1c
38 #define APMU_SDH0 0x54
39 #define APMU_SDH1 0x58
40 #define APMU_USB 0x5c
41 #define APMU_DISP0 0x4c
42 #define APMU_CCIC0 0x50
43 #define APMU_DFC 0x60
44 #define MPMU_UART_PLL 0x14
45
46 static DEFINE_SPINLOCK(clk_lock);
47
48 static struct mmp_clk_factor_masks uart_factor_masks = {
49 .factor = 2,
50 .num_mask = 0x1fff,
51 .den_mask = 0x1fff,
52 .num_shift = 16,
53 .den_shift = 0,
54 };
55
56 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
57 {.num = 8125, .den = 1536}, /*14.745MHZ */
58 };
59
60 static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
61 static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
62 static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
63 static const char *disp_parent[] = {"pll1_2", "pll1_12"};
64 static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
65 static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
66
pxa910_clk_init(phys_addr_t mpmu_phys,phys_addr_t apmu_phys,phys_addr_t apbc_phys,phys_addr_t apbcp_phys)67 void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
68 phys_addr_t apbc_phys, phys_addr_t apbcp_phys)
69 {
70 struct clk *clk;
71 struct clk *uart_pll;
72 void __iomem *mpmu_base;
73 void __iomem *apmu_base;
74 void __iomem *apbcp_base;
75 void __iomem *apbc_base;
76
77 mpmu_base = ioremap(mpmu_phys, SZ_4K);
78 if (!mpmu_base) {
79 pr_err("error to ioremap MPMU base\n");
80 return;
81 }
82
83 apmu_base = ioremap(apmu_phys, SZ_4K);
84 if (!apmu_base) {
85 pr_err("error to ioremap APMU base\n");
86 return;
87 }
88
89 apbcp_base = ioremap(apbcp_phys, SZ_4K);
90 if (!apbcp_base) {
91 pr_err("error to ioremap APBC extension base\n");
92 return;
93 }
94
95 apbc_base = ioremap(apbc_phys, SZ_4K);
96 if (!apbc_base) {
97 pr_err("error to ioremap APBC base\n");
98 return;
99 }
100
101 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
102 clk_register_clkdev(clk, "clk32", NULL);
103
104 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
105 clk_register_clkdev(clk, "vctcxo", NULL);
106
107 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
108 clk_register_clkdev(clk, "pll1", NULL);
109
110 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
111 CLK_SET_RATE_PARENT, 1, 2);
112 clk_register_clkdev(clk, "pll1_2", NULL);
113
114 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
115 CLK_SET_RATE_PARENT, 1, 2);
116 clk_register_clkdev(clk, "pll1_4", NULL);
117
118 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
119 CLK_SET_RATE_PARENT, 1, 2);
120 clk_register_clkdev(clk, "pll1_8", NULL);
121
122 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
123 CLK_SET_RATE_PARENT, 1, 2);
124 clk_register_clkdev(clk, "pll1_16", NULL);
125
126 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
127 CLK_SET_RATE_PARENT, 1, 3);
128 clk_register_clkdev(clk, "pll1_6", NULL);
129
130 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
131 CLK_SET_RATE_PARENT, 1, 2);
132 clk_register_clkdev(clk, "pll1_12", NULL);
133
134 clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
135 CLK_SET_RATE_PARENT, 1, 2);
136 clk_register_clkdev(clk, "pll1_24", NULL);
137
138 clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
139 CLK_SET_RATE_PARENT, 1, 2);
140 clk_register_clkdev(clk, "pll1_48", NULL);
141
142 clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
143 CLK_SET_RATE_PARENT, 1, 2);
144 clk_register_clkdev(clk, "pll1_96", NULL);
145
146 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
147 CLK_SET_RATE_PARENT, 1, 13);
148 clk_register_clkdev(clk, "pll1_13", NULL);
149
150 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
151 CLK_SET_RATE_PARENT, 2, 3);
152 clk_register_clkdev(clk, "pll1_13_1_5", NULL);
153
154 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
155 CLK_SET_RATE_PARENT, 2, 3);
156 clk_register_clkdev(clk, "pll1_2_1_5", NULL);
157
158 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
159 CLK_SET_RATE_PARENT, 3, 16);
160 clk_register_clkdev(clk, "pll1_3_16", NULL);
161
162 uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
163 mpmu_base + MPMU_UART_PLL,
164 &uart_factor_masks, uart_factor_tbl,
165 ARRAY_SIZE(uart_factor_tbl), &clk_lock);
166 clk_set_rate(uart_pll, 14745600);
167 clk_register_clkdev(uart_pll, "uart_pll", NULL);
168
169 clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
170 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
171 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
172
173 clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
174 apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
175 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
176
177 clk = mmp_clk_register_apbc("gpio", "vctcxo",
178 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
179 clk_register_clkdev(clk, NULL, "mmp-gpio");
180
181 clk = mmp_clk_register_apbc("kpc", "clk32",
182 apbc_base + APBC_KPC, 10, 0, &clk_lock);
183 clk_register_clkdev(clk, NULL, "pxa27x-keypad");
184
185 clk = mmp_clk_register_apbc("rtc", "clk32",
186 apbc_base + APBC_RTC, 10, 0, &clk_lock);
187 clk_register_clkdev(clk, NULL, "sa1100-rtc");
188
189 clk = mmp_clk_register_apbc("pwm0", "pll1_48",
190 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
191 clk_register_clkdev(clk, NULL, "pxa910-pwm.0");
192
193 clk = mmp_clk_register_apbc("pwm1", "pll1_48",
194 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
195 clk_register_clkdev(clk, NULL, "pxa910-pwm.1");
196
197 clk = mmp_clk_register_apbc("pwm2", "pll1_48",
198 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
199 clk_register_clkdev(clk, NULL, "pxa910-pwm.2");
200
201 clk = mmp_clk_register_apbc("pwm3", "pll1_48",
202 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
203 clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
204
205 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
206 ARRAY_SIZE(uart_parent),
207 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
208 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
209 clk_set_parent(clk, uart_pll);
210 clk_register_clkdev(clk, "uart_mux.0", NULL);
211
212 clk = mmp_clk_register_apbc("uart0", "uart0_mux",
213 apbc_base + APBC_UART0, 10, 0, &clk_lock);
214 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
215
216 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
217 ARRAY_SIZE(uart_parent),
218 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
219 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
220 clk_set_parent(clk, uart_pll);
221 clk_register_clkdev(clk, "uart_mux.1", NULL);
222
223 clk = mmp_clk_register_apbc("uart1", "uart1_mux",
224 apbc_base + APBC_UART1, 10, 0, &clk_lock);
225 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
226
227 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
228 ARRAY_SIZE(uart_parent),
229 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
230 apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
231 clk_set_parent(clk, uart_pll);
232 clk_register_clkdev(clk, "uart_mux.2", NULL);
233
234 clk = mmp_clk_register_apbc("uart2", "uart2_mux",
235 apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
236 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
237
238 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
239 ARRAY_SIZE(ssp_parent),
240 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
241 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
242 clk_register_clkdev(clk, "uart_mux.0", NULL);
243
244 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
245 apbc_base + APBC_SSP0, 10, 0, &clk_lock);
246 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
247
248 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
249 ARRAY_SIZE(ssp_parent),
250 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
251 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
252 clk_register_clkdev(clk, "ssp_mux.1", NULL);
253
254 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
255 apbc_base + APBC_SSP1, 10, 0, &clk_lock);
256 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
257
258 clk = mmp_clk_register_apmu("dfc", "pll1_4",
259 apmu_base + APMU_DFC, 0x19b, &clk_lock);
260 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
261
262 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
263 ARRAY_SIZE(sdh_parent),
264 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
265 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
266 clk_register_clkdev(clk, "sdh0_mux", NULL);
267
268 clk = mmp_clk_register_apmu("sdh0", "sdh_mux",
269 apmu_base + APMU_SDH0, 0x1b, &clk_lock);
270 clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
271
272 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
273 ARRAY_SIZE(sdh_parent),
274 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
275 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
276 clk_register_clkdev(clk, "sdh1_mux", NULL);
277
278 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux",
279 apmu_base + APMU_SDH1, 0x1b, &clk_lock);
280 clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
281
282 clk = mmp_clk_register_apmu("usb", "usb_pll",
283 apmu_base + APMU_USB, 0x9, &clk_lock);
284 clk_register_clkdev(clk, "usb_clk", NULL);
285
286 clk = mmp_clk_register_apmu("sph", "usb_pll",
287 apmu_base + APMU_USB, 0x12, &clk_lock);
288 clk_register_clkdev(clk, "sph_clk", NULL);
289
290 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
291 ARRAY_SIZE(disp_parent),
292 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
293 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
294 clk_register_clkdev(clk, "disp_mux.0", NULL);
295
296 clk = mmp_clk_register_apmu("disp0", "disp0_mux",
297 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
298 clk_register_clkdev(clk, NULL, "mmp-disp.0");
299
300 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
301 ARRAY_SIZE(ccic_parent),
302 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
303 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
304 clk_register_clkdev(clk, "ccic_mux.0", NULL);
305
306 clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
307 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
308 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
309
310 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
311 ARRAY_SIZE(ccic_phy_parent),
312 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
313 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
314 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
315
316 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
317 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
318 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
319
320 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
321 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
322 10, 5, 0, &clk_lock);
323 clk_register_clkdev(clk, "sphyclk_div", NULL);
324
325 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
326 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
327 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
328 }
329
