1 /*
2 * pxa168 clock framework source file
3 *
4 * Copyright (C) 2012 Marvell
5 * Chao Xie <xiechao.mail@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/spinlock.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/of_address.h>
19
20 #include <dt-bindings/clock/marvell,pxa168.h>
21
22 #include "clk.h"
23 #include "reset.h"
24
25 #define APBC_RTC 0x28
26 #define APBC_TWSI0 0x2c
27 #define APBC_KPC 0x30
28 #define APBC_UART0 0x0
29 #define APBC_UART1 0x4
30 #define APBC_GPIO 0x8
31 #define APBC_PWM0 0xc
32 #define APBC_PWM1 0x10
33 #define APBC_PWM2 0x14
34 #define APBC_PWM3 0x18
35 #define APBC_TIMER 0x34
36 #define APBC_SSP0 0x81c
37 #define APBC_SSP1 0x820
38 #define APBC_SSP2 0x84c
39 #define APBC_SSP3 0x858
40 #define APBC_SSP4 0x85c
41 #define APBC_TWSI1 0x6c
42 #define APBC_UART2 0x70
43 #define APMU_SDH0 0x54
44 #define APMU_SDH1 0x58
45 #define APMU_USB 0x5c
46 #define APMU_DISP0 0x4c
47 #define APMU_CCIC0 0x50
48 #define APMU_DFC 0x60
49 #define MPMU_UART_PLL 0x14
50
51 struct pxa168_clk_unit {
52 struct mmp_clk_unit unit;
53 void __iomem *mpmu_base;
54 void __iomem *apmu_base;
55 void __iomem *apbc_base;
56 };
57
58 static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
59 {PXA168_CLK_CLK32, "clk32", NULL, 0, 32768},
60 {PXA168_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
61 {PXA168_CLK_PLL1, "pll1", NULL, 0, 624000000},
62 {PXA168_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
63 };
64
65 static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
66 {PXA168_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
67 {PXA168_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
68 {PXA168_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
69 {PXA168_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
70 {PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
71 {PXA168_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
72 {PXA168_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
73 {PXA168_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
74 {PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
75 {PXA168_CLK_PLL1_192, "pll1_192", "pll1_96", 1, 2, 0},
76 {PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
77 {PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
78 {PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
79 {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
80 };
81
82 static struct mmp_clk_factor_masks uart_factor_masks = {
83 .factor = 2,
84 .num_mask = 0x1fff,
85 .den_mask = 0x1fff,
86 .num_shift = 16,
87 .den_shift = 0,
88 };
89
90 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
91 {.num = 8125, .den = 1536}, /*14.745MHZ */
92 };
93
pxa168_pll_init(struct pxa168_clk_unit * pxa_unit)94 static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit)
95 {
96 struct clk *clk;
97 struct mmp_clk_unit *unit = &pxa_unit->unit;
98
99 mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
100 ARRAY_SIZE(fixed_rate_clks));
101
102 mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
103 ARRAY_SIZE(fixed_factor_clks));
104
105 clk = mmp_clk_register_factor("uart_pll", "pll1_4",
106 CLK_SET_RATE_PARENT,
107 pxa_unit->mpmu_base + MPMU_UART_PLL,
108 &uart_factor_masks, uart_factor_tbl,
109 ARRAY_SIZE(uart_factor_tbl), NULL);
110 mmp_clk_add(unit, PXA168_CLK_UART_PLL, clk);
111 }
112
113 static DEFINE_SPINLOCK(uart0_lock);
114 static DEFINE_SPINLOCK(uart1_lock);
115 static DEFINE_SPINLOCK(uart2_lock);
116 static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
117
118 static DEFINE_SPINLOCK(ssp0_lock);
119 static DEFINE_SPINLOCK(ssp1_lock);
120 static DEFINE_SPINLOCK(ssp2_lock);
121 static DEFINE_SPINLOCK(ssp3_lock);
122 static DEFINE_SPINLOCK(ssp4_lock);
123 static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
124
125 static DEFINE_SPINLOCK(timer_lock);
126 static const char *timer_parent_names[] = {"pll1_48", "clk32", "pll1_96", "pll1_192"};
127
128 static DEFINE_SPINLOCK(reset_lock);
129
130 static struct mmp_param_mux_clk apbc_mux_clks[] = {
131 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
132 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
133 {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
134 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
135 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
136 {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
137 {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
138 {0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4, 3, 0, &ssp4_lock},
139 {0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER, 4, 3, 0, &timer_lock},
140 };
141
142 static struct mmp_param_gate_clk apbc_gate_clks[] = {
143 {PXA168_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
144 {PXA168_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
145 {PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
146 {PXA168_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
147 {PXA168_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
148 {PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
149 {PXA168_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
150 {PXA168_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
151 {PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
152 /* The gate clocks has mux parent. */
153 {PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
154 {PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
155 {PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
156 {PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
157 {PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
158 {PXA168_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x3, 0x3, 0x0, 0, &ssp2_lock},
159 {PXA168_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x3, 0x3, 0x0, 0, &ssp3_lock},
160 {PXA168_CLK_SSP4, "ssp4_clk", "ssp4_mux", CLK_SET_RATE_PARENT, APBC_SSP4, 0x3, 0x3, 0x0, 0, &ssp4_lock},
161 {PXA168_CLK_TIMER, "timer_clk", "timer_mux", CLK_SET_RATE_PARENT, APBC_TIMER, 0x3, 0x3, 0x0, 0, &timer_lock},
162 };
163
pxa168_apb_periph_clk_init(struct pxa168_clk_unit * pxa_unit)164 static void pxa168_apb_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
165 {
166 struct mmp_clk_unit *unit = &pxa_unit->unit;
167
168 mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
169 ARRAY_SIZE(apbc_mux_clks));
170
171 mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
172 ARRAY_SIZE(apbc_gate_clks));
173
174 }
175
176 static DEFINE_SPINLOCK(sdh0_lock);
177 static DEFINE_SPINLOCK(sdh1_lock);
178 static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
179
180 static DEFINE_SPINLOCK(usb_lock);
181
182 static DEFINE_SPINLOCK(disp0_lock);
183 static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
184
185 static DEFINE_SPINLOCK(ccic0_lock);
186 static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
187 static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
188
189 static struct mmp_param_mux_clk apmu_mux_clks[] = {
190 {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
191 {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
192 {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
193 {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
194 {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
195 };
196
197 static struct mmp_param_div_clk apmu_div_clks[] = {
198 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
199 };
200
201 static struct mmp_param_gate_clk apmu_gate_clks[] = {
202 {PXA168_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
203 {PXA168_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
204 {PXA168_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
205 /* The gate clocks has mux parent. */
206 {PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
207 {PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
208 {PXA168_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
209 {PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
210 {PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
211 {PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
212 };
213
pxa168_axi_periph_clk_init(struct pxa168_clk_unit * pxa_unit)214 static void pxa168_axi_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
215 {
216 struct mmp_clk_unit *unit = &pxa_unit->unit;
217
218 mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
219 ARRAY_SIZE(apmu_mux_clks));
220
221 mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
222 ARRAY_SIZE(apmu_div_clks));
223
224 mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
225 ARRAY_SIZE(apmu_gate_clks));
226 }
227
pxa168_clk_reset_init(struct device_node * np,struct pxa168_clk_unit * pxa_unit)228 static void pxa168_clk_reset_init(struct device_node *np,
229 struct pxa168_clk_unit *pxa_unit)
230 {
231 struct mmp_clk_reset_cell *cells;
232 int i, nr_resets;
233
234 nr_resets = ARRAY_SIZE(apbc_gate_clks);
235 cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
236 if (!cells)
237 return;
238
239 for (i = 0; i < nr_resets; i++) {
240 cells[i].clk_id = apbc_gate_clks[i].id;
241 cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
242 cells[i].flags = 0;
243 cells[i].lock = apbc_gate_clks[i].lock;
244 cells[i].bits = 0x4;
245 }
246
247 mmp_clk_reset_register(np, cells, nr_resets);
248 }
249
pxa168_clk_init(struct device_node * np)250 static void __init pxa168_clk_init(struct device_node *np)
251 {
252 struct pxa168_clk_unit *pxa_unit;
253
254 pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
255 if (!pxa_unit)
256 return;
257
258 pxa_unit->mpmu_base = of_iomap(np, 0);
259 if (!pxa_unit->mpmu_base) {
260 pr_err("failed to map mpmu registers\n");
261 return;
262 }
263
264 pxa_unit->apmu_base = of_iomap(np, 1);
265 if (!pxa_unit->apmu_base) {
266 pr_err("failed to map apmu registers\n");
267 return;
268 }
269
270 pxa_unit->apbc_base = of_iomap(np, 2);
271 if (!pxa_unit->apbc_base) {
272 pr_err("failed to map apbc registers\n");
273 return;
274 }
275
276 mmp_clk_init(np, &pxa_unit->unit, PXA168_NR_CLKS);
277
278 pxa168_pll_init(pxa_unit);
279
280 pxa168_apb_periph_clk_init(pxa_unit);
281
282 pxa168_axi_periph_clk_init(pxa_unit);
283
284 pxa168_clk_reset_init(np, pxa_unit);
285 }
286
287 CLK_OF_DECLARE(pxa168_clk, "marvell,pxa168-clock", pxa168_clk_init);
288
