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Searched +full:pll0 +full:- +full:refclk (Results 1 – 13 of 13) sorted by relevance

/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dmicrochip,mpfs-ccc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Conor Dooley <conor.dooley@microchip.com>
16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
20 const: microchip,mpfs-ccc
24 - description: PLL0's control registers
25 - description: PLL1's control registers
26 - description: DLL0's control registers
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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,am64-wiz-10g
19 - ti,j7200-wiz-10g
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/Linux-v6.1/drivers/ata/
Dahci_da850.c1 // SPDX-License-Identifier: GPL-2.0-or-later
51 * the refclk rate by ten. in ahci_da850_calculate_mpy()
56 WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10"); in ahci_da850_calculate_mpy()
86 * We should have divided evenly - if not, return an invalid in ahci_da850_calculate_mpy()
108 if (pmp && ret == -EBUSY) in ahci_da850_softreset()
123 * we increased the PLL0 frequency to 456MHz from the default 300MHz. in ahci_da850_hardreset()
133 } while (retry--); in ahci_da850_hardreset()
142 * No need to override .pmp_softreset - it's only used for actual
143 * PMP-enabled ports.
162 struct device *dev = &pdev->dev; in ahci_da850_probe()
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/Linux-v6.1/drivers/phy/ti/
Dphy-j721e-wiz.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
13 #include <linux/clk-provider.h>
25 #include <linux/reset-controller.h>
111 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
112 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
113 [TI_WIZ_REFCLK_DIG] = "refclk-dig",
114 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk",
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/Linux-v6.1/arch/arm64/boot/dts/ti/
Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
10 #include <dt-bindings/mux/ti-serdes.h>
13 cmn_refclk: clock-cmnrefclk {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <0>;
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Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
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/Linux-v6.1/drivers/clk/renesas/
Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
62 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate()
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/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c2 * Copyright © 2006-2016 Intel Corporation
40 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
117 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
118 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
120 shared_dpll[i] = pll->state; in intel_atomic_duplicate_dpll_state()
129 drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); in intel_atomic_get_shared_dpll_state()
131 if (!state->dpll_set) { in intel_atomic_get_shared_dpll_state()
132 state->dpll_set = true; in intel_atomic_get_shared_dpll_state()
134 intel_atomic_duplicate_dpll_state(to_i915(s->dev), in intel_atomic_get_shared_dpll_state()
135 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
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Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
32 #include <linux/dma-resv.h>
134 * intel_update_watermarks - update FIFO watermark values based on current modes
141 * - normal (i.e. non-self-refresh)
142 * - self-refresh (SR) mode
143 * - lines are large relative to FIFO size (buffer can hold up to 2)
144 * - lines are small relative to FIFO size (buffer can hold more than 2
164 * to set the non-SR watermarks to 8.
168 if (dev_priv->display.funcs.wm->update_wm) in intel_update_watermarks()
169 dev_priv->display.funcs.wm->update_wm(dev_priv); in intel_update_watermarks()
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/Linux-v6.1/drivers/clk/
Dclk-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
51 val = readl_relaxed(pll->pllcon); in npcm7xx_clk_pll_recalc_rate()
79 return ERR_PTR(-ENOMEM); in npcm7xx_clk_register_pll()
89 pll->pllcon = pllcon; in npcm7xx_clk_register_pll()
90 pll->hw.init = &init; in npcm7xx_clk_register_pll()
92 hw = &pll->hw; in npcm7xx_clk_register_pll()
142 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
143 * this specific clock. Otherwise, set to -1.
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/Linux-v6.1/arch/arm/boot/dts/
Dda850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
28 operating-points-v2 = <&opp_table>;
32 opp_table: opp-table {
33 compatible = "operating-points-v2";
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/Linux-v6.1/drivers/phy/broadcom/
Dphy-brcm-sata.c1 // SPDX-License-Identifier: GPL-2.0-or-later
196 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
199 switch (priv->version) { in brcm_sata_ctrl_base()
204 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
214 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
215 void __iomem *pcb_base = priv->phy_base; in brcm_sata_phy_wr()
218 if (priv->version == BRCM_SATA_PHY_STB_40NM) in brcm_sata_phy_wr()
219 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); in brcm_sata_phy_wr()
221 pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE); in brcm_sata_phy_wr()
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/Linux-v6.1/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
241 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
242 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
243 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
424 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_write()
426 writew(val, ctx->base + offset); in cdns_regmap_write()
434 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_read()
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