Lines Matching +full:pll0 +full:- +full:refclk
2 * Copyright © 2006-2007 Intel Corporation
32 #include <linux/dma-resv.h>
134 * intel_update_watermarks - update FIFO watermark values based on current modes
141 * - normal (i.e. non-self-refresh)
142 * - self-refresh (SR) mode
143 * - lines are large relative to FIFO size (buffer can hold up to 2)
144 * - lines are small relative to FIFO size (buffer can hold more than 2
164 * to set the non-SR watermarks to 8.
168 if (dev_priv->display.funcs.wm->update_wm) in intel_update_watermarks()
169 dev_priv->display.funcs.wm->update_wm(dev_priv); in intel_update_watermarks()
175 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_compute_pipe_wm()
176 if (dev_priv->display.funcs.wm->compute_pipe_wm) in intel_compute_pipe_wm()
177 return dev_priv->display.funcs.wm->compute_pipe_wm(state, crtc); in intel_compute_pipe_wm()
184 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_compute_intermediate_wm()
185 if (!dev_priv->display.funcs.wm->compute_intermediate_wm) in intel_compute_intermediate_wm()
187 if (drm_WARN_ON(&dev_priv->drm, in intel_compute_intermediate_wm()
188 !dev_priv->display.funcs.wm->compute_pipe_wm)) in intel_compute_intermediate_wm()
190 return dev_priv->display.funcs.wm->compute_intermediate_wm(state, crtc); in intel_compute_intermediate_wm()
196 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_initial_watermarks()
197 if (dev_priv->display.funcs.wm->initial_watermarks) { in intel_initial_watermarks()
198 dev_priv->display.funcs.wm->initial_watermarks(state, crtc); in intel_initial_watermarks()
207 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_update_watermarks()
208 if (dev_priv->display.funcs.wm->atomic_update_watermarks) in intel_atomic_update_watermarks()
209 dev_priv->display.funcs.wm->atomic_update_watermarks(state, crtc); in intel_atomic_update_watermarks()
215 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_optimize_watermarks()
216 if (dev_priv->display.funcs.wm->optimize_watermarks) in intel_optimize_watermarks()
217 dev_priv->display.funcs.wm->optimize_watermarks(state, crtc); in intel_optimize_watermarks()
222 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_compute_global_watermarks()
223 if (dev_priv->display.funcs.wm->compute_global_watermarks) in intel_compute_global_watermarks()
224 return dev_priv->display.funcs.wm->compute_global_watermarks(state); in intel_compute_global_watermarks()
249 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
263 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
264 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
266 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
278 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
281 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
282 dev_priv->czclk_freq); in intel_update_czclk()
287 return (crtc_state->active_planes & in is_hdr_mode()
328 return crtc_state->master_transcoder != INVALID_TRANSCODER; in is_trans_port_sync_slave()
334 return crtc_state->sync_mode_slaves_mask != 0; in is_trans_port_sync_master()
346 return ffs(crtc_state->bigjoiner_pipes) - 1; in bigjoiner_master_pipe()
351 if (crtc_state->bigjoiner_pipes) in intel_crtc_bigjoiner_slave_pipes()
352 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); in intel_crtc_bigjoiner_slave_pipes()
359 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_is_bigjoiner_slave()
361 return crtc_state->bigjoiner_pipes && in intel_crtc_is_bigjoiner_slave()
362 crtc->pipe != bigjoiner_master_pipe(crtc_state); in intel_crtc_is_bigjoiner_slave()
367 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_is_bigjoiner_master()
369 return crtc_state->bigjoiner_pipes && in intel_crtc_is_bigjoiner_master()
370 crtc->pipe == bigjoiner_master_pipe(crtc_state); in intel_crtc_is_bigjoiner_master()
375 return hweight8(crtc_state->bigjoiner_pipes); in intel_bigjoiner_num_pipes()
380 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_master_crtc()
385 return to_intel_crtc(crtc_state->uapi.crtc); in intel_master_crtc()
403 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in wait_for_pipe_scanline_moving()
404 enum pipe pipe = crtc->pipe; in wait_for_pipe_scanline_moving()
408 drm_err(&dev_priv->drm, in wait_for_pipe_scanline_moving()
426 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in intel_wait_for_pipe_off()
427 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_wait_for_pipe_off()
430 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; in intel_wait_for_pipe_off()
435 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); in intel_wait_for_pipe_off()
474 cur_state = plane->get_hw_state(plane, &pipe); in assert_plane()
478 plane->base.name, str_on_off(state), in assert_plane()
487 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in assert_planes_disabled()
490 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in assert_planes_disabled()
501 switch (dig_port->base.port) { in vlv_wait_port_ready()
503 MISSING_CASE(dig_port->base.port); in vlv_wait_port_ready()
522 drm_WARN(&dev_priv->drm, 1, in vlv_wait_port_ready()
524 dig_port->base.base.base.id, dig_port->base.base.name, in vlv_wait_port_ready()
531 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); in intel_enable_transcoder()
532 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_enable_transcoder()
533 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; in intel_enable_transcoder()
534 enum pipe pipe = crtc->pipe; in intel_enable_transcoder()
538 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); in intel_enable_transcoder()
553 if (new_crtc_state->has_pch_encoder) { in intel_enable_transcoder()
563 /* Wa_22012358565:adl-p */ in intel_enable_transcoder()
572 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); in intel_enable_transcoder()
592 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in intel_disable_transcoder()
593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_disable_transcoder()
594 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; in intel_disable_transcoder()
595 enum pipe pipe = crtc->pipe; in intel_disable_transcoder()
599 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); in intel_disable_transcoder()
616 if (old_crtc_state->double_wide) in intel_disable_transcoder()
640 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) in intel_rotation_info_size()
641 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; in intel_rotation_info_size()
651 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { in intel_remapped_info_size()
654 if (rem_info->plane[i].linear) in intel_remapped_info_size()
655 plane_size = rem_info->plane[i].size; in intel_remapped_info_size()
657 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; in intel_remapped_info_size()
662 if (rem_info->plane_alignment) in intel_remapped_info_size()
663 size = ALIGN(size, rem_info->plane_alignment); in intel_remapped_info_size()
673 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_plane_uses_fence()
674 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in intel_plane_uses_fence()
677 (plane->fbc && in intel_plane_uses_fence()
678 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); in intel_plane_uses_fence()
684 * offset is only used with linear buffers on pre-hsw and tiled buffers
691 const struct drm_framebuffer *fb = state->hw.fb; in intel_fb_xy_to_linear()
692 unsigned int cpp = fb->format->cpp[color_plane]; in intel_fb_xy_to_linear()
693 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; in intel_fb_xy_to_linear()
699 * Add the x/y offsets derived from fb->offsets[] to the user
708 *x += state->view.color_plane[color_plane].x; in intel_add_fb_offsets()
709 *y += state->view.color_plane[color_plane].y; in intel_add_fb_offsets()
730 plane = to_intel_plane(crtc->base.primary); in intel_plane_fb_max_stride()
732 return plane->max_stride(plane, pixel_format, modifier, in intel_plane_fb_max_stride()
740 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_set_plane_visible()
742 plane_state->uapi.visible = visible; in intel_set_plane_visible()
745 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); in intel_set_plane_visible()
747 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); in intel_set_plane_visible()
752 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_plane_fixup_bitmasks()
760 crtc_state->enabled_planes = 0; in intel_plane_fixup_bitmasks()
761 crtc_state->active_planes = 0; in intel_plane_fixup_bitmasks()
763 drm_for_each_plane_mask(plane, &dev_priv->drm, in intel_plane_fixup_bitmasks()
764 crtc_state->uapi.plane_mask) { in intel_plane_fixup_bitmasks()
765 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); in intel_plane_fixup_bitmasks()
766 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); in intel_plane_fixup_bitmasks()
773 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_plane_disable_noatomic()
775 to_intel_crtc_state(crtc->base.state); in intel_plane_disable_noatomic()
777 to_intel_plane_state(plane->base.state); in intel_plane_disable_noatomic()
779 drm_dbg_kms(&dev_priv->drm, in intel_plane_disable_noatomic()
781 plane->base.base.id, plane->base.name, in intel_plane_disable_noatomic()
782 crtc->base.base.id, crtc->base.name); in intel_plane_disable_noatomic()
786 crtc_state->data_rate[plane->id] = 0; in intel_plane_disable_noatomic()
787 crtc_state->data_rate_y[plane->id] = 0; in intel_plane_disable_noatomic()
788 crtc_state->rel_data_rate[plane->id] = 0; in intel_plane_disable_noatomic()
789 crtc_state->rel_data_rate_y[plane->id] = 0; in intel_plane_disable_noatomic()
790 crtc_state->min_cdclk[plane->id] = 0; in intel_plane_disable_noatomic()
792 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && in intel_plane_disable_noatomic()
794 crtc_state->ips_enabled = false; in intel_plane_disable_noatomic()
800 * are blocked if the memory self-refresh mode is active at that in intel_plane_disable_noatomic()
802 * first the self-refresh mode. The self-refresh enable bit in turn in intel_plane_disable_noatomic()
805 * wait-for-vblank between disabling the plane and the pipe. in intel_plane_disable_noatomic()
815 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) in intel_plane_disable_noatomic()
816 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); in intel_plane_disable_noatomic()
828 plane_state->view.color_plane[0].offset, 0); in intel_plane_fence_y_offset()
859 crtc_state->mode_changed = true; in __intel_display_resume()
864 to_intel_atomic_state(state)->skip_intermediate_wm = true; in __intel_display_resume()
868 drm_WARN_ON(&i915->drm, ret == -EDEADLK); in __intel_display_resume()
875 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && in gpu_reset_clobbers_display()
881 struct drm_device *dev = &dev_priv->drm; in intel_display_prepare_reset()
882 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; in intel_display_prepare_reset()
890 if (!dev_priv->params.force_reset_modeset_test && in intel_display_prepare_reset()
895 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); in intel_display_prepare_reset()
897 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); in intel_display_prepare_reset()
899 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { in intel_display_prepare_reset()
900 drm_dbg_kms(&dev_priv->drm, in intel_display_prepare_reset()
907 * trample ongoing ->detect() and whatnot. in intel_display_prepare_reset()
909 mutex_lock(&dev->mode_config.mutex); in intel_display_prepare_reset()
913 if (ret != -EDEADLK) in intel_display_prepare_reset()
925 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", in intel_display_prepare_reset()
932 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", in intel_display_prepare_reset()
938 dev_priv->modeset_restore_state = state; in intel_display_prepare_reset()
939 state->acquire_ctx = ctx; in intel_display_prepare_reset()
944 struct drm_modeset_acquire_ctx *ctx = &i915->reset_ctx; in intel_display_finish_reset()
952 if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags)) in intel_display_finish_reset()
955 state = fetch_and_zero(&i915->modeset_restore_state); in intel_display_finish_reset()
964 drm_err(&i915->drm, in intel_display_finish_reset()
969 * so need a full re-initialization. in intel_display_finish_reset()
978 drm_err(&i915->drm, in intel_display_finish_reset()
988 mutex_unlock(&i915->drm.mode_config.mutex); in intel_display_finish_reset()
990 clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags); in intel_display_finish_reset()
995 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in icl_set_pipe_chicken()
996 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in icl_set_pipe_chicken()
997 enum pipe pipe = crtc->pipe; in icl_set_pipe_chicken()
1005 * and rounding for per-pixel values 00 and 0xff in icl_set_pipe_chicken()
1037 drm_for_each_crtc(crtc, &dev_priv->drm) { in intel_has_pending_fb_unpin()
1039 spin_lock(&crtc->commit_lock); in intel_has_pending_fb_unpin()
1040 commit = list_first_entry_or_null(&crtc->commit_list, in intel_has_pending_fb_unpin()
1043 try_wait_for_completion(&commit->cleanup_done) : true; in intel_has_pending_fb_unpin()
1044 spin_unlock(&crtc->commit_lock); in intel_has_pending_fb_unpin()
1074 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { in intel_get_crtc_new_encoder()
1075 if (connector_state->crtc != &master_crtc->base) in intel_get_crtc_new_encoder()
1078 encoder = to_intel_encoder(connector_state->best_encoder); in intel_get_crtc_new_encoder()
1082 drm_WARN(encoder->base.dev, num_encoders != 1, in intel_get_crtc_new_encoder()
1084 num_encoders, pipe_name(master_crtc->pipe)); in intel_get_crtc_new_encoder()
1099 drm_err(&dev_priv->drm, in cpt_verify_modeset()
1107 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_pfit_enable()
1108 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_pfit_enable()
1109 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; in ilk_pfit_enable()
1110 enum pipe pipe = crtc->pipe; in ilk_pfit_enable()
1113 int x = dst->x1; in ilk_pfit_enable()
1114 int y = dst->y1; in ilk_pfit_enable()
1116 if (!crtc_state->pch_pfit.enabled) in ilk_pfit_enable()
1119 /* Force use of hard-coded filter coefficients in ilk_pfit_enable()
1120 * as some pre-programmed values are broken, in ilk_pfit_enable()
1135 if (crtc->overlay) in intel_crtc_dpms_overlay_disable()
1136 (void) intel_overlay_switch_off(crtc->overlay); in intel_crtc_dpms_overlay_disable()
1145 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in needs_nv12_wa()
1147 if (!crtc_state->nv12_planes) in needs_nv12_wa()
1159 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in needs_scalerclk_wa()
1162 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) in needs_scalerclk_wa()
1170 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in needs_cursorclk_wa()
1174 crtc_state->active_planes & BIT(PLANE_CURSOR) && in needs_cursorclk_wa()
1202 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in needs_async_flip_vtd_wa()
1204 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && in needs_async_flip_vtd_wa()
1211 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && in planes_enabling()
1212 new_crtc_state->active_planes; in planes_enabling()
1218 return old_crtc_state->active_planes && in planes_disabling()
1219 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); in planes_disabling()
1225 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_post_plane_update()
1230 enum pipe pipe = crtc->pipe; in intel_post_plane_update()
1232 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); in intel_post_plane_update()
1234 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) in intel_post_plane_update()
1264 u8 update_planes = crtc_state->update_planes; in intel_crtc_enable_flip_done()
1270 if (plane->pipe == crtc->pipe && in intel_crtc_enable_flip_done()
1271 update_planes & BIT(plane->id)) in intel_crtc_enable_flip_done()
1272 plane->enable_flip_done(plane); in intel_crtc_enable_flip_done()
1281 u8 update_planes = crtc_state->update_planes; in intel_crtc_disable_flip_done()
1287 if (plane->pipe == crtc->pipe && in intel_crtc_disable_flip_done()
1288 update_planes & BIT(plane->id)) in intel_crtc_disable_flip_done()
1289 plane->disable_flip_done(plane); in intel_crtc_disable_flip_done()
1300 u8 update_planes = new_crtc_state->update_planes; in intel_crtc_async_flip_disable_wa()
1307 if (plane->need_async_flip_disable_wa && in intel_crtc_async_flip_disable_wa()
1308 plane->pipe == crtc->pipe && in intel_crtc_async_flip_disable_wa()
1309 update_planes & BIT(plane->id)) { in intel_crtc_async_flip_disable_wa()
1314 plane->async_flip(plane, old_crtc_state, in intel_crtc_async_flip_disable_wa()
1327 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_pre_plane_update()
1332 enum pipe pipe = crtc->pipe; in intel_pre_plane_update()
1365 * are blocked if the memory self-refresh mode is active at that in intel_pre_plane_update()
1367 * first the self-refresh mode. The self-refresh enable bit in turn in intel_pre_plane_update()
1370 * wait-for-vblank between disabling the plane and the pipe. in intel_pre_plane_update()
1372 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && in intel_pre_plane_update()
1373 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) in intel_pre_plane_update()
1378 * one frame before enabling scaling. LP watermarks can be re-enabled in intel_pre_plane_update()
1383 if (old_crtc_state->hw.active && in intel_pre_plane_update()
1384 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) in intel_pre_plane_update()
1389 * pre-vblank watermark programming here. in intel_pre_plane_update()
1394 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these in intel_pre_plane_update()
1395 * will be the intermediate values that are safe for both pre- and in intel_pre_plane_update()
1396 * post- vblank; when vblank happens, the 'active' values will be set in intel_pre_plane_update()
1407 if (new_crtc_state->update_wm_pre) in intel_pre_plane_update()
1426 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip) in intel_pre_plane_update()
1433 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_disable_planes()
1436 unsigned int update_mask = new_crtc_state->update_planes; in intel_crtc_disable_planes()
1445 if (crtc->pipe != plane->pipe || in intel_crtc_disable_planes()
1446 !(update_mask & BIT(plane->id))) in intel_crtc_disable_planes()
1451 if (old_plane_state->uapi.visible) in intel_crtc_disable_planes()
1452 fb_bits |= plane->frontbuffer_bit; in intel_crtc_disable_planes()
1459 * intel_connector_primary_encoder - get the primary encoder for a connector
1463 * all connectors to their encoder, except for DP-MST connectors which have
1464 * both a virtual and a primary encoder. These DP-MST primary encoders can be
1465 * pointed to by as many DP-MST connectors as there are pipes.
1472 if (connector->mst_port) in intel_connector_primary_encoder()
1473 return &dp_to_dig_port(connector->mst_port)->base; in intel_connector_primary_encoder()
1476 drm_WARN_ON(connector->base.dev, !encoder); in intel_connector_primary_encoder()
1483 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_encoders_update_prepare()
1491 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. in intel_encoders_update_prepare()
1492 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. in intel_encoders_update_prepare()
1494 if (i915->display.dpll.mgr) { in intel_encoders_update_prepare()
1499 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; in intel_encoders_update_prepare()
1500 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; in intel_encoders_update_prepare()
1504 if (!state->modeset) in intel_encoders_update_prepare()
1507 for_each_new_connector_in_state(&state->base, connector, new_conn_state, in intel_encoders_update_prepare()
1518 if (!encoder->update_prepare) in intel_encoders_update_prepare()
1521 crtc = new_conn_state->crtc ? in intel_encoders_update_prepare()
1522 to_intel_crtc(new_conn_state->crtc) : NULL; in intel_encoders_update_prepare()
1523 encoder->update_prepare(state, encoder, crtc); in intel_encoders_update_prepare()
1533 if (!state->modeset) in intel_encoders_update_complete()
1536 for_each_new_connector_in_state(&state->base, connector, new_conn_state, in intel_encoders_update_complete()
1547 if (!encoder->update_complete) in intel_encoders_update_complete()
1550 crtc = new_conn_state->crtc ? in intel_encoders_update_complete()
1551 to_intel_crtc(new_conn_state->crtc) : NULL; in intel_encoders_update_complete()
1552 encoder->update_complete(state, encoder, crtc); in intel_encoders_update_complete()
1565 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in intel_encoders_pre_pll_enable()
1567 to_intel_encoder(conn_state->best_encoder); in intel_encoders_pre_pll_enable()
1569 if (conn_state->crtc != &crtc->base) in intel_encoders_pre_pll_enable()
1572 if (encoder->pre_pll_enable) in intel_encoders_pre_pll_enable()
1573 encoder->pre_pll_enable(state, encoder, in intel_encoders_pre_pll_enable()
1587 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in intel_encoders_pre_enable()
1589 to_intel_encoder(conn_state->best_encoder); in intel_encoders_pre_enable()
1591 if (conn_state->crtc != &crtc->base) in intel_encoders_pre_enable()
1594 if (encoder->pre_enable) in intel_encoders_pre_enable()
1595 encoder->pre_enable(state, encoder, in intel_encoders_pre_enable()
1609 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in intel_encoders_enable()
1611 to_intel_encoder(conn_state->best_encoder); in intel_encoders_enable()
1613 if (conn_state->crtc != &crtc->base) in intel_encoders_enable()
1616 if (encoder->enable) in intel_encoders_enable()
1617 encoder->enable(state, encoder, in intel_encoders_enable()
1632 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { in intel_encoders_disable()
1634 to_intel_encoder(old_conn_state->best_encoder); in intel_encoders_disable()
1636 if (old_conn_state->crtc != &crtc->base) in intel_encoders_disable()
1640 if (encoder->disable) in intel_encoders_disable()
1641 encoder->disable(state, encoder, in intel_encoders_disable()
1655 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { in intel_encoders_post_disable()
1657 to_intel_encoder(old_conn_state->best_encoder); in intel_encoders_post_disable()
1659 if (old_conn_state->crtc != &crtc->base) in intel_encoders_post_disable()
1662 if (encoder->post_disable) in intel_encoders_post_disable()
1663 encoder->post_disable(state, encoder, in intel_encoders_post_disable()
1677 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { in intel_encoders_post_pll_disable()
1679 to_intel_encoder(old_conn_state->best_encoder); in intel_encoders_post_pll_disable()
1681 if (old_conn_state->crtc != &crtc->base) in intel_encoders_post_pll_disable()
1684 if (encoder->post_pll_disable) in intel_encoders_post_pll_disable()
1685 encoder->post_pll_disable(state, encoder, in intel_encoders_post_pll_disable()
1699 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in intel_encoders_update_pipe()
1701 to_intel_encoder(conn_state->best_encoder); in intel_encoders_update_pipe()
1703 if (conn_state->crtc != &crtc->base) in intel_encoders_update_pipe()
1706 if (encoder->update_pipe) in intel_encoders_update_pipe()
1707 encoder->update_pipe(state, encoder, in intel_encoders_update_pipe()
1714 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_disable_primary_plane()
1715 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in intel_disable_primary_plane()
1717 plane->disable_arm(plane, crtc_state); in intel_disable_primary_plane()
1722 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_configure_cpu_transcoder()
1723 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in ilk_configure_cpu_transcoder()
1725 if (crtc_state->has_pch_encoder) { in ilk_configure_cpu_transcoder()
1727 &crtc_state->fdi_m_n); in ilk_configure_cpu_transcoder()
1730 &crtc_state->dp_m_n); in ilk_configure_cpu_transcoder()
1732 &crtc_state->dp_m2_n2); in ilk_configure_cpu_transcoder()
1745 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_crtc_enable()
1746 enum pipe pipe = crtc->pipe; in ilk_crtc_enable()
1748 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) in ilk_crtc_enable()
1768 crtc->active = true; in ilk_crtc_enable()
1772 if (new_crtc_state->has_pch_encoder) { in ilk_crtc_enable()
1794 if (new_crtc_state->has_pch_encoder) in ilk_crtc_enable()
1810 if (new_crtc_state->has_pch_encoder) { in ilk_crtc_enable()
1834 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_set_linetime_wm()
1835 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_set_linetime_wm()
1837 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), in hsw_set_linetime_wm()
1838 HSW_LINETIME(crtc_state->linetime) | in hsw_set_linetime_wm()
1839 HSW_IPS_LINETIME(crtc_state->ips_linetime)); in hsw_set_linetime_wm()
1844 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_set_frame_start_delay()
1845 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_set_frame_start_delay()
1846 enum transcoder transcoder = crtc_state->cpu_transcoder; in hsw_set_frame_start_delay()
1853 val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1); in hsw_set_frame_start_delay()
1863 * Enable sequence steps 1-7 on bigjoiner master in icl_ddi_bigjoiner_pre_enable()
1868 if (crtc_state->shared_dpll) in icl_ddi_bigjoiner_pre_enable()
1877 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_configure_cpu_transcoder()
1878 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_configure_cpu_transcoder()
1879 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_configure_cpu_transcoder()
1881 if (crtc_state->has_pch_encoder) { in hsw_configure_cpu_transcoder()
1883 &crtc_state->fdi_m_n); in hsw_configure_cpu_transcoder()
1886 &crtc_state->dp_m_n); in hsw_configure_cpu_transcoder()
1888 &crtc_state->dp_m2_n2); in hsw_configure_cpu_transcoder()
1895 crtc_state->pixel_multiplier - 1); in hsw_configure_cpu_transcoder()
1907 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_crtc_enable()
1908 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; in hsw_crtc_enable()
1909 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; in hsw_crtc_enable()
1912 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) in hsw_crtc_enable()
1915 if (!new_crtc_state->bigjoiner_pipes) { in hsw_crtc_enable()
1918 if (new_crtc_state->shared_dpll) in hsw_crtc_enable()
1939 crtc->active = true; in hsw_crtc_enable()
1943 new_crtc_state->pch_pfit.enabled; in hsw_crtc_enable()
1982 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; in hsw_crtc_enable()
1995 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in ilk_pfit_disable()
1996 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_pfit_disable()
1997 enum pipe pipe = crtc->pipe; in ilk_pfit_disable()
2001 if (!old_crtc_state->pch_pfit.enabled) in ilk_pfit_disable()
2014 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_crtc_disable()
2015 enum pipe pipe = crtc->pipe; in ilk_crtc_disable()
2033 if (old_crtc_state->has_pch_encoder) in ilk_crtc_disable()
2038 if (old_crtc_state->has_pch_encoder) in ilk_crtc_disable()
2053 * Need care with mst->ddi interactions. in hsw_crtc_disable()
2063 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_pfit_enable()
2064 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_pfit_enable()
2066 if (!crtc_state->gmch_pfit.control) in i9xx_pfit_enable()
2073 drm_WARN_ON(&dev_priv->drm, in i9xx_pfit_enable()
2075 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_pfit_enable()
2078 crtc_state->gmch_pfit.pgm_ratios); in i9xx_pfit_enable()
2079 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); in i9xx_pfit_enable()
2083 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); in i9xx_pfit_enable()
2139 return PHY_D + port - PORT_D_XELPD; in intel_port_to_phy()
2141 return PHY_F + port - PORT_TC1; in intel_port_to_phy()
2143 return PHY_B + port - PORT_TC1; in intel_port_to_phy()
2145 return PHY_C + port - PORT_TC1; in intel_port_to_phy()
2149 return PHY_A + port - PORT_A; in intel_port_to_phy()
2158 return TC_PORT_1 + port - PORT_TC1; in intel_port_to_tc()
2160 return TC_PORT_1 + port - PORT_C; in intel_port_to_tc()
2166 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_aux_power_domain()
2169 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); in intel_aux_power_domain()
2171 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); in intel_aux_power_domain()
2177 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in get_crtc_power_domains()
2178 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in get_crtc_power_domains()
2179 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in get_crtc_power_domains()
2181 enum pipe pipe = crtc->pipe; in get_crtc_power_domains()
2183 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); in get_crtc_power_domains()
2185 if (!crtc_state->hw.active) in get_crtc_power_domains()
2188 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); in get_crtc_power_domains()
2189 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); in get_crtc_power_domains()
2190 if (crtc_state->pch_pfit.enabled || in get_crtc_power_domains()
2191 crtc_state->pch_pfit.force_thru) in get_crtc_power_domains()
2192 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); in get_crtc_power_domains()
2194 drm_for_each_encoder_mask(encoder, &dev_priv->drm, in get_crtc_power_domains()
2195 crtc_state->uapi.encoder_mask) { in get_crtc_power_domains()
2198 set_bit(intel_encoder->power_domain, mask->bits); in get_crtc_power_domains()
2201 if (HAS_DDI(dev_priv) && crtc_state->has_audio) in get_crtc_power_domains()
2202 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); in get_crtc_power_domains()
2204 if (crtc_state->shared_dpll) in get_crtc_power_domains()
2205 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); in get_crtc_power_domains()
2207 if (crtc_state->dsc.compression_enable) in get_crtc_power_domains()
2208 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); in get_crtc_power_domains()
2214 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_modeset_get_crtc_power_domains()
2215 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_modeset_get_crtc_power_domains()
2223 crtc->enabled_power_domains.mask.bits, in intel_modeset_get_crtc_power_domains()
2225 bitmap_andnot(old_domains->bits, in intel_modeset_get_crtc_power_domains()
2226 crtc->enabled_power_domains.mask.bits, in intel_modeset_get_crtc_power_domains()
2232 &crtc->enabled_power_domains, in intel_modeset_get_crtc_power_domains()
2239 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), in intel_modeset_put_crtc_power_domains()
2240 &crtc->enabled_power_domains, in intel_modeset_put_crtc_power_domains()
2246 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_configure_cpu_transcoder()
2247 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in i9xx_configure_cpu_transcoder()
2251 &crtc_state->dp_m_n); in i9xx_configure_cpu_transcoder()
2253 &crtc_state->dp_m2_n2); in i9xx_configure_cpu_transcoder()
2266 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in valleyview_crtc_enable()
2267 enum pipe pipe = crtc->pipe; in valleyview_crtc_enable()
2269 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) in valleyview_crtc_enable()
2281 crtc->active = true; in valleyview_crtc_enable()
2315 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_crtc_enable()
2316 enum pipe pipe = crtc->pipe; in i9xx_crtc_enable()
2318 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) in i9xx_crtc_enable()
2325 crtc->active = true; in i9xx_crtc_enable()
2357 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in i9xx_pfit_disable()
2358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_pfit_disable()
2360 if (!old_crtc_state->gmch_pfit.control) in i9xx_pfit_disable()
2363 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); in i9xx_pfit_disable()
2365 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", in i9xx_pfit_disable()
2375 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_crtc_disable()
2376 enum pipe pipe = crtc->pipe; in i9xx_crtc_disable()
2409 if (!dev_priv->display.funcs.wm->initial_watermarks) in i9xx_crtc_disable()
2434 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", in intel_display_suspend()
2437 dev_priv->modeset_restore_state = state; in intel_display_suspend()
2451 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_supports_double_wide()
2455 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); in intel_crtc_supports_double_wide()
2460 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; in ilk_pipe_pixel_rate()
2464 * We only use IF-ID interlacing. If we ever use in ilk_pipe_pixel_rate()
2465 * PF-ID we'll need to adjust the pixel_rate here. in ilk_pipe_pixel_rate()
2468 if (!crtc_state->pch_pfit.enabled) in ilk_pipe_pixel_rate()
2472 drm_rect_width(&crtc_state->pipe_src) << 16, in ilk_pipe_pixel_rate()
2473 drm_rect_height(&crtc_state->pipe_src) << 16); in ilk_pipe_pixel_rate()
2475 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, in ilk_pipe_pixel_rate()
2482 mode->hdisplay = timings->crtc_hdisplay; in intel_mode_from_crtc_timings()
2483 mode->htotal = timings->crtc_htotal; in intel_mode_from_crtc_timings()
2484 mode->hsync_start = timings->crtc_hsync_start; in intel_mode_from_crtc_timings()
2485 mode->hsync_end = timings->crtc_hsync_end; in intel_mode_from_crtc_timings()
2487 mode->vdisplay = timings->crtc_vdisplay; in intel_mode_from_crtc_timings()
2488 mode->vtotal = timings->crtc_vtotal; in intel_mode_from_crtc_timings()
2489 mode->vsync_start = timings->crtc_vsync_start; in intel_mode_from_crtc_timings()
2490 mode->vsync_end = timings->crtc_vsync_end; in intel_mode_from_crtc_timings()
2492 mode->flags = timings->flags; in intel_mode_from_crtc_timings()
2493 mode->type = DRM_MODE_TYPE_DRIVER; in intel_mode_from_crtc_timings()
2495 mode->clock = timings->crtc_clock; in intel_mode_from_crtc_timings()
2502 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_crtc_compute_pixel_rate()
2506 crtc_state->pixel_rate = in intel_crtc_compute_pixel_rate()
2507 crtc_state->hw.pipe_mode.crtc_clock; in intel_crtc_compute_pixel_rate()
2509 crtc_state->pixel_rate = in intel_crtc_compute_pixel_rate()
2521 mode->crtc_clock /= num_pipes; in intel_bigjoiner_adjust_timings()
2522 mode->crtc_hdisplay /= num_pipes; in intel_bigjoiner_adjust_timings()
2523 mode->crtc_hblank_start /= num_pipes; in intel_bigjoiner_adjust_timings()
2524 mode->crtc_hblank_end /= num_pipes; in intel_bigjoiner_adjust_timings()
2525 mode->crtc_hsync_start /= num_pipes; in intel_bigjoiner_adjust_timings()
2526 mode->crtc_hsync_end /= num_pipes; in intel_bigjoiner_adjust_timings()
2527 mode->crtc_htotal /= num_pipes; in intel_bigjoiner_adjust_timings()
2533 int overlap = crtc_state->splitter.pixel_overlap; in intel_splitter_adjust_timings()
2534 int n = crtc_state->splitter.link_count; in intel_splitter_adjust_timings()
2536 if (!crtc_state->splitter.enable) in intel_splitter_adjust_timings()
2543 * h_full = (h_segment - pixel_overlap) * link_count in intel_splitter_adjust_timings()
2545 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; in intel_splitter_adjust_timings()
2546 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; in intel_splitter_adjust_timings()
2547 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; in intel_splitter_adjust_timings()
2548 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; in intel_splitter_adjust_timings()
2549 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; in intel_splitter_adjust_timings()
2550 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; in intel_splitter_adjust_timings()
2551 mode->crtc_clock *= n; in intel_splitter_adjust_timings()
2556 struct drm_display_mode *mode = &crtc_state->hw.mode; in intel_crtc_readout_derived_state()
2557 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; in intel_crtc_readout_derived_state()
2558 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_crtc_readout_derived_state()
2566 /* Expand MSO per-segment transcoder timings to full */ in intel_crtc_readout_derived_state()
2579 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * in intel_crtc_readout_derived_state()
2581 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); in intel_crtc_readout_derived_state()
2583 /* Derive per-pipe timings in case bigjoiner is used */ in intel_crtc_readout_derived_state()
2593 encoder->get_config(encoder, crtc_state); in intel_encoder_get_config()
2606 width = drm_rect_width(&crtc_state->pipe_src); in intel_bigjoiner_compute_pipe_src()
2607 height = drm_rect_height(&crtc_state->pipe_src); in intel_bigjoiner_compute_pipe_src()
2609 drm_rect_init(&crtc_state->pipe_src, 0, 0, in intel_bigjoiner_compute_pipe_src()
2615 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_compute_pipe_src()
2616 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_crtc_compute_pipe_src()
2622 * - DVO ganged mode in intel_crtc_compute_pipe_src()
2623 * - LVDS dual channel mode in intel_crtc_compute_pipe_src()
2624 * - Double wide pipe in intel_crtc_compute_pipe_src()
2626 if (drm_rect_width(&crtc_state->pipe_src) & 1) { in intel_crtc_compute_pipe_src()
2627 if (crtc_state->double_wide) { in intel_crtc_compute_pipe_src()
2628 drm_dbg_kms(&i915->drm, in intel_crtc_compute_pipe_src()
2630 crtc->base.base.id, crtc->base.name); in intel_crtc_compute_pipe_src()
2631 return -EINVAL; in intel_crtc_compute_pipe_src()
2636 drm_dbg_kms(&i915->drm, in intel_crtc_compute_pipe_src()
2638 crtc->base.base.id, crtc->base.name); in intel_crtc_compute_pipe_src()
2639 return -EINVAL; in intel_crtc_compute_pipe_src()
2648 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_compute_pipe_mode()
2649 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_crtc_compute_pipe_mode()
2650 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_crtc_compute_pipe_mode()
2651 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; in intel_crtc_compute_pipe_mode()
2652 int clock_limit = i915->max_dotclk_freq; in intel_crtc_compute_pipe_mode()
2660 /* Expand MSO per-segment transcoder timings to full */ in intel_crtc_compute_pipe_mode()
2663 /* Derive per-pipe timings in case bigjoiner is used */ in intel_crtc_compute_pipe_mode()
2668 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; in intel_crtc_compute_pipe_mode()
2675 pipe_mode->crtc_clock > clock_limit) { in intel_crtc_compute_pipe_mode()
2676 clock_limit = i915->max_dotclk_freq; in intel_crtc_compute_pipe_mode()
2677 crtc_state->double_wide = true; in intel_crtc_compute_pipe_mode()
2681 if (pipe_mode->crtc_clock > clock_limit) { in intel_crtc_compute_pipe_mode()
2682 drm_dbg_kms(&i915->drm, in intel_crtc_compute_pipe_mode()
2684 crtc->base.base.id, crtc->base.name, in intel_crtc_compute_pipe_mode()
2685 pipe_mode->crtc_clock, clock_limit, in intel_crtc_compute_pipe_mode()
2686 str_yes_no(crtc_state->double_wide)); in intel_crtc_compute_pipe_mode()
2687 return -EINVAL; in intel_crtc_compute_pipe_mode()
2714 if (crtc_state->has_pch_encoder) in intel_crtc_compute_config()
2760 m_n->tu = 64; in intel_link_compute_m_n()
2761 compute_m_n(&m_n->data_m, &m_n->data_n, in intel_link_compute_m_n()
2765 compute_m_n(&m_n->link_m, &m_n->link_n, in intel_link_compute_m_n()
2783 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { in intel_panel_sanitize_ssc()
2784 drm_dbg_kms(&dev_priv->drm, in intel_panel_sanitize_ssc()
2787 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); in intel_panel_sanitize_ssc()
2788 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; in intel_panel_sanitize_ssc()
2797 m_n->tu = 1; in intel_zero_m_n()
2805 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); in intel_set_m_n()
2806 intel_de_write(i915, data_n_reg, m_n->data_n); in intel_set_m_n()
2807 intel_de_write(i915, link_m_reg, m_n->link_m); in intel_set_m_n()
2812 intel_de_write(i915, link_n_reg, m_n->link_n); in intel_set_m_n()
2828 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_cpu_transcoder_set_m1_n1()
2829 enum pipe pipe = crtc->pipe; in intel_cpu_transcoder_set_m1_n1()
2845 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_cpu_transcoder_set_m2_n2()
2857 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_set_transcoder_timings()
2858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_set_transcoder_timings()
2859 enum pipe pipe = crtc->pipe; in intel_set_transcoder_timings()
2860 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_set_transcoder_timings()
2861 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_set_transcoder_timings()
2867 crtc_vtotal = adjusted_mode->crtc_vtotal; in intel_set_transcoder_timings()
2868 crtc_vblank_end = adjusted_mode->crtc_vblank_end; in intel_set_transcoder_timings()
2870 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { in intel_set_transcoder_timings()
2872 crtc_vtotal -= 1; in intel_set_transcoder_timings()
2873 crtc_vblank_end -= 1; in intel_set_transcoder_timings()
2876 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; in intel_set_transcoder_timings()
2878 vsyncshift = adjusted_mode->crtc_hsync_start - in intel_set_transcoder_timings()
2879 adjusted_mode->crtc_htotal / 2; in intel_set_transcoder_timings()
2881 vsyncshift += adjusted_mode->crtc_htotal; in intel_set_transcoder_timings()
2889 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); in intel_set_transcoder_timings()
2891 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); in intel_set_transcoder_timings()
2893 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); in intel_set_transcoder_timings()
2896 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); in intel_set_transcoder_timings()
2898 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); in intel_set_transcoder_timings()
2900 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); in intel_set_transcoder_timings()
2915 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_set_pipe_src_size()
2916 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_set_pipe_src_size()
2917 int width = drm_rect_width(&crtc_state->pipe_src); in intel_set_pipe_src_size()
2918 int height = drm_rect_height(&crtc_state->pipe_src); in intel_set_pipe_src_size()
2919 enum pipe pipe = crtc->pipe; in intel_set_pipe_src_size()
2925 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); in intel_set_pipe_src_size()
2930 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_pipe_is_interlaced()
2931 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_pipe_is_interlaced()
2946 struct drm_device *dev = crtc->base.dev; in intel_get_transcoder_timings()
2948 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_get_transcoder_timings()
2952 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; in intel_get_transcoder_timings()
2953 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_transcoder_timings()
2957 pipe_config->hw.adjusted_mode.crtc_hblank_start = in intel_get_transcoder_timings()
2959 pipe_config->hw.adjusted_mode.crtc_hblank_end = in intel_get_transcoder_timings()
2963 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; in intel_get_transcoder_timings()
2964 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_transcoder_timings()
2967 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; in intel_get_transcoder_timings()
2968 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_transcoder_timings()
2972 pipe_config->hw.adjusted_mode.crtc_vblank_start = in intel_get_transcoder_timings()
2974 pipe_config->hw.adjusted_mode.crtc_vblank_end = in intel_get_transcoder_timings()
2978 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; in intel_get_transcoder_timings()
2979 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_transcoder_timings()
2982 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; in intel_get_transcoder_timings()
2983 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; in intel_get_transcoder_timings()
2984 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; in intel_get_transcoder_timings()
2990 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_bigjoiner_adjust_pipe_src()
2992 enum pipe master_pipe, pipe = crtc->pipe; in intel_bigjoiner_adjust_pipe_src()
2999 width = drm_rect_width(&crtc_state->pipe_src); in intel_bigjoiner_adjust_pipe_src()
3001 drm_rect_translate_to(&crtc_state->pipe_src, in intel_bigjoiner_adjust_pipe_src()
3002 (pipe - master_pipe) * width, 0); in intel_bigjoiner_adjust_pipe_src()
3008 struct drm_device *dev = crtc->base.dev; in intel_get_pipe_src_size()
3012 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); in intel_get_pipe_src_size()
3014 drm_rect_init(&pipe_config->pipe_src, 0, 0, in intel_get_pipe_src_size()
3023 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_set_pipeconf()
3024 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_set_pipeconf()
3028 * - We keep both pipes enabled on 830 in i9xx_set_pipeconf()
3029 * - During modeset the pipe is still disabled and must remain so in i9xx_set_pipeconf()
3030 * - During fastset the pipe is already enabled and must remain so in i9xx_set_pipeconf()
3035 if (crtc_state->double_wide) in i9xx_set_pipeconf()
3042 if (crtc_state->dither && crtc_state->pipe_bpp != 30) in i9xx_set_pipeconf()
3046 switch (crtc_state->pipe_bpp) { in i9xx_set_pipeconf()
3049 MISSING_CASE(crtc_state->pipe_bpp); in i9xx_set_pipeconf()
3063 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { in i9xx_set_pipeconf()
3074 crtc_state->limited_color_range) in i9xx_set_pipeconf()
3077 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); in i9xx_set_pipeconf()
3079 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); in i9xx_set_pipeconf()
3081 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); in i9xx_set_pipeconf()
3082 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); in i9xx_set_pipeconf()
3096 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_get_pfit_config()
3097 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_get_pfit_config()
3109 if (crtc->pipe != PIPE_B) in i9xx_get_pfit_config()
3112 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) in i9xx_get_pfit_config()
3116 crtc_state->gmch_pfit.control = tmp; in i9xx_get_pfit_config()
3117 crtc_state->gmch_pfit.pgm_ratios = in i9xx_get_pfit_config()
3124 struct drm_device *dev = crtc->base.dev; in vlv_crtc_clock_get()
3126 enum pipe pipe = crtc->pipe; in vlv_crtc_clock_get()
3129 int refclk = 100000; in vlv_crtc_clock_get() local
3132 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
3145 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
3151 struct drm_device *dev = crtc->base.dev; in chv_crtc_clock_get()
3153 enum pipe pipe = crtc->pipe; in chv_crtc_clock_get()
3157 int refclk = 100000; in chv_crtc_clock_get() local
3160 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
3179 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
3185 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in bdw_get_pipemisc_output_format()
3188 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); in bdw_get_pipemisc_output_format()
3192 drm_WARN_ON(&dev_priv->drm, in bdw_get_pipemisc_output_format()
3205 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_get_pipe_color_config()
3206 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in i9xx_get_pipe_color_config()
3207 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_get_pipe_color_config()
3208 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_get_pipe_color_config()
3214 crtc_state->gamma_enable = true; in i9xx_get_pipe_color_config()
3218 crtc_state->csc_enable = true; in i9xx_get_pipe_color_config()
3224 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_get_pipe_config()
3230 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); in i9xx_get_pipe_config()
3235 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in i9xx_get_pipe_config()
3236 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in i9xx_get_pipe_config()
3237 pipe_config->shared_dpll = NULL; in i9xx_get_pipe_config()
3241 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); in i9xx_get_pipe_config()
3249 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
3252 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
3255 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
3265 pipe_config->limited_color_range = true; in i9xx_get_pipe_config()
3267 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); in i9xx_get_pipe_config()
3269 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; in i9xx_get_pipe_config()
3272 pipe_config->cgm_mode = intel_de_read(dev_priv, in i9xx_get_pipe_config()
3273 CGM_PIPE_MODE(crtc->pipe)); in i9xx_get_pipe_config()
3279 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; in i9xx_get_pipe_config()
3288 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) in i9xx_get_pipe_config()
3289 tmp = dev_priv->chv_dpll_md[crtc->pipe]; in i9xx_get_pipe_config()
3291 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); in i9xx_get_pipe_config()
3292 pipe_config->pixel_multiplier = in i9xx_get_pipe_config()
3295 pipe_config->dpll_hw_state.dpll_md = tmp; in i9xx_get_pipe_config()
3298 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); in i9xx_get_pipe_config()
3299 pipe_config->pixel_multiplier = in i9xx_get_pipe_config()
3304 * port and will be fixed up in the encoder->get_config in i9xx_get_pipe_config()
3306 pipe_config->pixel_multiplier = 1; in i9xx_get_pipe_config()
3308 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, in i9xx_get_pipe_config()
3309 DPLL(crtc->pipe)); in i9xx_get_pipe_config()
3311 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, in i9xx_get_pipe_config()
3312 FP0(crtc->pipe)); in i9xx_get_pipe_config()
3313 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, in i9xx_get_pipe_config()
3314 FP1(crtc->pipe)); in i9xx_get_pipe_config()
3316 /* Mask out read-only status bits. */ in i9xx_get_pipe_config()
3317 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
3334 pipe_config->hw.adjusted_mode.crtc_clock = in i9xx_get_pipe_config()
3335 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
3347 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_set_pipeconf()
3348 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_set_pipeconf()
3349 enum pipe pipe = crtc->pipe; in ilk_set_pipeconf()
3353 * - During modeset the pipe is still disabled and must remain so in ilk_set_pipeconf()
3354 * - During fastset the pipe is already enabled and must remain so in ilk_set_pipeconf()
3359 switch (crtc_state->pipe_bpp) { in ilk_set_pipeconf()
3362 MISSING_CASE(crtc_state->pipe_bpp); in ilk_set_pipeconf()
3378 if (crtc_state->dither) in ilk_set_pipeconf()
3381 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in ilk_set_pipeconf()
3390 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && in ilk_set_pipeconf()
3391 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); in ilk_set_pipeconf()
3393 if (crtc_state->limited_color_range && in ilk_set_pipeconf()
3397 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) in ilk_set_pipeconf()
3400 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); in ilk_set_pipeconf()
3402 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); in ilk_set_pipeconf()
3403 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); in ilk_set_pipeconf()
3411 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_set_transconf()
3412 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_set_transconf()
3413 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_set_transconf()
3417 * - During modeset the pipe is still disabled and must remain so in hsw_set_transconf()
3418 * - During fastset the pipe is already enabled and must remain so in hsw_set_transconf()
3423 if (IS_HASWELL(dev_priv) && crtc_state->dither) in hsw_set_transconf()
3426 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in hsw_set_transconf()
3432 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) in hsw_set_transconf()
3441 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in bdw_set_pipemisc()
3442 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in bdw_set_pipemisc()
3445 switch (crtc_state->pipe_bpp) { in bdw_set_pipemisc()
3461 MISSING_CASE(crtc_state->pipe_bpp); in bdw_set_pipemisc()
3465 if (crtc_state->dither) in bdw_set_pipemisc()
3468 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || in bdw_set_pipemisc()
3469 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) in bdw_set_pipemisc()
3472 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in bdw_set_pipemisc()
3482 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); in bdw_set_pipemisc()
3487 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in bdw_get_pipemisc_bpp()
3490 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); in bdw_get_pipemisc_bpp()
3535 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; in intel_get_m_n()
3536 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; in intel_get_m_n()
3537 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; in intel_get_m_n()
3538 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; in intel_get_m_n()
3539 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; in intel_get_m_n()
3546 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_cpu_transcoder_get_m1_n1()
3547 enum pipe pipe = crtc->pipe; in intel_cpu_transcoder_get_m1_n1()
3563 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_cpu_transcoder_get_m2_n2()
3576 drm_rect_init(&crtc_state->pch_pfit.dst, in ilk_get_pfit_pos_size()
3583 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_get_pfit_config()
3584 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in skl_get_pfit_config()
3585 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; in skl_get_pfit_config()
3586 int id = -1; in skl_get_pfit_config()
3590 for (i = 0; i < crtc->num_scalers; i++) { in skl_get_pfit_config()
3593 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); in skl_get_pfit_config()
3598 crtc_state->pch_pfit.enabled = true; in skl_get_pfit_config()
3600 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); in skl_get_pfit_config()
3601 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); in skl_get_pfit_config()
3605 scaler_state->scalers[i].in_use = true; in skl_get_pfit_config()
3609 scaler_state->scaler_id = id; in skl_get_pfit_config()
3611 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); in skl_get_pfit_config()
3613 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); in skl_get_pfit_config()
3618 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_get_pfit_config()
3619 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_get_pfit_config()
3622 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); in ilk_get_pfit_config()
3626 crtc_state->pch_pfit.enabled = true; in ilk_get_pfit_config()
3628 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); in ilk_get_pfit_config()
3629 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); in ilk_get_pfit_config()
3638 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && in ilk_get_pfit_config()
3639 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); in ilk_get_pfit_config()
3645 struct drm_device *dev = crtc->base.dev; in ilk_get_pipe_config()
3652 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); in ilk_get_pipe_config()
3657 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in ilk_get_pipe_config()
3658 pipe_config->shared_dpll = NULL; in ilk_get_pipe_config()
3661 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); in ilk_get_pipe_config()
3667 pipe_config->pipe_bpp = 18; in ilk_get_pipe_config()
3670 pipe_config->pipe_bpp = 24; in ilk_get_pipe_config()
3673 pipe_config->pipe_bpp = 30; in ilk_get_pipe_config()
3676 pipe_config->pipe_bpp = 36; in ilk_get_pipe_config()
3683 pipe_config->limited_color_range = true; in ilk_get_pipe_config()
3688 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; in ilk_get_pipe_config()
3691 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in ilk_get_pipe_config()
3695 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); in ilk_get_pipe_config()
3697 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; in ilk_get_pipe_config()
3699 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); in ilk_get_pipe_config()
3701 pipe_config->csc_mode = intel_de_read(dev_priv, in ilk_get_pipe_config()
3702 PIPE_CSC_MODE(crtc->pipe)); in ilk_get_pipe_config()
3707 pipe_config->pixel_multiplier = 1; in ilk_get_pipe_config()
3735 return pipes & RUNTIME_INFO(i915)->pipe_mask; in bigjoiner_pipes()
3761 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, in enabled_bigjoiner_pipes()
3764 enum pipe pipe = crtc->pipe; in enabled_bigjoiner_pipes()
3795 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, in enabled_bigjoiner_pipes()
3809 return fls(master_pipes) - 1; in get_bigjoiner_master_pipe()
3826 next_master_pipe = ffs(master_pipes) - 1; in get_bigjoiner_slave_pipes()
3828 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); in get_bigjoiner_slave_pipes()
3843 struct drm_device *dev = crtc->base.dev; in hsw_enabled_transcoders()
3889 if (trans_pipe == crtc->pipe) in hsw_enabled_transcoders()
3894 cpu_transcoder = (enum transcoder) crtc->pipe; in hsw_enabled_transcoders()
3898 /* bigjoiner slave -> consider the master pipe's transcoder as well */ in hsw_enabled_transcoders()
3900 if (slave_pipes & BIT(crtc->pipe)) { in hsw_enabled_transcoders()
3902 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); in hsw_enabled_transcoders()
3932 drm_WARN_ON(&i915->drm, in assert_enabled_transcoders()
3938 drm_WARN_ON(&i915->drm, in assert_enabled_transcoders()
3947 struct drm_device *dev = crtc->base.dev; in hsw_get_transcoder_state()
3963 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; in hsw_get_transcoder_state()
3966 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) in hsw_get_transcoder_state()
3969 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { in hsw_get_transcoder_state()
3970 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); in hsw_get_transcoder_state()
3973 pipe_config->pch_pfit.force_thru = true; in hsw_get_transcoder_state()
3976 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); in hsw_get_transcoder_state()
3985 struct drm_device *dev = crtc->base.dev; in bxt_get_dsi_transcoder_state()
4017 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) in bxt_get_dsi_transcoder_state()
4020 pipe_config->cpu_transcoder = cpu_transcoder; in bxt_get_dsi_transcoder_state()
4024 return transcoder_is_dsi(pipe_config->cpu_transcoder); in bxt_get_dsi_transcoder_state()
4029 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_bigjoiner_get_config()
4030 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_bigjoiner_get_config()
4032 enum pipe pipe = crtc->pipe; in intel_bigjoiner_get_config()
4039 crtc_state->bigjoiner_pipes = in intel_bigjoiner_get_config()
4047 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_get_pipe_config()
4053 POWER_DOMAIN_PIPE(crtc->pipe))) in hsw_get_pipe_config()
4056 pipe_config->shared_dpll = NULL; in hsw_get_pipe_config()
4062 drm_WARN_ON(&dev_priv->drm, active); in hsw_get_pipe_config()
4072 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || in hsw_get_pipe_config()
4076 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) in hsw_get_pipe_config()
4083 PIPECONF(pipe_config->cpu_transcoder)); in hsw_get_pipe_config()
4086 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; in hsw_get_pipe_config()
4088 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in hsw_get_pipe_config()
4090 pipe_config->output_format = in hsw_get_pipe_config()
4094 pipe_config->gamma_mode = intel_de_read(dev_priv, in hsw_get_pipe_config()
4095 GAMMA_MODE(crtc->pipe)); in hsw_get_pipe_config()
4097 pipe_config->csc_mode = intel_de_read(dev_priv, in hsw_get_pipe_config()
4098 PIPE_CSC_MODE(crtc->pipe)); in hsw_get_pipe_config()
4101 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); in hsw_get_pipe_config()
4104 pipe_config->gamma_enable = true; in hsw_get_pipe_config()
4107 pipe_config->csc_enable = true; in hsw_get_pipe_config()
4114 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); in hsw_get_pipe_config()
4115 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); in hsw_get_pipe_config()
4117 pipe_config->ips_linetime = in hsw_get_pipe_config()
4121 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { in hsw_get_pipe_config()
4130 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && in hsw_get_pipe_config()
4131 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { in hsw_get_pipe_config()
4132 pipe_config->pixel_multiplier = in hsw_get_pipe_config()
4134 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; in hsw_get_pipe_config()
4136 pipe_config->pixel_multiplier = 1; in hsw_get_pipe_config()
4139 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { in hsw_get_pipe_config()
4141 MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : in hsw_get_pipe_config()
4142 CHICKEN_TRANS(pipe_config->cpu_transcoder)); in hsw_get_pipe_config()
4144 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; in hsw_get_pipe_config()
4147 pipe_config->framestart_delay = 1; in hsw_get_pipe_config()
4158 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_get_pipe_config()
4159 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_crtc_get_pipe_config()
4161 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) in intel_crtc_get_pipe_config()
4164 crtc_state->hw.active = true; in intel_crtc_get_pipe_config()
4189 if (plane_state->crtc != crtc) in intel_modeset_disable_planes()
4210 struct drm_device *dev = encoder->base.dev; in intel_get_load_detect_pipe()
4212 struct drm_mode_config *config = &dev->mode_config; in intel_get_load_detect_pipe()
4218 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", in intel_get_load_detect_pipe()
4219 connector->base.id, connector->name, in intel_get_load_detect_pipe()
4220 encoder->base.base.id, encoder->base.name); in intel_get_load_detect_pipe()
4222 old->restore_state = NULL; in intel_get_load_detect_pipe()
4224 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); in intel_get_load_detect_pipe()
4229 * - if the connector already has an assigned crtc, use it (but make in intel_get_load_detect_pipe()
4232 * - try to find the first unused crtc that can drive this connector, in intel_get_load_detect_pipe()
4237 if (connector->state->crtc) { in intel_get_load_detect_pipe()
4238 crtc = to_intel_crtc(connector->state->crtc); in intel_get_load_detect_pipe()
4240 ret = drm_modeset_lock(&crtc->base.mutex, ctx); in intel_get_load_detect_pipe()
4250 if (!(encoder->base.possible_crtcs & in intel_get_load_detect_pipe()
4251 drm_crtc_mask(&possible_crtc->base))) in intel_get_load_detect_pipe()
4254 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); in intel_get_load_detect_pipe()
4258 if (possible_crtc->base.state->enable) { in intel_get_load_detect_pipe()
4259 drm_modeset_unlock(&possible_crtc->base.mutex); in intel_get_load_detect_pipe()
4271 drm_dbg_kms(&dev_priv->drm, in intel_get_load_detect_pipe()
4272 "no pipe available for load-detect\n"); in intel_get_load_detect_pipe()
4273 ret = -ENODEV; in intel_get_load_detect_pipe()
4281 ret = -ENOMEM; in intel_get_load_detect_pipe()
4285 state->acquire_ctx = ctx; in intel_get_load_detect_pipe()
4286 restore_state->acquire_ctx = ctx; in intel_get_load_detect_pipe()
4294 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); in intel_get_load_detect_pipe()
4304 crtc_state->uapi.active = true; in intel_get_load_detect_pipe()
4306 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, in intel_get_load_detect_pipe()
4311 ret = intel_modeset_disable_planes(state, &crtc->base); in intel_get_load_detect_pipe()
4317 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); in intel_get_load_detect_pipe()
4319 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); in intel_get_load_detect_pipe()
4321 drm_dbg_kms(&dev_priv->drm, in intel_get_load_detect_pipe()
4329 drm_dbg_kms(&dev_priv->drm, in intel_get_load_detect_pipe()
4330 "failed to set mode on load-detect pipe\n"); in intel_get_load_detect_pipe()
4334 old->restore_state = restore_state; in intel_get_load_detect_pipe()
4352 if (ret == -EDEADLK) in intel_get_load_detect_pipe()
4364 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); in intel_release_load_detect_pipe()
4365 struct drm_encoder *encoder = &intel_encoder->base; in intel_release_load_detect_pipe()
4366 struct drm_atomic_state *state = old->restore_state; in intel_release_load_detect_pipe()
4369 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", in intel_release_load_detect_pipe()
4370 connector->base.id, connector->name, in intel_release_load_detect_pipe()
4371 encoder->base.id, encoder->name); in intel_release_load_detect_pipe()
4378 drm_dbg_kms(&i915->drm, in intel_release_load_detect_pipe()
4387 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk()
4390 return dev_priv->display.vbt.lvds_ssc_freq; in i9xx_pll_refclk()
4403 struct drm_device *dev = crtc->base.dev; in i9xx_crtc_clock_get()
4405 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get()
4409 int refclk = i9xx_pll_refclk(dev, pipe_config); in i9xx_crtc_clock_get() local
4412 fp = pipe_config->dpll_hw_state.fp0; in i9xx_crtc_clock_get()
4414 fp = pipe_config->dpll_hw_state.fp1; in i9xx_crtc_clock_get()
4418 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; in i9xx_crtc_clock_get()
4443 drm_dbg_kms(&dev_priv->drm, in i9xx_crtc_clock_get()
4450 port_clock = pnv_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
4452 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
4458 lvds_pipe == crtc->pipe) { in i9xx_crtc_clock_get()
4481 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
4489 pipe_config->port_clock = port_clock; in i9xx_crtc_clock_get()
4505 if (!m_n->link_n) in intel_dotclock_calculate()
4508 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), in intel_dotclock_calculate()
4509 m_n->link_n); in intel_dotclock_calculate()
4517 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in intel_crtc_dotclock()
4518 &pipe_config->dp_m_n); in intel_crtc_dotclock()
4519 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) in intel_crtc_dotclock()
4520 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, in intel_crtc_dotclock()
4521 pipe_config->pipe_bpp); in intel_crtc_dotclock()
4523 dotclock = pipe_config->port_clock; in intel_crtc_dotclock()
4525 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && in intel_crtc_dotclock()
4529 if (pipe_config->pixel_multiplier) in intel_crtc_dotclock()
4530 dotclock /= pipe_config->pixel_multiplier; in intel_crtc_dotclock()
4539 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_encoder_current_mode()
4545 if (!encoder->get_hw_state(encoder, &pipe)) in intel_encoder_current_mode()
4568 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); in intel_encoder_current_mode()
4579 return a == b || (a->cloneable & (1 << b->type) && in encoders_cloneable()
4580 b->cloneable & (1 << a->type)); in encoders_cloneable()
4592 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { in check_single_encoder_cloning()
4593 if (connector_state->crtc != &crtc->base) in check_single_encoder_cloning()
4597 to_intel_encoder(connector_state->best_encoder); in check_single_encoder_cloning()
4612 linked = plane_state->planar_linked_plane; in icl_add_linked_planes()
4621 drm_WARN_ON(state->base.dev, in icl_add_linked_planes()
4622 linked_plane_state->planar_linked_plane != plane); in icl_add_linked_planes()
4623 drm_WARN_ON(state->base.dev, in icl_add_linked_planes()
4624 linked_plane_state->planar_slave == plane_state->planar_slave); in icl_add_linked_planes()
4632 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in icl_check_nv12_planes()
4633 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in icl_check_nv12_planes()
4634 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); in icl_check_nv12_planes()
4644 * in the crtc_state->active_planes mask. in icl_check_nv12_planes()
4647 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) in icl_check_nv12_planes()
4650 plane_state->planar_linked_plane = NULL; in icl_check_nv12_planes()
4651 if (plane_state->planar_slave && !plane_state->uapi.visible) { in icl_check_nv12_planes()
4652 crtc_state->enabled_planes &= ~BIT(plane->id); in icl_check_nv12_planes()
4653 crtc_state->active_planes &= ~BIT(plane->id); in icl_check_nv12_planes()
4654 crtc_state->update_planes |= BIT(plane->id); in icl_check_nv12_planes()
4655 crtc_state->data_rate[plane->id] = 0; in icl_check_nv12_planes()
4656 crtc_state->rel_data_rate[plane->id] = 0; in icl_check_nv12_planes()
4659 plane_state->planar_slave = false; in icl_check_nv12_planes()
4662 if (!crtc_state->nv12_planes) in icl_check_nv12_planes()
4668 if (plane->pipe != crtc->pipe || in icl_check_nv12_planes()
4669 !(crtc_state->nv12_planes & BIT(plane->id))) in icl_check_nv12_planes()
4672 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { in icl_check_nv12_planes()
4673 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) in icl_check_nv12_planes()
4676 if (crtc_state->active_planes & BIT(linked->id)) in icl_check_nv12_planes()
4687 drm_dbg_kms(&dev_priv->drm, in icl_check_nv12_planes()
4689 hweight8(crtc_state->nv12_planes)); in icl_check_nv12_planes()
4691 return -EINVAL; in icl_check_nv12_planes()
4694 plane_state->planar_linked_plane = linked; in icl_check_nv12_planes()
4696 linked_state->planar_slave = true; in icl_check_nv12_planes()
4697 linked_state->planar_linked_plane = plane; in icl_check_nv12_planes()
4698 crtc_state->enabled_planes |= BIT(linked->id); in icl_check_nv12_planes()
4699 crtc_state->active_planes |= BIT(linked->id); in icl_check_nv12_planes()
4700 crtc_state->update_planes |= BIT(linked->id); in icl_check_nv12_planes()
4701 crtc_state->data_rate[linked->id] = in icl_check_nv12_planes()
4702 crtc_state->data_rate_y[plane->id]; in icl_check_nv12_planes()
4703 crtc_state->rel_data_rate[linked->id] = in icl_check_nv12_planes()
4704 crtc_state->rel_data_rate_y[plane->id]; in icl_check_nv12_planes()
4705 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", in icl_check_nv12_planes()
4706 linked->base.name, plane->base.name); in icl_check_nv12_planes()
4709 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; in icl_check_nv12_planes()
4710 linked_state->color_ctl = plane_state->color_ctl; in icl_check_nv12_planes()
4711 linked_state->view = plane_state->view; in icl_check_nv12_planes()
4712 linked_state->decrypt = plane_state->decrypt; in icl_check_nv12_planes()
4715 linked_state->uapi.src = plane_state->uapi.src; in icl_check_nv12_planes()
4716 linked_state->uapi.dst = plane_state->uapi.dst; in icl_check_nv12_planes()
4718 if (icl_is_hdr_plane(dev_priv, plane->id)) { in icl_check_nv12_planes()
4719 if (linked->id == PLANE_SPRITE5) in icl_check_nv12_planes()
4720 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; in icl_check_nv12_planes()
4721 else if (linked->id == PLANE_SPRITE4) in icl_check_nv12_planes()
4722 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; in icl_check_nv12_planes()
4723 else if (linked->id == PLANE_SPRITE3) in icl_check_nv12_planes()
4724 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; in icl_check_nv12_planes()
4725 else if (linked->id == PLANE_SPRITE2) in icl_check_nv12_planes()
4726 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; in icl_check_nv12_planes()
4728 MISSING_CASE(linked->id); in icl_check_nv12_planes()
4737 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); in c8_planes_changed()
4739 to_intel_atomic_state(new_crtc_state->uapi.state); in c8_planes_changed()
4743 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; in c8_planes_changed()
4749 &crtc_state->hw.pipe_mode; in hsw_linetime_wm()
4752 if (!crtc_state->hw.enable) in hsw_linetime_wm()
4755 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, in hsw_linetime_wm()
4756 pipe_mode->crtc_clock); in hsw_linetime_wm()
4765 &crtc_state->hw.pipe_mode; in hsw_ips_linetime_wm()
4768 if (!crtc_state->hw.enable) in hsw_ips_linetime_wm()
4771 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, in hsw_ips_linetime_wm()
4772 cdclk_state->logical.cdclk); in hsw_ips_linetime_wm()
4779 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_linetime_wm()
4780 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in skl_linetime_wm()
4782 &crtc_state->hw.pipe_mode; in skl_linetime_wm()
4785 if (!crtc_state->hw.enable) in skl_linetime_wm()
4788 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, in skl_linetime_wm()
4789 crtc_state->pixel_rate); in skl_linetime_wm()
4802 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_compute_linetime_wm()
4808 crtc_state->linetime = skl_linetime_wm(crtc_state); in hsw_compute_linetime_wm()
4810 crtc_state->linetime = hsw_linetime_wm(crtc_state); in hsw_compute_linetime_wm()
4819 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, in hsw_compute_linetime_wm()
4828 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_atomic_check()
4835 mode_changed && !crtc_state->hw.active) in intel_crtc_atomic_check()
4836 crtc_state->update_wm_post = true; in intel_crtc_atomic_check()
4849 crtc_state->uapi.color_mgmt_changed = true; in intel_crtc_atomic_check()
4851 if (mode_changed || crtc_state->update_pipe || in intel_crtc_atomic_check()
4852 crtc_state->uapi.color_mgmt_changed) { in intel_crtc_atomic_check()
4860 drm_dbg_kms(&dev_priv->drm, in intel_crtc_atomic_check()
4872 drm_dbg_kms(&dev_priv->drm, in intel_crtc_atomic_check()
4878 if (mode_changed || crtc_state->update_pipe) { in intel_crtc_atomic_check()
4914 struct drm_connector *connector = conn_state->connector; in compute_sink_pipe_bpp()
4915 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in compute_sink_pipe_bpp()
4916 const struct drm_display_info *info = &connector->display_info; in compute_sink_pipe_bpp()
4919 switch (conn_state->max_bpc) { in compute_sink_pipe_bpp()
4933 MISSING_CASE(conn_state->max_bpc); in compute_sink_pipe_bpp()
4934 return -EINVAL; in compute_sink_pipe_bpp()
4937 if (bpp < crtc_state->pipe_bpp) { in compute_sink_pipe_bpp()
4938 drm_dbg_kms(&i915->drm, in compute_sink_pipe_bpp()
4941 connector->base.id, connector->name, in compute_sink_pipe_bpp()
4942 bpp, 3 * info->bpc, in compute_sink_pipe_bpp()
4943 3 * conn_state->max_requested_bpc, in compute_sink_pipe_bpp()
4944 crtc_state->pipe_bpp); in compute_sink_pipe_bpp()
4946 crtc_state->pipe_bpp = bpp; in compute_sink_pipe_bpp()
4956 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in compute_baseline_pipe_bpp()
4971 crtc_state->pipe_bpp = bpp; in compute_baseline_pipe_bpp()
4974 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { in compute_baseline_pipe_bpp()
4977 if (connector_state->crtc != &crtc->base) in compute_baseline_pipe_bpp()
4990 struct drm_device *dev = state->base.dev; in check_digital_port_conflicts()
4998 * We're going to peek into connector->state, in check_digital_port_conflicts()
5001 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); in check_digital_port_conflicts()
5014 drm_atomic_get_new_connector_state(&state->base, in check_digital_port_conflicts()
5017 connector_state = connector->state; in check_digital_port_conflicts()
5019 if (!connector_state->best_encoder) in check_digital_port_conflicts()
5022 encoder = to_intel_encoder(connector_state->best_encoder); in check_digital_port_conflicts()
5024 drm_WARN_ON(dev, !connector_state->crtc); in check_digital_port_conflicts()
5026 switch (encoder->type) { in check_digital_port_conflicts()
5035 if (used_ports & BIT(encoder->port)) in check_digital_port_conflicts()
5038 used_ports |= BIT(encoder->port); in check_digital_port_conflicts()
5042 1 << encoder->port; in check_digital_port_conflicts()
5066 drm_property_replace_blob(&crtc_state->hw.degamma_lut, in intel_crtc_copy_uapi_to_hw_state_nomodeset()
5067 crtc_state->uapi.degamma_lut); in intel_crtc_copy_uapi_to_hw_state_nomodeset()
5068 drm_property_replace_blob(&crtc_state->hw.gamma_lut, in intel_crtc_copy_uapi_to_hw_state_nomodeset()
5069 crtc_state->uapi.gamma_lut); in intel_crtc_copy_uapi_to_hw_state_nomodeset()
5070 drm_property_replace_blob(&crtc_state->hw.ctm, in intel_crtc_copy_uapi_to_hw_state_nomodeset()
5071 crtc_state->uapi.ctm); in intel_crtc_copy_uapi_to_hw_state_nomodeset()
5083 crtc_state->hw.enable = crtc_state->uapi.enable; in intel_crtc_copy_uapi_to_hw_state_modeset()
5084 crtc_state->hw.active = crtc_state->uapi.active; in intel_crtc_copy_uapi_to_hw_state_modeset()
5085 drm_mode_copy(&crtc_state->hw.mode, in intel_crtc_copy_uapi_to_hw_state_modeset()
5086 &crtc_state->uapi.mode); in intel_crtc_copy_uapi_to_hw_state_modeset()
5087 drm_mode_copy(&crtc_state->hw.adjusted_mode, in intel_crtc_copy_uapi_to_hw_state_modeset()
5088 &crtc_state->uapi.adjusted_mode); in intel_crtc_copy_uapi_to_hw_state_modeset()
5089 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; in intel_crtc_copy_uapi_to_hw_state_modeset()
5104 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, in copy_bigjoiner_crtc_state_nomodeset()
5105 master_crtc_state->hw.degamma_lut); in copy_bigjoiner_crtc_state_nomodeset()
5106 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, in copy_bigjoiner_crtc_state_nomodeset()
5107 master_crtc_state->hw.gamma_lut); in copy_bigjoiner_crtc_state_nomodeset()
5108 drm_property_replace_blob(&slave_crtc_state->hw.ctm, in copy_bigjoiner_crtc_state_nomodeset()
5109 master_crtc_state->hw.ctm); in copy_bigjoiner_crtc_state_nomodeset()
5111 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; in copy_bigjoiner_crtc_state_nomodeset()
5125 WARN_ON(master_crtc_state->bigjoiner_pipes != in copy_bigjoiner_crtc_state_modeset()
5126 slave_crtc_state->bigjoiner_pipes); in copy_bigjoiner_crtc_state_modeset()
5130 return -ENOMEM; in copy_bigjoiner_crtc_state_modeset()
5133 saved_state->uapi = slave_crtc_state->uapi; in copy_bigjoiner_crtc_state_modeset()
5134 saved_state->scaler_state = slave_crtc_state->scaler_state; in copy_bigjoiner_crtc_state_modeset()
5135 saved_state->shared_dpll = slave_crtc_state->shared_dpll; in copy_bigjoiner_crtc_state_modeset()
5136 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; in copy_bigjoiner_crtc_state_modeset()
5137 saved_state->crc_enabled = slave_crtc_state->crc_enabled; in copy_bigjoiner_crtc_state_modeset()
5143 /* Re-init hw state */ in copy_bigjoiner_crtc_state_modeset()
5144 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); in copy_bigjoiner_crtc_state_modeset()
5145 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; in copy_bigjoiner_crtc_state_modeset()
5146 slave_crtc_state->hw.active = master_crtc_state->hw.active; in copy_bigjoiner_crtc_state_modeset()
5147 drm_mode_copy(&slave_crtc_state->hw.mode, in copy_bigjoiner_crtc_state_modeset()
5148 &master_crtc_state->hw.mode); in copy_bigjoiner_crtc_state_modeset()
5149 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, in copy_bigjoiner_crtc_state_modeset()
5150 &master_crtc_state->hw.pipe_mode); in copy_bigjoiner_crtc_state_modeset()
5151 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, in copy_bigjoiner_crtc_state_modeset()
5152 &master_crtc_state->hw.adjusted_mode); in copy_bigjoiner_crtc_state_modeset()
5153 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; in copy_bigjoiner_crtc_state_modeset()
5157 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; in copy_bigjoiner_crtc_state_modeset()
5158 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; in copy_bigjoiner_crtc_state_modeset()
5159 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; in copy_bigjoiner_crtc_state_modeset()
5161 WARN_ON(master_crtc_state->bigjoiner_pipes != in copy_bigjoiner_crtc_state_modeset()
5162 slave_crtc_state->bigjoiner_pipes); in copy_bigjoiner_crtc_state_modeset()
5173 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_prepare_cleared_state()
5178 return -ENOMEM; in intel_crtc_prepare_cleared_state()
5180 /* free the old crtc_state->hw members */ in intel_crtc_prepare_cleared_state()
5188 saved_state->uapi = crtc_state->uapi; in intel_crtc_prepare_cleared_state()
5189 saved_state->scaler_state = crtc_state->scaler_state; in intel_crtc_prepare_cleared_state()
5190 saved_state->shared_dpll = crtc_state->shared_dpll; in intel_crtc_prepare_cleared_state()
5191 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; in intel_crtc_prepare_cleared_state()
5192 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, in intel_crtc_prepare_cleared_state()
5193 sizeof(saved_state->icl_port_dplls)); in intel_crtc_prepare_cleared_state()
5194 saved_state->crc_enabled = crtc_state->crc_enabled; in intel_crtc_prepare_cleared_state()
5197 saved_state->wm = crtc_state->wm; in intel_crtc_prepare_cleared_state()
5211 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_modeset_pipe_config()
5220 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; in intel_modeset_pipe_config()
5222 crtc_state->framestart_delay = 1; in intel_modeset_pipe_config()
5229 if (!(crtc_state->hw.adjusted_mode.flags & in intel_modeset_pipe_config()
5231 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; in intel_modeset_pipe_config()
5233 if (!(crtc_state->hw.adjusted_mode.flags & in intel_modeset_pipe_config()
5235 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; in intel_modeset_pipe_config()
5241 base_bpp = crtc_state->pipe_bpp; in intel_modeset_pipe_config()
5251 drm_mode_get_hv_timing(&crtc_state->hw.mode, in intel_modeset_pipe_config()
5253 drm_rect_init(&crtc_state->pipe_src, 0, 0, in intel_modeset_pipe_config()
5256 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { in intel_modeset_pipe_config()
5258 to_intel_encoder(connector_state->best_encoder); in intel_modeset_pipe_config()
5260 if (connector_state->crtc != &crtc->base) in intel_modeset_pipe_config()
5264 drm_dbg_kms(&i915->drm, in intel_modeset_pipe_config()
5266 encoder->base.base.id, encoder->base.name); in intel_modeset_pipe_config()
5267 return -EINVAL; in intel_modeset_pipe_config()
5274 if (encoder->compute_output_type) in intel_modeset_pipe_config()
5275 crtc_state->output_types |= in intel_modeset_pipe_config()
5276 BIT(encoder->compute_output_type(encoder, crtc_state, in intel_modeset_pipe_config()
5279 crtc_state->output_types |= BIT(encoder->type); in intel_modeset_pipe_config()
5284 crtc_state->port_clock = 0; in intel_modeset_pipe_config()
5285 crtc_state->pixel_multiplier = 1; in intel_modeset_pipe_config()
5288 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, in intel_modeset_pipe_config()
5295 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { in intel_modeset_pipe_config()
5297 to_intel_encoder(connector_state->best_encoder); in intel_modeset_pipe_config()
5299 if (connector_state->crtc != &crtc->base) in intel_modeset_pipe_config()
5302 ret = encoder->compute_config(encoder, crtc_state, in intel_modeset_pipe_config()
5304 if (ret == -EDEADLK) in intel_modeset_pipe_config()
5307 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", in intel_modeset_pipe_config()
5308 encoder->base.base.id, encoder->base.name, ret); in intel_modeset_pipe_config()
5315 if (!crtc_state->port_clock) in intel_modeset_pipe_config()
5316 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock in intel_modeset_pipe_config()
5317 * crtc_state->pixel_multiplier; in intel_modeset_pipe_config()
5320 if (ret == -EDEADLK) in intel_modeset_pipe_config()
5322 if (ret == -EAGAIN) { in intel_modeset_pipe_config()
5323 if (drm_WARN(&i915->drm, !retry, in intel_modeset_pipe_config()
5325 crtc->base.base.id, crtc->base.name)) in intel_modeset_pipe_config()
5326 return -EINVAL; in intel_modeset_pipe_config()
5328 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", in intel_modeset_pipe_config()
5329 crtc->base.base.id, crtc->base.name); in intel_modeset_pipe_config()
5334 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", in intel_modeset_pipe_config()
5335 crtc->base.base.id, crtc->base.name, ret); in intel_modeset_pipe_config()
5339 /* Dithering seems to not pass-through bits correctly when it should, so in intel_modeset_pipe_config()
5343 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && in intel_modeset_pipe_config()
5344 !crtc_state->dither_force_disable; in intel_modeset_pipe_config()
5345 drm_dbg_kms(&i915->drm, in intel_modeset_pipe_config()
5347 crtc->base.base.id, crtc->base.name, in intel_modeset_pipe_config()
5348 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); in intel_modeset_pipe_config()
5365 for_each_new_connector_in_state(&state->base, connector, in intel_modeset_pipe_config_late()
5368 to_intel_encoder(conn_state->best_encoder); in intel_modeset_pipe_config_late()
5371 if (conn_state->crtc != &crtc->base || in intel_modeset_pipe_config_late()
5372 !encoder->compute_config_late) in intel_modeset_pipe_config_late()
5375 ret = encoder->compute_config_late(encoder, crtc_state, in intel_modeset_pipe_config_late()
5394 diff = abs(clock1 - clock2); in intel_fuzzy_clock_check()
5406 return m_n->tu == m2_n2->tu && in intel_compare_link_m_n()
5407 m_n->data_m == m2_n2->data_m && in intel_compare_link_m_n()
5408 m_n->data_n == m2_n2->data_n && in intel_compare_link_m_n()
5409 m_n->link_m == m2_n2->link_m && in intel_compare_link_m_n()
5410 m_n->link_n == m2_n2->link_n; in intel_compare_link_m_n()
5437 drm_dbg_kms(&dev_priv->drm, in pipe_config_infoframe_mismatch()
5439 drm_dbg_kms(&dev_priv->drm, "expected:\n"); in pipe_config_infoframe_mismatch()
5440 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); in pipe_config_infoframe_mismatch()
5441 drm_dbg_kms(&dev_priv->drm, "found:\n"); in pipe_config_infoframe_mismatch()
5442 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); in pipe_config_infoframe_mismatch()
5444 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); in pipe_config_infoframe_mismatch()
5445 drm_err(&dev_priv->drm, "expected:\n"); in pipe_config_infoframe_mismatch()
5446 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); in pipe_config_infoframe_mismatch()
5447 drm_err(&dev_priv->drm, "found:\n"); in pipe_config_infoframe_mismatch()
5448 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); in pipe_config_infoframe_mismatch()
5462 drm_dbg_kms(&dev_priv->drm, in pipe_config_dp_vsc_sdp_mismatch()
5464 drm_dbg_kms(&dev_priv->drm, "expected:\n"); in pipe_config_dp_vsc_sdp_mismatch()
5465 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); in pipe_config_dp_vsc_sdp_mismatch()
5466 drm_dbg_kms(&dev_priv->drm, "found:\n"); in pipe_config_dp_vsc_sdp_mismatch()
5467 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); in pipe_config_dp_vsc_sdp_mismatch()
5469 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); in pipe_config_dp_vsc_sdp_mismatch()
5470 drm_err(&dev_priv->drm, "expected:\n"); in pipe_config_dp_vsc_sdp_mismatch()
5471 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); in pipe_config_dp_vsc_sdp_mismatch()
5472 drm_err(&dev_priv->drm, "found:\n"); in pipe_config_dp_vsc_sdp_mismatch()
5473 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); in pipe_config_dp_vsc_sdp_mismatch()
5481 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in pipe_config_mismatch()
5490 drm_dbg_kms(&i915->drm, in pipe_config_mismatch()
5492 crtc->base.base.id, crtc->base.name, name, &vaf); in pipe_config_mismatch()
5494 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", in pipe_config_mismatch()
5495 crtc->base.base.id, crtc->base.name, name, &vaf); in pipe_config_mismatch()
5502 if (dev_priv->params.fastboot != -1) in fastboot_enabled()
5503 return dev_priv->params.fastboot; in fastboot_enabled()
5522 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); in intel_pipe_config_compare()
5523 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_pipe_config_compare()
5527 current_config->inherited && !pipe_config->inherited; in intel_pipe_config_compare()
5530 drm_dbg_kms(&dev_priv->drm, in intel_pipe_config_compare()
5536 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
5539 current_config->name, \ in intel_pipe_config_compare()
5540 pipe_config->name); \ in intel_pipe_config_compare()
5546 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ in intel_pipe_config_compare()
5549 current_config->name & (mask), \ in intel_pipe_config_compare()
5550 pipe_config->name & (mask)); \ in intel_pipe_config_compare()
5556 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
5559 current_config->name, \ in intel_pipe_config_compare()
5560 pipe_config->name); \ in intel_pipe_config_compare()
5566 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
5569 str_yes_no(current_config->name), \ in intel_pipe_config_compare()
5570 str_yes_no(pipe_config->name)); \ in intel_pipe_config_compare()
5581 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ in intel_pipe_config_compare()
5586 str_yes_no(current_config->name), \ in intel_pipe_config_compare()
5587 str_yes_no(pipe_config->name)); \ in intel_pipe_config_compare()
5593 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
5596 current_config->name, \ in intel_pipe_config_compare()
5597 pipe_config->name); \ in intel_pipe_config_compare()
5603 if (!intel_compare_link_m_n(¤t_config->name, \ in intel_pipe_config_compare()
5604 &pipe_config->name)) { \ in intel_pipe_config_compare()
5608 current_config->name.tu, \ in intel_pipe_config_compare()
5609 current_config->name.data_m, \ in intel_pipe_config_compare()
5610 current_config->name.data_n, \ in intel_pipe_config_compare()
5611 current_config->name.link_m, \ in intel_pipe_config_compare()
5612 current_config->name.link_n, \ in intel_pipe_config_compare()
5613 pipe_config->name.tu, \ in intel_pipe_config_compare()
5614 pipe_config->name.data_m, \ in intel_pipe_config_compare()
5615 pipe_config->name.data_n, \ in intel_pipe_config_compare()
5616 pipe_config->name.link_m, \ in intel_pipe_config_compare()
5617 pipe_config->name.link_n); \ in intel_pipe_config_compare()
5650 if (!intel_compare_link_m_n(¤t_config->name, \ in intel_pipe_config_compare()
5651 &pipe_config->name) && \ in intel_pipe_config_compare()
5652 !intel_compare_link_m_n(¤t_config->alt_name, \ in intel_pipe_config_compare()
5653 &pipe_config->name)) { \ in intel_pipe_config_compare()
5658 current_config->name.tu, \ in intel_pipe_config_compare()
5659 current_config->name.data_m, \ in intel_pipe_config_compare()
5660 current_config->name.data_n, \ in intel_pipe_config_compare()
5661 current_config->name.link_m, \ in intel_pipe_config_compare()
5662 current_config->name.link_n, \ in intel_pipe_config_compare()
5663 current_config->alt_name.tu, \ in intel_pipe_config_compare()
5664 current_config->alt_name.data_m, \ in intel_pipe_config_compare()
5665 current_config->alt_name.data_n, \ in intel_pipe_config_compare()
5666 current_config->alt_name.link_m, \ in intel_pipe_config_compare()
5667 current_config->alt_name.link_n, \ in intel_pipe_config_compare()
5668 pipe_config->name.tu, \ in intel_pipe_config_compare()
5669 pipe_config->name.data_m, \ in intel_pipe_config_compare()
5670 pipe_config->name.data_n, \ in intel_pipe_config_compare()
5671 pipe_config->name.link_m, \ in intel_pipe_config_compare()
5672 pipe_config->name.link_n); \ in intel_pipe_config_compare()
5678 if ((current_config->name ^ pipe_config->name) & (mask)) { \ in intel_pipe_config_compare()
5682 current_config->name & (mask), \ in intel_pipe_config_compare()
5683 pipe_config->name & (mask)); \ in intel_pipe_config_compare()
5689 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ in intel_pipe_config_compare()
5690 &pipe_config->infoframes.name)) { \ in intel_pipe_config_compare()
5692 ¤t_config->infoframes.name, \ in intel_pipe_config_compare()
5693 &pipe_config->infoframes.name); \ in intel_pipe_config_compare()
5699 if (!current_config->has_psr && !pipe_config->has_psr && \ in intel_pipe_config_compare()
5700 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ in intel_pipe_config_compare()
5701 &pipe_config->infoframes.name)) { \ in intel_pipe_config_compare()
5703 ¤t_config->infoframes.name, \ in intel_pipe_config_compare()
5704 &pipe_config->infoframes.name); \ in intel_pipe_config_compare()
5710 if (current_config->name1 != pipe_config->name1) { \ in intel_pipe_config_compare()
5713 current_config->name1, \ in intel_pipe_config_compare()
5714 pipe_config->name1); \ in intel_pipe_config_compare()
5717 if (!intel_color_lut_equal(current_config->name2, \ in intel_pipe_config_compare()
5718 pipe_config->name2, pipe_config->name1, \ in intel_pipe_config_compare()
5728 ((current_config->quirks | pipe_config->quirks) & (quirk)) in intel_pipe_config_compare()
5744 if (!fastset || !pipe_config->seamless_m_n) in intel_pipe_config_compare()
5824 if (current_config->active_planes) { in intel_pipe_config_compare()
5834 if (dev_priv->display.dpll.mgr) { in intel_pipe_config_compare()
5850 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); in intel_pipe_config_compare()
5877 if (!fastset || !pipe_config->seamless_m_n) { in intel_pipe_config_compare()
5885 if (current_config->has_psr || pipe_config->has_psr) in intel_pipe_config_compare()
5940 assert_plane(plane, plane_state->planar_slave || in intel_verify_planes()
5941 plane_state->uapi.visible); in intel_verify_planes()
5946 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_all_pipes()
5953 for_each_intel_crtc(&dev_priv->drm, crtc) { in intel_modeset_all_pipes()
5957 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_modeset_all_pipes()
5961 if (!crtc_state->hw.active || in intel_modeset_all_pipes()
5962 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) in intel_modeset_all_pipes()
5965 crtc_state->uapi.mode_changed = true; in intel_modeset_all_pipes()
5967 ret = drm_atomic_add_affected_connectors(&state->base, in intel_modeset_all_pipes()
5968 &crtc->base); in intel_modeset_all_pipes()
5976 crtc_state->update_planes |= crtc_state->active_planes; in intel_modeset_all_pipes()
5984 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_update_active_timings()
5985 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_update_active_timings()
5988 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); in intel_crtc_update_active_timings()
5990 if (crtc_state->vrr.enable) { in intel_crtc_update_active_timings()
5991 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; in intel_crtc_update_active_timings()
5992 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; in intel_crtc_update_active_timings()
5994 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); in intel_crtc_update_active_timings()
5997 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); in intel_crtc_update_active_timings()
5999 crtc->mode_flags = crtc_state->mode_flags; in intel_crtc_update_active_timings()
6004 * On most platforms it starts counting from vtotal-1 on the in intel_crtc_update_active_timings()
6008 * last active line), the scanline counter will read vblank_start-1. in intel_crtc_update_active_timings()
6011 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 in intel_crtc_update_active_timings()
6035 crtc->scanline_offset = vtotal - 1; in intel_crtc_update_active_timings()
6038 crtc->scanline_offset = 2; in intel_crtc_update_active_timings()
6040 crtc->scanline_offset = 1; in intel_crtc_update_active_timings()
6061 if (!crtc_state->hw.active || in hsw_mode_set_planes_workaround()
6070 first_pipe = crtc->pipe; in hsw_mode_set_planes_workaround()
6079 for_each_intel_crtc(state->base.dev, crtc) { in hsw_mode_set_planes_workaround()
6080 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in hsw_mode_set_planes_workaround()
6084 crtc_state->hsw_workaround_pipe = INVALID_PIPE; in hsw_mode_set_planes_workaround()
6086 if (!crtc_state->hw.active || in hsw_mode_set_planes_workaround()
6094 enabled_pipe = crtc->pipe; in hsw_mode_set_planes_workaround()
6098 first_crtc_state->hsw_workaround_pipe = enabled_pipe; in hsw_mode_set_planes_workaround()
6100 other_crtc_state->hsw_workaround_pipe = first_pipe; in hsw_mode_set_planes_workaround()
6113 if (crtc_state->hw.active) in intel_calc_active_pipes()
6114 active_pipes |= BIT(crtc->pipe); in intel_calc_active_pipes()
6116 active_pipes &= ~BIT(crtc->pipe); in intel_calc_active_pipes()
6124 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_checks()
6126 state->modeset = true; in intel_modeset_checks()
6140 new_crtc_state->uapi.mode_changed = false; in intel_crtc_check_fastset()
6141 new_crtc_state->update_pipe = true; in intel_crtc_check_fastset()
6148 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_crtc_add_planes_to_state()
6151 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { in intel_crtc_add_planes_to_state()
6154 if ((plane_ids_mask & BIT(plane->id)) == 0) in intel_crtc_add_planes_to_state()
6174 old_crtc_state->enabled_planes | in intel_atomic_add_affected_planes()
6175 new_crtc_state->enabled_planes); in intel_atomic_add_affected_planes()
6196 if (plane->pipe == crtc->pipe) in intel_crtc_add_bigjoiner_planes()
6197 plane_ids |= BIT(plane->id); in intel_crtc_add_bigjoiner_planes()
6205 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_bigjoiner_add_affected_planes()
6213 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, in intel_bigjoiner_add_affected_planes()
6214 crtc_state->bigjoiner_pipes) { in intel_bigjoiner_add_affected_planes()
6231 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_check_planes()
6249 drm_dbg_atomic(&dev_priv->drm, in intel_atomic_check_planes()
6251 plane->base.base.id, plane->base.name); in intel_atomic_check_planes()
6272 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); in intel_atomic_check_planes()
6273 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); in intel_atomic_check_planes()
6293 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_atomic_check_crtcs()
6298 drm_dbg_atomic(&i915->drm, in intel_atomic_check_crtcs()
6300 crtc->base.base.id, crtc->base.name); in intel_atomic_check_crtcs()
6316 if (new_crtc_state->hw.enable && in intel_cpu_transcoders_need_modeset()
6317 transcoders & BIT(new_crtc_state->cpu_transcoder) && in intel_cpu_transcoders_need_modeset()
6333 if (new_crtc_state->hw.enable && in intel_pipes_need_modeset()
6334 pipes & BIT(crtc->pipe) && in intel_pipes_need_modeset()
6345 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_atomic_check_bigjoiner()
6350 if (!master_crtc_state->bigjoiner_pipes) in intel_atomic_check_bigjoiner()
6354 if (drm_WARN_ON(&i915->drm, in intel_atomic_check_bigjoiner()
6355 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) in intel_atomic_check_bigjoiner()
6356 return -EINVAL; in intel_atomic_check_bigjoiner()
6358 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { in intel_atomic_check_bigjoiner()
6359 drm_dbg_kms(&i915->drm, in intel_atomic_check_bigjoiner()
6362 master_crtc->base.base.id, master_crtc->base.name, in intel_atomic_check_bigjoiner()
6363 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); in intel_atomic_check_bigjoiner()
6364 return -EINVAL; in intel_atomic_check_bigjoiner()
6367 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, in intel_atomic_check_bigjoiner()
6372 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); in intel_atomic_check_bigjoiner()
6377 if (slave_crtc_state->uapi.enable) { in intel_atomic_check_bigjoiner()
6378 drm_dbg_kms(&i915->drm, in intel_atomic_check_bigjoiner()
6381 slave_crtc->base.base.id, slave_crtc->base.name, in intel_atomic_check_bigjoiner()
6382 master_crtc->base.base.id, master_crtc->base.name); in intel_atomic_check_bigjoiner()
6383 return -EINVAL; in intel_atomic_check_bigjoiner()
6393 if (WARN_ON(drm_crtc_index(&master_crtc->base) > in intel_atomic_check_bigjoiner()
6394 drm_crtc_index(&slave_crtc->base))) in intel_atomic_check_bigjoiner()
6395 return -EINVAL; in intel_atomic_check_bigjoiner()
6397 drm_dbg_kms(&i915->drm, in intel_atomic_check_bigjoiner()
6399 slave_crtc->base.base.id, slave_crtc->base.name, in intel_atomic_check_bigjoiner()
6400 master_crtc->base.base.id, master_crtc->base.name); in intel_atomic_check_bigjoiner()
6402 slave_crtc_state->bigjoiner_pipes = in intel_atomic_check_bigjoiner()
6403 master_crtc_state->bigjoiner_pipes; in intel_atomic_check_bigjoiner()
6416 struct drm_i915_private *i915 = to_i915(state->base.dev); in kill_bigjoiner_slave()
6421 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, in kill_bigjoiner_slave()
6426 slave_crtc_state->bigjoiner_pipes = 0; in kill_bigjoiner_slave()
6431 master_crtc_state->bigjoiner_pipes = 0; in kill_bigjoiner_slave()
6455 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_async_flip_check_uapi()
6463 if (!new_crtc_state->uapi.async_flip) in intel_async_flip_check_uapi()
6466 if (!new_crtc_state->uapi.active) { in intel_async_flip_check_uapi()
6467 drm_dbg_kms(&i915->drm, in intel_async_flip_check_uapi()
6469 crtc->base.base.id, crtc->base.name); in intel_async_flip_check_uapi()
6470 return -EINVAL; in intel_async_flip_check_uapi()
6474 drm_dbg_kms(&i915->drm, in intel_async_flip_check_uapi()
6476 crtc->base.base.id, crtc->base.name); in intel_async_flip_check_uapi()
6477 return -EINVAL; in intel_async_flip_check_uapi()
6482 if (plane->pipe != crtc->pipe) in intel_async_flip_check_uapi()
6492 if (!plane->async_flip) { in intel_async_flip_check_uapi()
6493 drm_dbg_kms(&i915->drm, in intel_async_flip_check_uapi()
6495 plane->base.base.id, plane->base.name); in intel_async_flip_check_uapi()
6496 return -EINVAL; in intel_async_flip_check_uapi()
6499 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { in intel_async_flip_check_uapi()
6500 drm_dbg_kms(&i915->drm, in intel_async_flip_check_uapi()
6502 plane->base.base.id, plane->base.name); in intel_async_flip_check_uapi()
6503 return -EINVAL; in intel_async_flip_check_uapi()
6512 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_async_flip_check_hw()
6521 if (!new_crtc_state->uapi.async_flip) in intel_async_flip_check_hw()
6524 if (!new_crtc_state->hw.active) { in intel_async_flip_check_hw()
6525 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6527 crtc->base.base.id, crtc->base.name); in intel_async_flip_check_hw()
6528 return -EINVAL; in intel_async_flip_check_hw()
6532 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6534 crtc->base.base.id, crtc->base.name); in intel_async_flip_check_hw()
6535 return -EINVAL; in intel_async_flip_check_hw()
6538 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { in intel_async_flip_check_hw()
6539 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6541 crtc->base.base.id, crtc->base.name); in intel_async_flip_check_hw()
6542 return -EINVAL; in intel_async_flip_check_hw()
6547 if (plane->pipe != crtc->pipe) in intel_async_flip_check_hw()
6555 if (drm_WARN_ON(&i915->drm, in intel_async_flip_check_hw()
6556 new_crtc_state->do_async_flip && !plane->async_flip)) in intel_async_flip_check_hw()
6557 return -EINVAL; in intel_async_flip_check_hw()
6567 if (!plane->async_flip) in intel_async_flip_check_hw()
6575 switch (new_plane_state->hw.fb->modifier) { in intel_async_flip_check_hw()
6582 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6584 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6585 return -EINVAL; in intel_async_flip_check_hw()
6588 if (new_plane_state->hw.fb->format->num_planes > 1) { in intel_async_flip_check_hw()
6589 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6591 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6592 return -EINVAL; in intel_async_flip_check_hw()
6595 if (old_plane_state->view.color_plane[0].mapping_stride != in intel_async_flip_check_hw()
6596 new_plane_state->view.color_plane[0].mapping_stride) { in intel_async_flip_check_hw()
6597 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6599 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6600 return -EINVAL; in intel_async_flip_check_hw()
6603 if (old_plane_state->hw.fb->modifier != in intel_async_flip_check_hw()
6604 new_plane_state->hw.fb->modifier) { in intel_async_flip_check_hw()
6605 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6607 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6608 return -EINVAL; in intel_async_flip_check_hw()
6611 if (old_plane_state->hw.fb->format != in intel_async_flip_check_hw()
6612 new_plane_state->hw.fb->format) { in intel_async_flip_check_hw()
6613 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6615 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6616 return -EINVAL; in intel_async_flip_check_hw()
6619 if (old_plane_state->hw.rotation != in intel_async_flip_check_hw()
6620 new_plane_state->hw.rotation) { in intel_async_flip_check_hw()
6621 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6623 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6624 return -EINVAL; in intel_async_flip_check_hw()
6627 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || in intel_async_flip_check_hw()
6628 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { in intel_async_flip_check_hw()
6629 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6630 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", in intel_async_flip_check_hw()
6631 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6632 return -EINVAL; in intel_async_flip_check_hw()
6635 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { in intel_async_flip_check_hw()
6636 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6638 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6639 return -EINVAL; in intel_async_flip_check_hw()
6642 if (old_plane_state->hw.pixel_blend_mode != in intel_async_flip_check_hw()
6643 new_plane_state->hw.pixel_blend_mode) { in intel_async_flip_check_hw()
6644 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6646 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6647 return -EINVAL; in intel_async_flip_check_hw()
6650 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { in intel_async_flip_check_hw()
6651 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6653 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6654 return -EINVAL; in intel_async_flip_check_hw()
6657 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { in intel_async_flip_check_hw()
6658 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6660 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6661 return -EINVAL; in intel_async_flip_check_hw()
6665 if (old_plane_state->decrypt != new_plane_state->decrypt) { in intel_async_flip_check_hw()
6666 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6668 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6669 return -EINVAL; in intel_async_flip_check_hw()
6678 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_bigjoiner_add_affected_crtcs()
6686 affected_pipes |= crtc_state->bigjoiner_pipes; in intel_bigjoiner_add_affected_crtcs()
6688 modeset_pipes |= crtc_state->bigjoiner_pipes; in intel_bigjoiner_add_affected_crtcs()
6691 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { in intel_bigjoiner_add_affected_crtcs()
6692 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_bigjoiner_add_affected_crtcs()
6697 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { in intel_bigjoiner_add_affected_crtcs()
6702 crtc_state->uapi.mode_changed = true; in intel_bigjoiner_add_affected_crtcs()
6704 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); in intel_bigjoiner_add_affected_crtcs()
6714 /* Kill old bigjoiner link, we may re-establish afterwards */ in intel_bigjoiner_add_affected_crtcs()
6724 * intel_atomic_check - validate state object
6740 if (new_crtc_state->inherited != old_crtc_state->inherited) in intel_atomic_check()
6741 new_crtc_state->uapi.mode_changed = true; in intel_atomic_check()
6743 if (new_crtc_state->uapi.scaling_filter != in intel_atomic_check()
6744 old_crtc_state->uapi.scaling_filter) in intel_atomic_check()
6745 new_crtc_state->uapi.mode_changed = true; in intel_atomic_check()
6750 ret = drm_atomic_helper_check_modeset(dev, &state->base); in intel_atomic_check()
6775 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); in intel_atomic_check()
6783 if (!new_crtc_state->hw.enable) in intel_atomic_check()
6800 if (new_crtc_state->hw.enable) { in intel_atomic_check()
6821 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) in intel_atomic_check()
6825 enum transcoder master = new_crtc_state->mst_master_transcoder; in intel_atomic_check()
6828 new_crtc_state->uapi.mode_changed = true; in intel_atomic_check()
6829 new_crtc_state->update_pipe = false; in intel_atomic_check()
6834 u8 trans = new_crtc_state->sync_mode_slaves_mask; in intel_atomic_check()
6836 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) in intel_atomic_check()
6837 trans |= BIT(new_crtc_state->master_transcoder); in intel_atomic_check()
6840 new_crtc_state->uapi.mode_changed = true; in intel_atomic_check()
6841 new_crtc_state->update_pipe = false; in intel_atomic_check()
6845 if (new_crtc_state->bigjoiner_pipes) { in intel_atomic_check()
6846 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { in intel_atomic_check()
6847 new_crtc_state->uapi.mode_changed = true; in intel_atomic_check()
6848 new_crtc_state->update_pipe = false; in intel_atomic_check()
6864 drm_dbg_kms(&dev_priv->drm, in intel_atomic_check()
6866 ret = -EINVAL; in intel_atomic_check()
6870 ret = drm_dp_mst_atomic_check(&state->base); in intel_atomic_check()
6918 !new_crtc_state->update_pipe) in intel_atomic_check()
6929 if (ret == -EDEADLK) in intel_atomic_check()
6949 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); in intel_atomic_prepare_commit()
6956 if (mode_changed || crtc_state->update_pipe || in intel_atomic_prepare_commit()
6957 crtc_state->uapi.color_mgmt_changed) { in intel_atomic_prepare_commit()
6968 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_arm_fifo_underrun()
6970 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) in intel_crtc_arm_fifo_underrun()
6971 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); in intel_crtc_arm_fifo_underrun()
6973 if (crtc_state->has_pch_encoder) { in intel_crtc_arm_fifo_underrun()
6984 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); in intel_pipe_fastset()
6985 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_pipe_fastset()
6999 if (new_crtc_state->pch_pfit.enabled) in intel_pipe_fastset()
7002 if (new_crtc_state->pch_pfit.enabled) in intel_pipe_fastset()
7004 else if (old_crtc_state->pch_pfit.enabled) in intel_pipe_fastset()
7020 if (new_crtc_state->seamless_m_n) in intel_pipe_fastset()
7021 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, in intel_pipe_fastset()
7022 &new_crtc_state->dp_m_n); in intel_pipe_fastset()
7028 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in commit_pipe_pre_planes()
7040 if (new_crtc_state->uapi.color_mgmt_changed || in commit_pipe_pre_planes()
7041 new_crtc_state->update_pipe) in commit_pipe_pre_planes()
7047 if (new_crtc_state->update_pipe) in commit_pipe_pre_planes()
7059 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in commit_pipe_post_planes()
7076 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_enable_crtc()
7085 dev_priv->display.funcs.display->crtc_enable(state, crtc); in intel_enable_crtc()
7090 /* vblanks work again, re-enable pipe CRC. */ in intel_enable_crtc()
7097 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_update_crtc()
7105 if (new_crtc_state->preload_luts && in intel_update_crtc()
7106 (new_crtc_state->uapi.color_mgmt_changed || in intel_update_crtc()
7107 new_crtc_state->update_pipe)) in intel_update_crtc()
7112 if (new_crtc_state->update_pipe) in intel_update_crtc()
7116 new_crtc_state->update_pipe) in intel_update_crtc()
7123 (new_crtc_state->uapi.color_mgmt_changed || in intel_update_crtc()
7124 new_crtc_state->update_pipe)) in intel_update_crtc()
7146 if (new_crtc_state->update_pipe && !modeset && in intel_update_crtc()
7147 old_crtc_state->inherited) in intel_update_crtc()
7156 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_old_crtc_state_disables()
7164 dev_priv->display.funcs.display->crtc_disable(state, crtc); in intel_old_crtc_state_disables()
7165 crtc->active = false; in intel_old_crtc_state_disables()
7170 if (!new_crtc_state->hw.active && in intel_old_crtc_state_disables()
7187 if (!old_crtc_state->hw.active) in intel_commit_modeset_disables()
7200 if (!old_crtc_state->hw.active) in intel_commit_modeset_disables()
7215 handled |= BIT(crtc->pipe); in intel_commit_modeset_disables()
7222 (handled & BIT(crtc->pipe))) in intel_commit_modeset_disables()
7225 if (!old_crtc_state->hw.active) in intel_commit_modeset_disables()
7240 if (!new_crtc_state->hw.active) in intel_commit_modeset_enables()
7250 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in skl_commit_modeset_enables()
7258 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
7260 if (!new_crtc_state->hw.active) in skl_commit_modeset_enables()
7265 entries[pipe] = old_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
7284 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
7289 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
7293 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
7304 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
7305 &old_crtc_state->wm.skl.ddb) && in skl_commit_modeset_enables()
7318 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
7338 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
7352 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
7357 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
7360 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
7366 drm_WARN_ON(&dev_priv->drm, modeset_pipes); in skl_commit_modeset_enables()
7367 drm_WARN_ON(&dev_priv->drm, update_pipes); in skl_commit_modeset_enables()
7375 freed = llist_del_all(&dev_priv->display.atomic_helper.free_list); in intel_atomic_helper_free_state()
7377 drm_atomic_state_put(&state->base); in intel_atomic_helper_free_state()
7391 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); in intel_atomic_commit_fence_wait()
7396 prepare_to_wait(&intel_state->commit_ready.wait, in intel_atomic_commit_fence_wait()
7398 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, in intel_atomic_commit_fence_wait()
7403 if (i915_sw_fence_done(&intel_state->commit_ready) || in intel_atomic_commit_fence_wait()
7404 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) in intel_atomic_commit_fence_wait()
7409 finish_wait(&intel_state->commit_ready.wait, &wait_fence); in intel_atomic_commit_fence_wait()
7410 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, in intel_atomic_commit_fence_wait()
7430 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_atomic_cleanup_work()
7433 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); in intel_atomic_cleanup_work()
7434 drm_atomic_helper_commit_cleanup_done(&state->base); in intel_atomic_cleanup_work()
7435 drm_atomic_state_put(&state->base); in intel_atomic_cleanup_work()
7442 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_atomic_prepare_plane_clear_colors()
7448 struct drm_framebuffer *fb = plane_state->hw.fb; in intel_atomic_prepare_plane_clear_colors()
7464 * - 4 x 4 bytes per-channel value in intel_atomic_prepare_plane_clear_colors()
7466 * - 8 bytes native color value used by the display in intel_atomic_prepare_plane_clear_colors()
7468 * above per-channel values) in intel_atomic_prepare_plane_clear_colors()
7475 fb->offsets[cc_plane] + 16, in intel_atomic_prepare_plane_clear_colors()
7476 &plane_state->ccval, in intel_atomic_prepare_plane_clear_colors()
7477 sizeof(plane_state->ccval)); in intel_atomic_prepare_plane_clear_colors()
7479 drm_WARN_ON(&i915->drm, ret); in intel_atomic_prepare_plane_clear_colors()
7485 struct drm_device *dev = state->base.dev; in intel_atomic_commit_tail()
7495 drm_atomic_helper_wait_for_dependencies(&state->base); in intel_atomic_commit_tail()
7496 drm_dp_mst_atomic_wait_for_dependencies(&state->base); in intel_atomic_commit_tail()
7498 if (state->modeset) in intel_atomic_commit_tail()
7506 new_crtc_state->update_pipe) { in intel_atomic_commit_tail()
7507 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); in intel_atomic_commit_tail()
7513 /* FIXME: Eventually get rid of our crtc->config pointer */ in intel_atomic_commit_tail()
7515 crtc->config = new_crtc_state; in intel_atomic_commit_tail()
7517 if (state->modeset) { in intel_atomic_commit_tail()
7518 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); in intel_atomic_commit_tail()
7532 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { in intel_atomic_commit_tail()
7533 spin_lock_irq(&dev->event_lock); in intel_atomic_commit_tail()
7534 drm_crtc_send_vblank_event(&crtc->base, in intel_atomic_commit_tail()
7535 new_crtc_state->uapi.event); in intel_atomic_commit_tail()
7536 spin_unlock_irq(&dev->event_lock); in intel_atomic_commit_tail()
7538 new_crtc_state->uapi.event = NULL; in intel_atomic_commit_tail()
7548 if (new_crtc_state->do_async_flip) in intel_atomic_commit_tail()
7553 dev_priv->display.funcs.display->commit_modeset_enables(state); in intel_atomic_commit_tail()
7557 if (state->modeset) in intel_atomic_commit_tail()
7565 * - wrap the optimization/post_plane_update stuff into a per-crtc work. in intel_atomic_commit_tail()
7566 * - schedule that vblank worker _before_ calling hw_done in intel_atomic_commit_tail()
7567 * - at the start of commit_tail, cancel it _synchrously in intel_atomic_commit_tail()
7568 * - switch over to the vblank wait helper in the core after that since in intel_atomic_commit_tail()
7571 drm_atomic_helper_wait_for_flip_done(dev, &state->base); in intel_atomic_commit_tail()
7574 if (new_crtc_state->do_async_flip) in intel_atomic_commit_tail()
7580 * optimal watermarks on platforms that need two-step watermark in intel_atomic_commit_tail()
7589 * So re-enable underrun reporting after some planes get enabled. in intel_atomic_commit_tail()
7596 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); in intel_atomic_commit_tail()
7607 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); in intel_atomic_commit_tail()
7616 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); in intel_atomic_commit_tail()
7623 if (state->modeset) in intel_atomic_commit_tail()
7628 drm_atomic_helper_commit_hw_done(&state->base); in intel_atomic_commit_tail()
7630 if (state->modeset) { in intel_atomic_commit_tail()
7634 * so enable debugging for the next modeset - and hope we catch in intel_atomic_commit_tail()
7637 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); in intel_atomic_commit_tail()
7640 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); in intel_atomic_commit_tail()
7645 * are executed inline. For out-of-line asynchronous modesets/flips, in intel_atomic_commit_tail()
7650 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); in intel_atomic_commit_tail()
7651 queue_work(system_highpri_wq, &state->base.commit_work); in intel_atomic_commit_tail()
7676 &to_i915(state->base.dev)->display.atomic_helper; in intel_atomic_commit_ready()
7678 if (llist_add(&state->freed, &helper->free_list)) in intel_atomic_commit_ready()
7679 schedule_work(&helper->free_work); in intel_atomic_commit_ready()
7695 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), in intel_atomic_track_fbs()
7696 to_intel_frontbuffer(new_plane_state->hw.fb), in intel_atomic_track_fbs()
7697 plane->frontbuffer_bit); in intel_atomic_track_fbs()
7708 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); in intel_atomic_commit()
7710 drm_atomic_state_get(&state->base); in intel_atomic_commit()
7711 i915_sw_fence_init(&state->commit_ready, in intel_atomic_commit()
7722 * Unset state->legacy_cursor_update before the call to in intel_atomic_commit()
7731 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { in intel_atomic_commit()
7737 if (new_crtc_state->wm.need_postvbl_update || in intel_atomic_commit()
7738 new_crtc_state->update_wm_post) in intel_atomic_commit()
7739 state->base.legacy_cursor_update = false; in intel_atomic_commit()
7744 drm_dbg_atomic(&dev_priv->drm, in intel_atomic_commit()
7746 i915_sw_fence_commit(&state->commit_ready); in intel_atomic_commit()
7747 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); in intel_atomic_commit()
7751 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); in intel_atomic_commit()
7753 ret = drm_atomic_helper_swap_state(&state->base, true); in intel_atomic_commit()
7762 i915_sw_fence_commit(&state->commit_ready); in intel_atomic_commit()
7767 drm_atomic_helper_cleanup_planes(dev, &state->base); in intel_atomic_commit()
7768 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); in intel_atomic_commit()
7774 drm_atomic_state_get(&state->base); in intel_atomic_commit()
7775 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); in intel_atomic_commit()
7777 i915_sw_fence_commit(&state->commit_ready); in intel_atomic_commit()
7778 if (nonblock && state->modeset) { in intel_atomic_commit()
7779 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); in intel_atomic_commit()
7781 queue_work(dev_priv->display.wq.flip, &state->base.commit_work); in intel_atomic_commit()
7783 if (state->modeset) in intel_atomic_commit()
7784 flush_workqueue(dev_priv->display.wq.modeset); in intel_atomic_commit()
7792 * intel_plane_destroy - destroy a plane
7808 for_each_intel_plane(&dev_priv->drm, plane) { in intel_plane_possible_crtcs_init()
7810 plane->pipe); in intel_plane_possible_crtcs_init()
7812 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); in intel_plane_possible_crtcs_init()
7824 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); in intel_get_pipe_from_crtc_id_ioctl()
7826 return -ENOENT; in intel_get_pipe_from_crtc_id_ioctl()
7829 pipe_from_crtc_id->pipe = crtc->pipe; in intel_get_pipe_from_crtc_id_ioctl()
7836 struct drm_device *dev = encoder->base.dev; in intel_encoder_possible_clones()
7842 possible_clones |= drm_encoder_mask(&source_encoder->base); in intel_encoder_possible_clones()
7850 struct drm_device *dev = encoder->base.dev; in intel_encoder_possible_crtcs()
7854 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) in intel_encoder_possible_crtcs()
7855 possible_crtcs |= drm_crtc_mask(&crtc->base); in intel_encoder_possible_crtcs()
7890 if (!dev_priv->display.vbt.int_crt_support) in intel_ddi_crt_present()
8025 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) in intel_setup_outputs()
8031 * (no way to plug in a DP->HDMI dongle) the DDC pins for in intel_setup_outputs()
8038 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap in intel_setup_outputs()
8082 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); in intel_setup_outputs()
8085 drm_dbg_kms(&dev_priv->drm, in intel_setup_outputs()
8097 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); in intel_setup_outputs()
8104 drm_dbg_kms(&dev_priv->drm, in intel_setup_outputs()
8125 for_each_intel_encoder(&dev_priv->drm, encoder) { in intel_setup_outputs()
8126 encoder->base.possible_crtcs = in intel_setup_outputs()
8128 encoder->base.possible_clones = in intel_setup_outputs()
8134 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); in intel_setup_outputs()
8139 int max_dotclock = i915->max_dotclk_freq; in max_dotclock()
8164 * reject modes with the DBLSCAN flag in encoder->compute_config(). in intel_mode_valid()
8165 * And we always reject DBLSCAN modes in connector->mode_valid() in intel_mode_valid()
8169 if (mode->vscan > 1) in intel_mode_valid()
8172 if (mode->flags & DRM_MODE_FLAG_HSKEW) in intel_mode_valid()
8175 if (mode->flags & (DRM_MODE_FLAG_CSYNC | in intel_mode_valid()
8180 if (mode->flags & (DRM_MODE_FLAG_BCAST | in intel_mode_valid()
8189 if (mode->clock > max_dotclock(dev_priv)) in intel_mode_valid()
8216 if (mode->hdisplay > hdisplay_max || in intel_mode_valid()
8217 mode->hsync_start > htotal_max || in intel_mode_valid()
8218 mode->hsync_end > htotal_max || in intel_mode_valid()
8219 mode->htotal > htotal_max) in intel_mode_valid()
8222 if (mode->vdisplay > vdisplay_max || in intel_mode_valid()
8223 mode->vsync_start > vtotal_max || in intel_mode_valid()
8224 mode->vsync_end > vtotal_max || in intel_mode_valid()
8225 mode->vtotal > vtotal_max) in intel_mode_valid()
8229 if (mode->hdisplay < 64 || in intel_mode_valid()
8230 mode->htotal - mode->hdisplay < 32) in intel_mode_valid()
8233 if (mode->vtotal - mode->vdisplay < 5) in intel_mode_valid()
8236 if (mode->htotal - mode->hdisplay < 32) in intel_mode_valid()
8239 if (mode->vtotal - mode->vdisplay < 3) in intel_mode_valid()
8248 mode->hsync_start == mode->hdisplay) in intel_mode_valid()
8281 if (mode->hdisplay > plane_width_max) in intel_mode_valid_max_plane_size()
8284 if (mode->vdisplay > plane_height_max) in intel_mode_valid_max_plane_size()
8343 * intel_init_display_hooks - initialize the display modesetting hooks
8357 dev_priv->display.funcs.display = &skl_display_funcs; in intel_init_display_hooks()
8359 dev_priv->display.funcs.display = &ddi_display_funcs; in intel_init_display_hooks()
8361 dev_priv->display.funcs.display = &pch_split_display_funcs; in intel_init_display_hooks()
8364 dev_priv->display.funcs.display = &vlv_display_funcs; in intel_init_display_hooks()
8366 dev_priv->display.funcs.display = &i9xx_display_funcs; in intel_init_display_hooks()
8379 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_modeset_init_hw()
8382 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); in intel_modeset_init_hw()
8383 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_modeset_init_hw()
8391 for_each_intel_crtc(state->dev, crtc) { in sanitize_watermarks_add_affected()
8398 if (crtc_state->hw.active) { in sanitize_watermarks_add_affected()
8403 crtc_state->inherited = true; in sanitize_watermarks_add_affected()
8407 drm_for_each_plane(plane, state->dev) { in sanitize_watermarks_add_affected()
8439 if (!dev_priv->display.funcs.wm->optimize_watermarks) in sanitize_watermarks()
8442 state = drm_atomic_state_alloc(&dev_priv->drm); in sanitize_watermarks()
8443 if (drm_WARN_ON(&dev_priv->drm, !state)) in sanitize_watermarks()
8451 state->acquire_ctx = &ctx; in sanitize_watermarks()
8459 intel_state->skip_intermediate_wm = true; in sanitize_watermarks()
8465 ret = intel_atomic_check(&dev_priv->drm, state); in sanitize_watermarks()
8471 crtc_state->wm.need_postvbl_update = true; in sanitize_watermarks()
8474 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; in sanitize_watermarks()
8478 if (ret == -EDEADLK) { in sanitize_watermarks()
8493 * BIOS-programmed watermarks untouched and hope for the best. in sanitize_watermarks()
8495 drm_WARN(&dev_priv->drm, ret, in sanitize_watermarks()
8513 return -ENOMEM; in intel_initial_commit()
8518 state->acquire_ctx = &ctx; in intel_initial_commit()
8529 if (crtc_state->hw.active) { in intel_initial_commit()
8539 crtc_state->inherited = true; in intel_initial_commit()
8541 ret = drm_atomic_add_affected_planes(state, &crtc->base); in intel_initial_commit()
8551 crtc_state->uapi.color_mgmt_changed = true; in intel_initial_commit()
8554 crtc_state->uapi.encoder_mask) { in intel_initial_commit()
8555 if (encoder->initial_fastset_check && in intel_initial_commit()
8556 !encoder->initial_fastset_check(encoder, crtc_state)) { in intel_initial_commit()
8558 &crtc->base); in intel_initial_commit()
8569 if (ret == -EDEADLK) { in intel_initial_commit()
8589 struct drm_mode_config *mode_config = &i915->drm.mode_config; in intel_mode_config_init()
8591 drm_mode_config_init(&i915->drm); in intel_mode_config_init()
8592 INIT_LIST_HEAD(&i915->global_obj_list); in intel_mode_config_init()
8594 mode_config->min_width = 0; in intel_mode_config_init()
8595 mode_config->min_height = 0; in intel_mode_config_init()
8597 mode_config->preferred_depth = 24; in intel_mode_config_init()
8598 mode_config->prefer_shadow = 1; in intel_mode_config_init()
8600 mode_config->funcs = &intel_mode_funcs; in intel_mode_config_init()
8601 mode_config->helper_private = &intel_mode_config_funcs; in intel_mode_config_init()
8603 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); in intel_mode_config_init()
8610 mode_config->max_width = 16384; in intel_mode_config_init()
8611 mode_config->max_height = 16384; in intel_mode_config_init()
8613 mode_config->max_width = 8192; in intel_mode_config_init()
8614 mode_config->max_height = 8192; in intel_mode_config_init()
8616 mode_config->max_width = 4096; in intel_mode_config_init()
8617 mode_config->max_height = 4096; in intel_mode_config_init()
8619 mode_config->max_width = 2048; in intel_mode_config_init()
8620 mode_config->max_height = 2048; in intel_mode_config_init()
8624 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; in intel_mode_config_init()
8625 mode_config->cursor_height = 1023; in intel_mode_config_init()
8628 mode_config->cursor_width = 64; in intel_mode_config_init()
8629 mode_config->cursor_height = 64; in intel_mode_config_init()
8631 mode_config->cursor_width = 256; in intel_mode_config_init()
8632 mode_config->cursor_height = 256; in intel_mode_config_init()
8639 drm_mode_config_cleanup(&i915->drm); in intel_mode_config_cleanup()
8648 return -ENODEV; in intel_modeset_init_noirq()
8651 ret = drm_vblank_init(&i915->drm, in intel_modeset_init_noirq()
8671 i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); in intel_modeset_init_noirq()
8672 i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | in intel_modeset_init_noirq()
8689 init_llist_head(&i915->display.atomic_helper.free_list); in intel_modeset_init_noirq()
8690 INIT_WORK(&i915->display.atomic_helper.free_work, in intel_modeset_init_noirq()
8712 struct drm_device *dev = &i915->drm; in intel_modeset_init_nogem()
8728 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", in intel_modeset_init_nogem()
8750 if (i915->display.cdclk.max_cdclk_freq == 0) in intel_modeset_init_nogem()
8757 if (INTEL_INFO(i915)->display.has_hti) in intel_modeset_init_nogem()
8758 i915->hti_state = intel_de_read(i915, HDPORT_STATE); in intel_modeset_init_nogem()
8765 intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx); in intel_modeset_init_nogem()
8770 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) in intel_modeset_init_nogem()
8778 * since the watermark calculation done here will use pstate->fb. in intel_modeset_init_nogem()
8800 ret = intel_initial_commit(&i915->drm); in intel_modeset_init()
8802 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); in intel_modeset_init()
8806 ret = intel_fbdev_init(&i915->drm); in intel_modeset_init()
8833 drm_WARN_ON(&dev_priv->drm, in i830_enable_pipe()
8836 drm_dbg_kms(&dev_priv->drm, in i830_enable_pipe()
8843 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | in i830_enable_pipe()
8848 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); in i830_enable_pipe()
8849 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); in i830_enable_pipe()
8850 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); in i830_enable_pipe()
8851 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); in i830_enable_pipe()
8852 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); in i830_enable_pipe()
8853 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); in i830_enable_pipe()
8854 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); in i830_enable_pipe()
8895 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", in i830_disable_pipe()
8898 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
8900 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
8902 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
8904 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
8906 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
8921 struct drm_atomic_state *state = i915->modeset_restore_state; in intel_display_resume()
8928 i915->modeset_restore_state = NULL; in intel_display_resume()
8930 state->acquire_ctx = &ctx; in intel_display_resume()
8936 if (ret != -EDEADLK) in intel_display_resume()
8950 drm_err(&i915->drm, in intel_display_resume()
8962 drm_connector_list_iter_begin(&i915->drm, &conn_iter); in intel_hpd_poll_fini()
8964 if (connector->modeset_retry_work.func) in intel_hpd_poll_fini()
8965 cancel_work_sync(&connector->modeset_retry_work); in intel_hpd_poll_fini()
8966 if (connector->hdcp.shim) { in intel_hpd_poll_fini()
8967 cancel_delayed_work_sync(&connector->hdcp.check_work); in intel_hpd_poll_fini()
8968 cancel_work_sync(&connector->hdcp.prop_work); in intel_hpd_poll_fini()
8980 flush_workqueue(i915->display.wq.flip); in intel_modeset_driver_remove()
8981 flush_workqueue(i915->display.wq.modeset); in intel_modeset_driver_remove()
8983 flush_work(&i915->display.atomic_helper.free_work); in intel_modeset_driver_remove()
8984 drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list)); in intel_modeset_driver_remove()
9001 * Due to the hpd irq storm handling the hotplug work can re-arm the in intel_modeset_driver_remove_noirq()
9022 destroy_workqueue(i915->display.wq.flip); in intel_modeset_driver_remove_noirq()
9023 destroy_workqueue(i915->display.wq.modeset); in intel_modeset_driver_remove_noirq()
9045 * apple-gmux is needed on dual GPU MacBook Pro in intel_modeset_probe_defer()
9051 /* If the LCD panel has a privacy-screen, wait for it */ in intel_modeset_probe_defer()
9052 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); in intel_modeset_probe_defer()
9053 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) in intel_modeset_probe_defer()
9075 * Some ports require correctly set-up hpd registers for in intel_display_driver_register()
9082 intel_fbdev_initial_config_async(&i915->drm); in intel_display_driver_register()
9087 * fbdev->async_cookie. in intel_display_driver_register()
9089 drm_kms_helper_poll_init(&i915->drm); in intel_display_driver_register()
9105 drm_kms_helper_poll_fini(&i915->drm); in intel_display_driver_unregister()
9106 drm_atomic_helper_shutdown(&i915->drm); in intel_display_driver_unregister()