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Searched +full:pll0 +full:- +full:refclk (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.10/Documentation/devicetree/bindings/phy/
Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
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/Linux-v5.10/drivers/ata/
Dahci_da850.c1 // SPDX-License-Identifier: GPL-2.0-or-later
51 * the refclk rate by ten. in ahci_da850_calculate_mpy()
56 WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10"); in ahci_da850_calculate_mpy()
86 * We should have divided evenly - if not, return an invalid in ahci_da850_calculate_mpy()
108 if (pmp && ret == -EBUSY) in ahci_da850_softreset()
123 * we increased the PLL0 frequency to 456MHz from the default 300MHz. in ahci_da850_hardreset()
133 } while (retry--); in ahci_da850_hardreset()
142 * No need to override .pmp_softreset - it's only used for actual
143 * PMP-enabled ports.
162 struct device *dev = &pdev->dev; in ahci_da850_probe()
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/Linux-v5.10/arch/arm64/boot/dts/ti/
Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/mux/ti-serdes.h>
13 compatible = "mmio-sram";
15 #address-cells = <1>;
16 #size-cells = <1>;
19 atf-sram@0 {
24 scm_conf: scm-conf@100000 {
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/Linux-v5.10/drivers/phy/ti/
Dphy-j721e-wiz.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
11 #include <linux/clk-provider.h>
22 #include <linux/reset-controller.h>
144 .node_name = "pll0-refclk",
148 .node_name = "pll1-refclk",
152 .node_name = "refclk-dig",
163 .node_name = "pll0-refclk",
167 .node_name = "pll1-refclk",
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/Linux-v5.10/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c2 * Copyright © 2006-2016 Intel Corporation
32 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
71 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
72 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
74 shared_dpll[i] = pll->state; in intel_atomic_duplicate_dpll_state()
83 drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); in intel_atomic_get_shared_dpll_state()
85 if (!state->dpll_set) { in intel_atomic_get_shared_dpll_state()
86 state->dpll_set = true; in intel_atomic_get_shared_dpll_state()
88 intel_atomic_duplicate_dpll_state(to_i915(s->dev), in intel_atomic_get_shared_dpll_state()
89 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
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Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
29 #include <linux/intel-iommu.h>
32 #include <linux/dma-resv.h>
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
222 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
241 dev_priv->czclk_freq); in intel_update_czclk()
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/Linux-v5.10/arch/arm/boot/dts/
Dda850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
28 operating-points-v2 = <&opp_table>;
32 opp_table: opp-table {
33 compatible = "operating-points-v2";
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/Linux-v5.10/drivers/phy/broadcom/
Dphy-brcm-sata.c1 // SPDX-License-Identifier: GPL-2.0-or-later
191 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
194 switch (priv->version) { in brcm_sata_ctrl_base()
199 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
203 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
209 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
210 void __iomem *pcb_base = priv->phy_base; in brcm_sata_phy_wr()
213 if (priv->version == BRCM_SATA_PHY_STB_40NM) in brcm_sata_phy_wr()
214 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); in brcm_sata_phy_wr()
216 pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE); in brcm_sata_phy_wr()
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/Linux-v5.10/drivers/clk/
Dclk-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
51 val = readl_relaxed(pll->pllcon); in npcm7xx_clk_pll_recalc_rate()
79 return ERR_PTR(-ENOMEM); in npcm7xx_clk_register_pll()
89 pll->pllcon = pllcon; in npcm7xx_clk_register_pll()
90 pll->hw.init = &init; in npcm7xx_clk_register_pll()
92 hw = &pll->hw; in npcm7xx_clk_register_pll()
140 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
141 * this specific clock. Otherwise, set to -1.
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/Linux-v5.10/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
365 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_write()
367 writew(val, ctx->base + offset); in cdns_regmap_write()
375 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_read()
377 *val = readw(ctx->base + offset); in cdns_regmap_read()
387 writel(val, ctx->base + offset); in cdns_regmap_dptx_write()
398 *val = readl(ctx->base + offset); in cdns_regmap_dptx_read()
497 * Structure used to store values of PHY registers for voltage-related
498 * coefficients, for particular voltage swing and pre-emphasis level. Values
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