Lines Matching +full:pll0 +full:- +full:refclk

1 // SPDX-License-Identifier: GPL-2.0-or-later
51 	 * the refclk rate by ten.  in ahci_da850_calculate_mpy()
56 	WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10");  in ahci_da850_calculate_mpy()
86 		 * We should have divided evenly - if not, return an invalid  in ahci_da850_calculate_mpy()
108 	if (pmp && ret == -EBUSY)  in ahci_da850_softreset()
123 	 * we increased the PLL0 frequency to 456MHz from the default 300MHz.  in ahci_da850_hardreset()
133 	} while (retry--);  in ahci_da850_hardreset()
142 	 * No need to override .pmp_softreset - it's only used for actual
143 	 * PMP-enabled ports.
162 	struct device *dev = &pdev->dev;  in ahci_da850_probe()
178 	 * have the functional clock at this point - call clk_get() again with  in ahci_da850_probe()
181 	if (!hpriv->clks[0]) {  in ahci_da850_probe()
186 		hpriv->clks[0] = clk;  in ahci_da850_probe()
190 	 * The second clock used by ahci-da850 is the external REFCLK. If we  in ahci_da850_probe()
194 	if (!hpriv->clks[1]) {  in ahci_da850_probe()
195 		clk = clk_get(dev, "refclk");  in ahci_da850_probe()
198 			return -ENODEV;  in ahci_da850_probe()
201 		hpriv->clks[1] = clk;  in ahci_da850_probe()
204 	mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1]));  in ahci_da850_probe()
206 		dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy);  in ahci_da850_probe()
207 		return -EINVAL;  in ahci_da850_probe()
216 		rc = -ENODEV;  in ahci_da850_probe()
220 	pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));  in ahci_da850_probe()
222 		rc = -ENOMEM;  in ahci_da850_probe()
226 	da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy);  in ahci_da850_probe()
243 	{ .compatible = "ti,da850-ahci", },