Lines Matching +full:pll0 +full:- +full:refclk
2 * Copyright © 2006-2007 Intel Corporation
29 #include <linux/intel-iommu.h>
32 #include <linux/dma-resv.h>
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
222 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
241 dev_priv->czclk_freq); in intel_update_czclk()
249 return pipe_config->port_clock; /* SPLL */ in intel_fdi_link_freq()
251 return dev_priv->fdi_pll_freq; in intel_fdi_link_freq()
407 * the range value for them is (actual_value - 2).
448 /* LVDS 100mhz refclk limits. */
547 return drm_atomic_crtc_needs_modeset(&state->uapi); in needs_modeset()
553 return crtc_state->master_transcoder != INVALID_TRANSCODER; in is_trans_port_sync_slave()
559 return crtc_state->sync_mode_slaves_mask != 0; in is_trans_port_sync_master()
570 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
571 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
575 * divided-down version of it.
578 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params() argument
580 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
581 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
582 if (WARN_ON(clock->n == 0 || clock->p == 0)) in pnv_calc_dpll_params()
584 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
585 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in pnv_calc_dpll_params()
587 return clock->dot; in pnv_calc_dpll_params()
592 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
595 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params() argument
597 clock->m = i9xx_dpll_compute_m(clock); in i9xx_calc_dpll_params()
598 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
599 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) in i9xx_calc_dpll_params()
601 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); in i9xx_calc_dpll_params()
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in i9xx_calc_dpll_params()
604 return clock->dot; in i9xx_calc_dpll_params()
607 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params() argument
609 clock->m = clock->m1 * clock->m2; in vlv_calc_dpll_params()
610 clock->p = clock->p1 * clock->p2; in vlv_calc_dpll_params()
611 if (WARN_ON(clock->n == 0 || clock->p == 0)) in vlv_calc_dpll_params()
613 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in vlv_calc_dpll_params()
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in vlv_calc_dpll_params()
616 return clock->dot / 5; in vlv_calc_dpll_params()
619 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params() argument
621 clock->m = clock->m1 * clock->m2; in chv_calc_dpll_params()
622 clock->p = clock->p1 * clock->p2; in chv_calc_dpll_params()
623 if (WARN_ON(clock->n == 0 || clock->p == 0)) in chv_calc_dpll_params()
625 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), in chv_calc_dpll_params()
626 clock->n << 22); in chv_calc_dpll_params()
627 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in chv_calc_dpll_params()
629 return clock->dot / 5; in chv_calc_dpll_params()
633 * Returns whether the given set of divisors are valid for a given refclk with
640 if (clock->n < limit->n.min || limit->n.max < clock->n) in intel_pll_is_valid()
642 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in intel_pll_is_valid()
644 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in intel_pll_is_valid()
646 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in intel_pll_is_valid()
651 if (clock->m1 <= clock->m2) in intel_pll_is_valid()
656 if (clock->p < limit->p.min || limit->p.max < clock->p) in intel_pll_is_valid()
658 if (clock->m < limit->m.min || limit->m.max < clock->m) in intel_pll_is_valid()
662 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in intel_pll_is_valid()
667 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in intel_pll_is_valid()
678 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in i9xx_select_p2_div()
682 * For LVDS just rely on its current settings for dual-channel. in i9xx_select_p2_div()
687 return limit->p2.p2_fast; in i9xx_select_p2_div()
689 return limit->p2.p2_slow; in i9xx_select_p2_div()
691 if (target < limit->p2.dot_limit) in i9xx_select_p2_div()
692 return limit->p2.p2_slow; in i9xx_select_p2_div()
694 return limit->p2.p2_fast; in i9xx_select_p2_div()
700 * refclk, or FALSE. The returned values represent the clock equation:
711 int target, int refclk, struct dpll *match_clock, in i9xx_find_best_dpll() argument
714 struct drm_device *dev = crtc_state->uapi.crtc->dev; in i9xx_find_best_dpll()
722 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in i9xx_find_best_dpll()
724 for (clock.m2 = limit->m2.min; in i9xx_find_best_dpll()
725 clock.m2 <= limit->m2.max; clock.m2++) { in i9xx_find_best_dpll()
728 for (clock.n = limit->n.min; in i9xx_find_best_dpll()
729 clock.n <= limit->n.max; clock.n++) { in i9xx_find_best_dpll()
730 for (clock.p1 = limit->p1.min; in i9xx_find_best_dpll()
731 clock.p1 <= limit->p1.max; clock.p1++) { in i9xx_find_best_dpll()
734 i9xx_calc_dpll_params(refclk, &clock); in i9xx_find_best_dpll()
740 clock.p != match_clock->p) in i9xx_find_best_dpll()
743 this_err = abs(clock.dot - target); in i9xx_find_best_dpll()
758 * refclk, or FALSE. The returned values represent the clock equation:
769 int target, int refclk, struct dpll *match_clock, in pnv_find_best_dpll() argument
772 struct drm_device *dev = crtc_state->uapi.crtc->dev; in pnv_find_best_dpll()
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in pnv_find_best_dpll()
782 for (clock.m2 = limit->m2.min; in pnv_find_best_dpll()
783 clock.m2 <= limit->m2.max; clock.m2++) { in pnv_find_best_dpll()
784 for (clock.n = limit->n.min; in pnv_find_best_dpll()
785 clock.n <= limit->n.max; clock.n++) { in pnv_find_best_dpll()
786 for (clock.p1 = limit->p1.min; in pnv_find_best_dpll()
787 clock.p1 <= limit->p1.max; clock.p1++) { in pnv_find_best_dpll()
790 pnv_calc_dpll_params(refclk, &clock); in pnv_find_best_dpll()
796 clock.p != match_clock->p) in pnv_find_best_dpll()
799 this_err = abs(clock.dot - target); in pnv_find_best_dpll()
814 * refclk, or FALSE. The returned values represent the clock equation:
825 int target, int refclk, struct dpll *match_clock, in g4x_find_best_dpll() argument
828 struct drm_device *dev = crtc_state->uapi.crtc->dev; in g4x_find_best_dpll()
839 max_n = limit->n.max; in g4x_find_best_dpll()
841 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in g4x_find_best_dpll()
843 for (clock.m1 = limit->m1.max; in g4x_find_best_dpll()
844 clock.m1 >= limit->m1.min; clock.m1--) { in g4x_find_best_dpll()
845 for (clock.m2 = limit->m2.max; in g4x_find_best_dpll()
846 clock.m2 >= limit->m2.min; clock.m2--) { in g4x_find_best_dpll()
847 for (clock.p1 = limit->p1.max; in g4x_find_best_dpll()
848 clock.p1 >= limit->p1.min; clock.p1--) { in g4x_find_best_dpll()
851 i9xx_calc_dpll_params(refclk, &clock); in g4x_find_best_dpll()
857 this_err = abs(clock.dot - target); in g4x_find_best_dpll()
888 return calculated_clock->p > best_clock->p; in vlv_PLL_is_optimal()
895 abs(target_freq - calculated_clock->dot), in vlv_PLL_is_optimal()
902 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { in vlv_PLL_is_optimal()
913 * refclk, or FALSE. The returned values represent the clock equation:
919 int target, int refclk, struct dpll *match_clock, in vlv_find_best_dpll() argument
922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_find_best_dpll()
923 struct drm_device *dev = crtc->base.dev; in vlv_find_best_dpll()
927 int max_n = min(limit->n.max, refclk / 19200); in vlv_find_best_dpll()
935 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in vlv_find_best_dpll()
936 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in vlv_find_best_dpll()
937 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; in vlv_find_best_dpll()
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in vlv_find_best_dpll()
941 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in vlv_find_best_dpll()
945 refclk * clock.m1); in vlv_find_best_dpll()
947 vlv_calc_dpll_params(refclk, &clock); in vlv_find_best_dpll()
973 * refclk, or FALSE. The returned values represent the clock equation:
979 int target, int refclk, struct dpll *match_clock, in chv_find_best_dpll() argument
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_find_best_dpll()
983 struct drm_device *dev = crtc->base.dev; in chv_find_best_dpll()
994 * set to 2. If requires to support 200Mhz refclk, we need to in chv_find_best_dpll()
1000 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in chv_find_best_dpll()
1001 for (clock.p2 = limit->p2.p2_fast; in chv_find_best_dpll()
1002 clock.p2 >= limit->p2.p2_slow; in chv_find_best_dpll()
1003 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in chv_find_best_dpll()
1009 refclk * clock.m1); in chv_find_best_dpll()
1016 chv_calc_dpll_params(refclk, &clock); in chv_find_best_dpll()
1037 int refclk = 100000; in bxt_find_best_dpll() local
1041 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
1066 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in wait_for_pipe_scanline_moving()
1067 enum pipe pipe = crtc->pipe; in wait_for_pipe_scanline_moving()
1071 drm_err(&dev_priv->drm, in wait_for_pipe_scanline_moving()
1089 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in intel_wait_for_pipe_off()
1090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_wait_for_pipe_off()
1093 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; in intel_wait_for_pipe_off()
1099 drm_WARN(&dev_priv->drm, 1, in intel_wait_for_pipe_off()
1106 /* Only for pre-ILK configs */
1146 * so pipe->transcoder cast is fine here. in assert_fdi_tx()
1215 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv))) in assert_panel_unlocked()
1251 drm_WARN_ON(&dev_priv->drm, in assert_panel_unlocked()
1299 cur_state = plane->get_hw_state(plane, &pipe); in assert_plane()
1303 plane->base.name, onoff(state), onoff(cur_state)); in assert_plane()
1311 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in assert_planes_disabled()
1314 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in assert_planes_disabled()
1401 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _vlv_enable_pll()
1402 enum pipe pipe = crtc->pipe; in _vlv_enable_pll()
1404 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1409 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); in _vlv_enable_pll()
1415 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_enable_pll()
1416 enum pipe pipe = crtc->pipe; in vlv_enable_pll()
1418 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); in vlv_enable_pll()
1423 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
1427 pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _chv_enable_pll()
1436 enum pipe pipe = crtc->pipe; in _chv_enable_pll()
1455 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1459 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); in _chv_enable_pll()
1465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_enable_pll()
1466 enum pipe pipe = crtc->pipe; in chv_enable_pll()
1468 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); in chv_enable_pll()
1473 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in chv_enable_pll()
1485 pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1487 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; in chv_enable_pll()
1493 drm_WARN_ON(&dev_priv->drm, in chv_enable_pll()
1498 pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_enable_pll()
1515 i915_reg_t reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1516 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll()
1519 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_enable_pll()
1523 assert_panel_unlocked(dev_priv, crtc->pipe); in i9xx_enable_pll()
1538 intel_de_write(dev_priv, DPLL_MD(crtc->pipe), in i9xx_enable_pll()
1539 crtc_state->dpll_hw_state.dpll_md); in i9xx_enable_pll()
1559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_disable_pll()
1560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_disable_pll()
1561 enum pipe pipe = crtc->pipe; in i9xx_disable_pll()
1568 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_disable_pll()
1623 switch (dig_port->base.port) { in vlv_wait_port_ready()
1643 drm_WARN(&dev_priv->drm, 1, in vlv_wait_port_ready()
1645 dig_port->base.base.base.id, dig_port->base.base.name, in vlv_wait_port_ready()
1652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_enable_pch_transcoder()
1653 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_enable_pch_transcoder()
1654 enum pipe pipe = crtc->pipe; in ilk_enable_pch_transcoder()
1659 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); in ilk_enable_pch_transcoder()
1713 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n", in ilk_enable_pch_transcoder()
1746 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n"); in lpt_enable_pch_transcoder()
1768 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n", in ilk_disable_pch_transcoder()
1790 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n"); in lpt_disable_pch_transcoder()
1800 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_pch_transcoder()
1805 return crtc->pipe; in intel_crtc_pch_transcoder()
1810 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_crtc_max_vblank_count()
1817 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT))) in intel_crtc_max_vblank_count()
1830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_vblank_on()
1832 assert_vblank_disabled(&crtc->base); in intel_crtc_vblank_on()
1833 drm_crtc_set_max_vblank_count(&crtc->base, in intel_crtc_vblank_on()
1835 drm_crtc_vblank_on(&crtc->base); in intel_crtc_vblank_on()
1840 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_vblank_off()
1842 drm_crtc_vblank_off(&crtc->base); in intel_crtc_vblank_off()
1843 assert_vblank_disabled(&crtc->base); in intel_crtc_vblank_off()
1848 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); in intel_enable_pipe()
1849 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_enable_pipe()
1850 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; in intel_enable_pipe()
1851 enum pipe pipe = crtc->pipe; in intel_enable_pipe()
1855 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); in intel_enable_pipe()
1870 if (new_crtc_state->has_pch_encoder) { in intel_enable_pipe()
1886 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); in intel_enable_pipe()
1906 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in intel_disable_pipe()
1907 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_disable_pipe()
1908 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; in intel_disable_pipe()
1909 enum pipe pipe = crtc->pipe; in intel_disable_pipe()
1913 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); in intel_disable_pipe()
1932 if (old_crtc_state->double_wide) in intel_disable_pipe()
1951 if (!is_ccs_modifier(fb->modifier)) in is_ccs_plane()
1954 return plane >= fb->format->num_planes / 2; in is_ccs_plane()
1966 return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane); in is_gen12_ccs_plane()
1971 if (is_ccs_modifier(fb->modifier)) in is_aux_plane()
1979 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) || in main_to_ccs_plane()
1980 (main_plane && main_plane >= fb->format->num_planes / 2)); in main_to_ccs_plane()
1982 return fb->format->num_planes / 2 + main_plane; in main_to_ccs_plane()
1987 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) || in ccs_to_main_plane()
1988 ccs_plane < fb->format->num_planes / 2); in ccs_to_main_plane()
1990 return ccs_plane - fb->format->num_planes / 2; in ccs_to_main_plane()
1993 /* Return either the main plane's CCS or - if not a CCS FB - UV plane */
1996 if (is_ccs_modifier(fb->modifier)) in intel_main_to_aux_plane()
2006 return info->is_yuv && in intel_format_info_is_yuv_semiplanar()
2007 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2); in intel_format_info_is_yuv_semiplanar()
2013 return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && in is_semiplanar_uv_plane()
2020 struct drm_i915_private *dev_priv = to_i915(fb->dev); in intel_tile_width_bytes()
2021 unsigned int cpp = fb->format->cpp[color_plane]; in intel_tile_width_bytes()
2023 switch (fb->modifier) { in intel_tile_width_bytes()
2065 MISSING_CASE(fb->modifier); in intel_tile_width_bytes()
2076 return intel_tile_size(to_i915(fb->dev)) / in intel_tile_height()
2086 unsigned int cpp = fb->format->cpp[color_plane]; in intel_tile_dims()
2099 return fb->pitches[color_plane] * tile_height; in intel_tile_row_size()
2116 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) in intel_rotation_info_size()
2117 size += rot_info->plane[i].width * rot_info->plane[i].height; in intel_rotation_info_size()
2127 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) in intel_remapped_info_size()
2128 size += rem_info->plane[i].width * rem_info->plane[i].height; in intel_remapped_info_size()
2138 view->type = I915_GGTT_VIEW_NORMAL; in intel_fill_fb_ggtt_view()
2140 view->type = I915_GGTT_VIEW_ROTATED; in intel_fill_fb_ggtt_view()
2141 view->rotated = to_intel_framebuffer(fb)->rot_info; in intel_fill_fb_ggtt_view()
2173 struct drm_i915_private *dev_priv = to_i915(fb->dev); in intel_surf_alignment()
2180 switch (fb->modifier) { in intel_surf_alignment()
2203 MISSING_CASE(fb->modifier); in intel_surf_alignment()
2210 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_plane_uses_fence()
2211 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in intel_plane_uses_fence()
2214 (plane->has_fbc && in intel_plane_uses_fence()
2215 plane_state->view.type == I915_GGTT_VIEW_NORMAL); in intel_plane_uses_fence()
2224 struct drm_device *dev = fb->dev; in intel_pin_and_fence_fb_obj()
2233 return ERR_PTR(-EINVAL); in intel_pin_and_fence_fb_obj()
2237 return ERR_PTR(-EINVAL); in intel_pin_and_fence_fb_obj()
2242 * the VT-d warning. in intel_pin_and_fence_fb_obj()
2254 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); in intel_pin_and_fence_fb_obj()
2256 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); in intel_pin_and_fence_fb_obj()
2279 * Install a fence for tiled scan-out. Pre-i965 always needs a in intel_pin_and_fence_fb_obj()
2302 if (ret == 0 && vma->fence) in intel_pin_and_fence_fb_obj()
2308 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); in intel_pin_and_fence_fb_obj()
2309 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); in intel_pin_and_fence_fb_obj()
2315 i915_gem_object_lock(vma->obj, NULL); in intel_unpin_fb_vma()
2319 i915_gem_object_unlock(vma->obj); in intel_unpin_fb_vma()
2328 return to_intel_framebuffer(fb)->rotated[color_plane].pitch; in intel_fb_pitch()
2330 return fb->pitches[color_plane]; in intel_fb_pitch()
2336 * offset is only used with linear buffers on pre-hsw and tiled buffers
2343 const struct drm_framebuffer *fb = state->hw.fb; in intel_fb_xy_to_linear()
2344 unsigned int cpp = fb->format->cpp[color_plane]; in intel_fb_xy_to_linear()
2345 unsigned int pitch = state->color_plane[color_plane].stride; in intel_fb_xy_to_linear()
2351 * Add the x/y offsets derived from fb->offsets[] to the user
2360 *x += state->color_plane[color_plane].x; in intel_add_fb_offsets()
2361 *y += state->color_plane[color_plane].y; in intel_add_fb_offsets()
2375 WARN_ON(old_offset & (tile_size - 1)); in intel_adjust_tile_offset()
2376 WARN_ON(new_offset & (tile_size - 1)); in intel_adjust_tile_offset()
2379 tiles = (old_offset - new_offset) / tile_size; in intel_adjust_tile_offset()
2393 return fb->modifier == DRM_FORMAT_MOD_LINEAR || in is_surface_linear()
2404 struct drm_i915_private *dev_priv = to_i915(fb->dev); in intel_adjust_aligned_offset()
2405 unsigned int cpp = fb->format->cpp[color_plane]; in intel_adjust_aligned_offset()
2407 drm_WARN_ON(&dev_priv->drm, new_offset > old_offset); in intel_adjust_aligned_offset()
2429 *y = (old_offset - new_offset) / pitch; in intel_adjust_aligned_offset()
2430 *x = ((old_offset - new_offset) - *y * pitch) / cpp; in intel_adjust_aligned_offset()
2445 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane, in intel_plane_adjust_aligned_offset()
2446 state->hw.rotation, in intel_plane_adjust_aligned_offset()
2447 state->color_plane[color_plane].stride, in intel_plane_adjust_aligned_offset()
2453 * x, y. bytes per pixel is assumed to be a power-of-two.
2473 unsigned int cpp = fb->format->cpp[color_plane]; in intel_compute_aligned_offset()
2511 *x = ((offset % alignment) - *y * pitch) / cpp; in intel_compute_aligned_offset()
2524 struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane); in intel_plane_compute_aligned_offset()
2525 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); in intel_plane_compute_aligned_offset()
2526 const struct drm_framebuffer *fb = state->hw.fb; in intel_plane_compute_aligned_offset()
2527 unsigned int rotation = state->hw.rotation; in intel_plane_compute_aligned_offset()
2528 int pitch = state->color_plane[color_plane].stride; in intel_plane_compute_aligned_offset()
2531 if (intel_plane->id == PLANE_CURSOR) in intel_plane_compute_aligned_offset()
2540 /* Convert the fb->offset[] into x/y offsets */
2545 struct drm_i915_private *dev_priv = to_i915(fb->dev); in intel_fb_offset_to_xy()
2552 else if (fb->modifier != DRM_FORMAT_MOD_LINEAR) in intel_fb_offset_to_xy()
2557 if (alignment != 0 && fb->offsets[color_plane] % alignment) { in intel_fb_offset_to_xy()
2558 drm_dbg_kms(&dev_priv->drm, in intel_fb_offset_to_xy()
2560 fb->offsets[color_plane], color_plane); in intel_fb_offset_to_xy()
2561 return -EINVAL; in intel_fb_offset_to_xy()
2564 height = drm_framebuffer_plane_height(fb->height, fb, color_plane); in intel_fb_offset_to_xy()
2568 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]), in intel_fb_offset_to_xy()
2569 fb->offsets[color_plane])) { in intel_fb_offset_to_xy()
2570 drm_dbg_kms(&dev_priv->drm, in intel_fb_offset_to_xy()
2572 fb->offsets[color_plane], fb->pitches[color_plane], in intel_fb_offset_to_xy()
2574 return -ERANGE; in intel_fb_offset_to_xy()
2582 fb->pitches[color_plane], in intel_fb_offset_to_xy()
2583 fb->offsets[color_plane], 0); in intel_fb_offset_to_xy()
2606 * the cache-line pairs. The compression state of the cache-line pair
2607 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2608 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2609 * cache-line-pairs. CCS is always Y tiled."
2629 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
2630 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
2631 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
2691 switch (cmd->modifier[0]) { in intel_get_format_info()
2696 cmd->pixel_format); in intel_get_format_info()
2701 cmd->pixel_format); in intel_get_format_info()
2717 return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)], in gen12_ccs_aux_stride()
2736 plane = to_intel_plane(crtc->base.primary); in intel_plane_fb_max_stride()
2738 return plane->max_stride(plane, pixel_format, modifier, in intel_plane_fb_max_stride()
2765 struct drm_i915_private *dev_priv = to_i915(fb->dev); in intel_fb_stride_alignment()
2770 fb->format->format, in intel_fb_stride_alignment()
2771 fb->modifier); in intel_fb_stride_alignment()
2777 if (fb->pitches[color_plane] > max_stride && in intel_fb_stride_alignment()
2778 !is_ccs_modifier(fb->modifier)) in intel_fb_stride_alignment()
2785 if (is_ccs_modifier(fb->modifier)) { in intel_fb_stride_alignment()
2795 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840) in intel_fb_stride_alignment()
2809 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_plane_can_remap()
2810 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in intel_plane_can_remap()
2811 const struct drm_framebuffer *fb = plane_state->hw.fb; in intel_plane_can_remap()
2815 if (plane->id == PLANE_CURSOR) in intel_plane_can_remap()
2831 if (is_ccs_modifier(fb->modifier)) in intel_plane_can_remap()
2835 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) { in intel_plane_can_remap()
2836 unsigned int alignment = intel_tile_size(dev_priv) - 1; in intel_plane_can_remap()
2838 for (i = 0; i < fb->format->num_planes; i++) { in intel_plane_can_remap()
2839 if (fb->pitches[i] & alignment) in intel_plane_can_remap()
2849 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_plane_needs_remap()
2850 const struct drm_framebuffer *fb = plane_state->hw.fb; in intel_plane_needs_remap()
2851 unsigned int rotation = plane_state->hw.rotation; in intel_plane_needs_remap()
2858 if (!plane_state->uapi.visible) in intel_plane_needs_remap()
2869 max_stride = plane->max_stride(plane, fb->format->format, in intel_plane_needs_remap()
2870 fb->modifier, rotation); in intel_plane_needs_remap()
2894 *hsub = fb->format->hsub; in intel_fb_plane_get_subsampling()
2895 *vsub = fb->format->vsub; in intel_fb_plane_get_subsampling()
2901 *hsub = drm_format_info_block_width(fb->format, color_plane) / in intel_fb_plane_get_subsampling()
2902 drm_format_info_block_width(fb->format, main_plane); in intel_fb_plane_get_subsampling()
2906 * assumes that format->hsub applies to every plane except for the in intel_fb_plane_get_subsampling()
2913 *hsub *= fb->format->hsub; in intel_fb_plane_get_subsampling()
2920 struct drm_i915_private *i915 = to_i915(fb->dev); in intel_fb_check_ccs_xy()
2941 main_x = intel_fb->normal[main_plane].x % tile_width; in intel_fb_check_ccs_xy()
2942 main_y = intel_fb->normal[main_plane].y % tile_height; in intel_fb_check_ccs_xy()
2949 drm_dbg_kms(&i915->drm, in intel_fb_check_ccs_xy()
2953 intel_fb->normal[main_plane].x, in intel_fb_check_ccs_xy()
2954 intel_fb->normal[main_plane].y, in intel_fb_check_ccs_xy()
2956 return -EINVAL; in intel_fb_check_ccs_xy()
2972 *w = fb->width / main_hsub / hsub; in intel_fb_plane_dims()
2973 *h = fb->height / main_vsub / vsub; in intel_fb_plane_dims()
2989 struct intel_rotation_info *rot_info = &intel_fb->rot_info; in setup_fb_rotation()
2994 if (fb->modifier != I915_FORMAT_MOD_Y_TILED && in setup_fb_rotation()
2995 fb->modifier != I915_FORMAT_MOD_Yf_TILED) in setup_fb_rotation()
2998 if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane))) in setup_fb_rotation()
3001 rot_info->plane[plane] = *plane_info; in setup_fb_rotation()
3003 intel_fb->rotated[plane].pitch = plane_info->height * tile_height; in setup_fb_rotation()
3008 plane_info->width * tile_width, in setup_fb_rotation()
3009 plane_info->height * tile_height, in setup_fb_rotation()
3015 pitch_tiles = intel_fb->rotated[plane].pitch / tile_height; in setup_fb_rotation()
3031 intel_fb->rotated[plane].x = x; in setup_fb_rotation()
3032 intel_fb->rotated[plane].y = y; in setup_fb_rotation()
3034 return plane_info->width * plane_info->height; in setup_fb_rotation()
3045 int i, num_planes = fb->format->num_planes; in intel_fill_fb_info()
3055 cpp = fb->format->cpp[i]; in intel_fill_fb_info()
3060 drm_dbg_kms(&dev_priv->drm, in intel_fill_fb_info()
3062 i, fb->offsets[i]); in intel_fill_fb_info()
3080 (x + width) * cpp > fb->pitches[i]) { in intel_fill_fb_info()
3081 drm_dbg_kms(&dev_priv->drm, in intel_fill_fb_info()
3083 i, fb->offsets[i]); in intel_fill_fb_info()
3084 return -EINVAL; in intel_fill_fb_info()
3091 intel_fb->normal[i].x = x; in intel_fill_fb_info()
3092 intel_fb->normal[i].y = y; in intel_fill_fb_info()
3095 fb->pitches[i], in intel_fill_fb_info()
3107 plane_info.stride = DIV_ROUND_UP(fb->pitches[i], in intel_fill_fb_info()
3130 size = DIV_ROUND_UP((y + height) * fb->pitches[i] + in intel_fill_fb_info()
3138 if (mul_u32_u32(max_size, tile_size) > obj->base.size) { in intel_fill_fb_info()
3139 drm_dbg_kms(&dev_priv->drm, in intel_fill_fb_info()
3141 mul_u32_u32(max_size, tile_size), obj->base.size); in intel_fill_fb_info()
3142 return -EINVAL; in intel_fill_fb_info()
3152 to_i915(plane_state->uapi.plane->dev); in intel_plane_remap_gtt()
3153 struct drm_framebuffer *fb = plane_state->hw.fb; in intel_plane_remap_gtt()
3155 struct intel_rotation_info *info = &plane_state->view.rotated; in intel_plane_remap_gtt()
3156 unsigned int rotation = plane_state->hw.rotation; in intel_plane_remap_gtt()
3157 int i, num_planes = fb->format->num_planes; in intel_plane_remap_gtt()
3163 memset(&plane_state->view, 0, sizeof(plane_state->view)); in intel_plane_remap_gtt()
3164 plane_state->view.type = drm_rotation_90_or_270(rotation) ? in intel_plane_remap_gtt()
3167 src_x = plane_state->uapi.src.x1 >> 16; in intel_plane_remap_gtt()
3168 src_y = plane_state->uapi.src.y1 >> 16; in intel_plane_remap_gtt()
3169 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; in intel_plane_remap_gtt()
3170 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; in intel_plane_remap_gtt()
3172 drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier)); in intel_plane_remap_gtt()
3175 drm_rect_translate(&plane_state->uapi.src, in intel_plane_remap_gtt()
3176 -(src_x << 16), -(src_y << 16)); in intel_plane_remap_gtt()
3180 drm_rect_rotate(&plane_state->uapi.src, in intel_plane_remap_gtt()
3185 unsigned int hsub = i ? fb->format->hsub : 1; in intel_plane_remap_gtt()
3186 unsigned int vsub = i ? fb->format->vsub : 1; in intel_plane_remap_gtt()
3187 unsigned int cpp = fb->format->cpp[i]; in intel_plane_remap_gtt()
3205 x += intel_fb->normal[i].x; in intel_plane_remap_gtt()
3206 y += intel_fb->normal[i].y; in intel_plane_remap_gtt()
3209 fb, i, fb->pitches[i], in intel_plane_remap_gtt()
3213 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane)); in intel_plane_remap_gtt()
3214 info->plane[i].offset = offset; in intel_plane_remap_gtt()
3215 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], in intel_plane_remap_gtt()
3217 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); in intel_plane_remap_gtt()
3218 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); in intel_plane_remap_gtt()
3226 info->plane[i].width * tile_width, in intel_plane_remap_gtt()
3227 info->plane[i].height * tile_height, in intel_plane_remap_gtt()
3232 pitch_tiles = info->plane[i].height; in intel_plane_remap_gtt()
3233 plane_state->color_plane[i].stride = pitch_tiles * tile_height; in intel_plane_remap_gtt()
3238 pitch_tiles = info->plane[i].width; in intel_plane_remap_gtt()
3239 plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp; in intel_plane_remap_gtt()
3251 gtt_offset += info->plane[i].width * info->plane[i].height; in intel_plane_remap_gtt()
3253 plane_state->color_plane[i].offset = 0; in intel_plane_remap_gtt()
3254 plane_state->color_plane[i].x = x; in intel_plane_remap_gtt()
3255 plane_state->color_plane[i].y = y; in intel_plane_remap_gtt()
3263 to_intel_framebuffer(plane_state->hw.fb); in intel_plane_compute_gtt()
3264 unsigned int rotation = plane_state->hw.rotation; in intel_plane_compute_gtt()
3270 num_planes = fb->base.format->num_planes; in intel_plane_compute_gtt()
3284 intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation); in intel_plane_compute_gtt()
3287 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation); in intel_plane_compute_gtt()
3288 plane_state->color_plane[i].offset = 0; in intel_plane_compute_gtt()
3291 plane_state->color_plane[i].x = fb->rotated[i].x; in intel_plane_compute_gtt()
3292 plane_state->color_plane[i].y = fb->rotated[i].y; in intel_plane_compute_gtt()
3294 plane_state->color_plane[i].x = fb->normal[i].x; in intel_plane_compute_gtt()
3295 plane_state->color_plane[i].y = fb->normal[i].y; in intel_plane_compute_gtt()
3301 drm_rect_rotate(&plane_state->uapi.src, in intel_plane_compute_gtt()
3302 fb->base.width << 16, fb->base.height << 16, in intel_plane_compute_gtt()
3416 if (plane_config->size == 0) in initial_plane_vma()
3419 base = round_down(plane_config->base, in initial_plane_vma()
3421 size = round_up(plane_config->base + plane_config->size, in initial_plane_vma()
3423 size -= base; in initial_plane_vma()
3430 if (size * 2 > i915->stolen_usable_size) in initial_plane_vma()
3445 switch (plane_config->tiling) { in initial_plane_vma()
3450 obj->tiling_and_stride = in initial_plane_vma()
3451 plane_config->fb->base.pitches[0] | in initial_plane_vma()
3452 plane_config->tiling; in initial_plane_vma()
3455 MISSING_CASE(plane_config->tiling); in initial_plane_vma()
3459 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL); in initial_plane_vma()
3481 struct drm_device *dev = crtc->base.dev; in intel_alloc_initial_plane_obj()
3484 struct drm_framebuffer *fb = &plane_config->fb->base; in intel_alloc_initial_plane_obj()
3487 switch (fb->modifier) { in intel_alloc_initial_plane_obj()
3493 drm_dbg(&dev_priv->drm, in intel_alloc_initial_plane_obj()
3495 fb->modifier); in intel_alloc_initial_plane_obj()
3503 mode_cmd.pixel_format = fb->format->format; in intel_alloc_initial_plane_obj()
3504 mode_cmd.width = fb->width; in intel_alloc_initial_plane_obj()
3505 mode_cmd.height = fb->height; in intel_alloc_initial_plane_obj()
3506 mode_cmd.pitches[0] = fb->pitches[0]; in intel_alloc_initial_plane_obj()
3507 mode_cmd.modifier[0] = fb->modifier; in intel_alloc_initial_plane_obj()
3511 vma->obj, &mode_cmd)) { in intel_alloc_initial_plane_obj()
3512 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n"); in intel_alloc_initial_plane_obj()
3516 plane_config->vma = vma; in intel_alloc_initial_plane_obj()
3529 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_set_plane_visible()
3531 plane_state->uapi.visible = visible; in intel_set_plane_visible()
3534 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); in intel_set_plane_visible()
3536 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); in intel_set_plane_visible()
3541 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in fixup_active_planes()
3549 crtc_state->active_planes = 0; in fixup_active_planes()
3551 drm_for_each_plane_mask(plane, &dev_priv->drm, in fixup_active_planes()
3552 crtc_state->uapi.plane_mask) in fixup_active_planes()
3553 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); in fixup_active_planes()
3559 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_plane_disable_noatomic()
3561 to_intel_crtc_state(crtc->base.state); in intel_plane_disable_noatomic()
3563 to_intel_plane_state(plane->base.state); in intel_plane_disable_noatomic()
3565 drm_dbg_kms(&dev_priv->drm, in intel_plane_disable_noatomic()
3567 plane->base.base.id, plane->base.name, in intel_plane_disable_noatomic()
3568 crtc->base.base.id, crtc->base.name); in intel_plane_disable_noatomic()
3572 crtc_state->data_rate[plane->id] = 0; in intel_plane_disable_noatomic()
3573 crtc_state->min_cdclk[plane->id] = 0; in intel_plane_disable_noatomic()
3575 if (plane->id == PLANE_PRIMARY) in intel_plane_disable_noatomic()
3580 * are blocked if the memory self-refresh mode is active at that in intel_plane_disable_noatomic()
3582 * first the self-refresh mode. The self-refresh enable bit in turn in intel_plane_disable_noatomic()
3585 * wait-for-vblank between disabling the plane and the pipe. in intel_plane_disable_noatomic()
3589 intel_wait_for_vblank(dev_priv, crtc->pipe); in intel_plane_disable_noatomic()
3595 if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes) in intel_plane_disable_noatomic()
3596 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); in intel_plane_disable_noatomic()
3604 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; in to_intel_frontbuffer()
3611 struct drm_device *dev = intel_crtc->base.dev; in intel_find_initial_plane_obj()
3614 struct drm_plane *primary = intel_crtc->base.primary; in intel_find_initial_plane_obj()
3615 struct drm_plane_state *plane_state = primary->state; in intel_find_initial_plane_obj()
3622 if (!plane_config->fb) in intel_find_initial_plane_obj()
3626 fb = &plane_config->fb->base; in intel_find_initial_plane_obj()
3627 vma = plane_config->vma; in intel_find_initial_plane_obj()
3638 if (c == &intel_crtc->base) in intel_find_initial_plane_obj()
3641 if (!to_intel_crtc(c)->active) in intel_find_initial_plane_obj()
3644 state = to_intel_plane_state(c->primary->state); in intel_find_initial_plane_obj()
3645 if (!state->vma) in intel_find_initial_plane_obj()
3648 if (intel_plane_ggtt_offset(state) == plane_config->base) { in intel_find_initial_plane_obj()
3649 fb = state->hw.fb; in intel_find_initial_plane_obj()
3650 vma = state->vma; in intel_find_initial_plane_obj()
3667 intel_state->hw.rotation = plane_config->rotation; in intel_find_initial_plane_obj()
3668 intel_fill_fb_ggtt_view(&intel_state->view, fb, in intel_find_initial_plane_obj()
3669 intel_state->hw.rotation); in intel_find_initial_plane_obj()
3670 intel_state->color_plane[0].stride = in intel_find_initial_plane_obj()
3671 intel_fb_pitch(fb, 0, intel_state->hw.rotation); in intel_find_initial_plane_obj()
3674 intel_state->vma = i915_vma_get(vma); in intel_find_initial_plane_obj()
3676 if (vma->fence) in intel_find_initial_plane_obj()
3677 intel_state->flags |= PLANE_HAS_FENCE; in intel_find_initial_plane_obj()
3679 plane_state->src_x = 0; in intel_find_initial_plane_obj()
3680 plane_state->src_y = 0; in intel_find_initial_plane_obj()
3681 plane_state->src_w = fb->width << 16; in intel_find_initial_plane_obj()
3682 plane_state->src_h = fb->height << 16; in intel_find_initial_plane_obj()
3684 plane_state->crtc_x = 0; in intel_find_initial_plane_obj()
3685 plane_state->crtc_y = 0; in intel_find_initial_plane_obj()
3686 plane_state->crtc_w = fb->width; in intel_find_initial_plane_obj()
3687 plane_state->crtc_h = fb->height; in intel_find_initial_plane_obj()
3689 intel_state->uapi.src = drm_plane_state_src(plane_state); in intel_find_initial_plane_obj()
3690 intel_state->uapi.dst = drm_plane_state_dest(plane_state); in intel_find_initial_plane_obj()
3692 if (plane_config->tiling) in intel_find_initial_plane_obj()
3693 dev_priv->preserve_bios_swizzle = true; in intel_find_initial_plane_obj()
3695 plane_state->fb = fb; in intel_find_initial_plane_obj()
3698 plane_state->crtc = &intel_crtc->base; in intel_find_initial_plane_obj()
3703 atomic_or(to_intel_plane(primary)->frontbuffer_bit, in intel_find_initial_plane_obj()
3704 &to_intel_frontbuffer(fb)->bits); in intel_find_initial_plane_obj()
3711 int cpp = fb->format->cpp[color_plane]; in skl_max_plane_width()
3713 switch (fb->modifier) { in skl_max_plane_width()
3719 * - Ytile (already limited to 4k) in skl_max_plane_width()
3720 * - FP16 (already limited to 4k) in skl_max_plane_width()
3721 * - render compression (already limited to 4k) in skl_max_plane_width()
3722 * - KVMR sprite and cursor (don't care) in skl_max_plane_width()
3723 * - horizontal panning (TODO verify this) in skl_max_plane_width()
3724 * - pipe and plane scaling (TODO verify this) in skl_max_plane_width()
3741 MISSING_CASE(fb->modifier); in skl_max_plane_width()
3750 int cpp = fb->format->cpp[color_plane]; in glk_max_plane_width()
3752 switch (fb->modifier) { in glk_max_plane_width()
3769 MISSING_CASE(fb->modifier); in glk_max_plane_width()
3777 switch (fb->format->format) { in icl_min_plane_width()
3834 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_check_main_ccs_coordinates()
3835 int aux_x = plane_state->color_plane[ccs_plane].x; in skl_check_main_ccs_coordinates()
3836 int aux_y = plane_state->color_plane[ccs_plane].y; in skl_check_main_ccs_coordinates()
3837 u32 aux_offset = plane_state->color_plane[ccs_plane].offset; in skl_check_main_ccs_coordinates()
3858 aux_offset - in skl_check_main_ccs_coordinates()
3867 plane_state->color_plane[ccs_plane].offset = aux_offset; in skl_check_main_ccs_coordinates()
3868 plane_state->color_plane[ccs_plane].x = aux_x; in skl_check_main_ccs_coordinates()
3869 plane_state->color_plane[ccs_plane].y = aux_y; in skl_check_main_ccs_coordinates()
3880 plane_state->color_plane[0].offset, 0); in intel_plane_fence_y_offset()
3887 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); in skl_check_main_surface()
3888 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_check_main_surface()
3889 unsigned int rotation = plane_state->hw.rotation; in skl_check_main_surface()
3890 int x = plane_state->uapi.src.x1 >> 16; in skl_check_main_surface()
3891 int y = plane_state->uapi.src.y1 >> 16; in skl_check_main_surface()
3892 int w = drm_rect_width(&plane_state->uapi.src) >> 16; in skl_check_main_surface()
3893 int h = drm_rect_height(&plane_state->uapi.src) >> 16; in skl_check_main_surface()
3897 u32 aux_offset = plane_state->color_plane[aux_plane].offset; in skl_check_main_surface()
3916 drm_dbg_kms(&dev_priv->drm, in skl_check_main_surface()
3919 return -EINVAL; in skl_check_main_surface()
3925 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) in skl_check_main_surface()
3926 return -EINVAL; in skl_check_main_surface()
3930 * main surface offset, and it must be non-negative. Make in skl_check_main_surface()
3935 offset, aux_offset & ~(alignment - 1)); in skl_check_main_surface()
3938 * When using an X-tiled surface, the plane blows up in skl_check_main_surface()
3941 * TODO: linear and Y-tiled seem fine, Yf untested, in skl_check_main_surface()
3943 if (fb->modifier == I915_FORMAT_MOD_X_TILED) { in skl_check_main_surface()
3944 int cpp = fb->format->cpp[0]; in skl_check_main_surface()
3946 while ((x + w) * cpp > plane_state->color_plane[0].stride) { in skl_check_main_surface()
3948 drm_dbg_kms(&dev_priv->drm, in skl_check_main_surface()
3949 "Unable to find suitable display surface offset due to X-tiling\n"); in skl_check_main_surface()
3950 return -EINVAL; in skl_check_main_surface()
3954 offset, offset - alignment); in skl_check_main_surface()
3962 if (is_ccs_modifier(fb->modifier)) { in skl_check_main_surface()
3969 offset, offset - alignment); in skl_check_main_surface()
3972 if (x != plane_state->color_plane[aux_plane].x || in skl_check_main_surface()
3973 y != plane_state->color_plane[aux_plane].y) { in skl_check_main_surface()
3974 drm_dbg_kms(&dev_priv->drm, in skl_check_main_surface()
3976 return -EINVAL; in skl_check_main_surface()
3980 plane_state->color_plane[0].offset = offset; in skl_check_main_surface()
3981 plane_state->color_plane[0].x = x; in skl_check_main_surface()
3982 plane_state->color_plane[0].y = y; in skl_check_main_surface()
3988 drm_rect_translate_to(&plane_state->uapi.src, in skl_check_main_surface()
3996 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); in skl_check_nv12_aux_surface()
3997 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_check_nv12_aux_surface()
3998 unsigned int rotation = plane_state->hw.rotation; in skl_check_nv12_aux_surface()
4002 int x = plane_state->uapi.src.x1 >> 17; in skl_check_nv12_aux_surface()
4003 int y = plane_state->uapi.src.y1 >> 17; in skl_check_nv12_aux_surface()
4004 int w = drm_rect_width(&plane_state->uapi.src) >> 17; in skl_check_nv12_aux_surface()
4005 int h = drm_rect_height(&plane_state->uapi.src) >> 17; in skl_check_nv12_aux_surface()
4014 drm_dbg_kms(&i915->drm, in skl_check_nv12_aux_surface()
4017 return -EINVAL; in skl_check_nv12_aux_surface()
4020 if (is_ccs_modifier(fb->modifier)) { in skl_check_nv12_aux_surface()
4022 int aux_offset = plane_state->color_plane[ccs_plane].offset; in skl_check_nv12_aux_surface()
4030 aux_offset & ~(alignment - 1)); in skl_check_nv12_aux_surface()
4040 offset, offset - alignment); in skl_check_nv12_aux_surface()
4043 if (x != plane_state->color_plane[ccs_plane].x || in skl_check_nv12_aux_surface()
4044 y != plane_state->color_plane[ccs_plane].y) { in skl_check_nv12_aux_surface()
4045 drm_dbg_kms(&i915->drm, in skl_check_nv12_aux_surface()
4047 return -EINVAL; in skl_check_nv12_aux_surface()
4051 plane_state->color_plane[uv_plane].offset = offset; in skl_check_nv12_aux_surface()
4052 plane_state->color_plane[uv_plane].x = x; in skl_check_nv12_aux_surface()
4053 plane_state->color_plane[uv_plane].y = y; in skl_check_nv12_aux_surface()
4060 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_check_ccs_aux_surface()
4061 int src_x = plane_state->uapi.src.x1 >> 16; in skl_check_ccs_aux_surface()
4062 int src_y = plane_state->uapi.src.y1 >> 16; in skl_check_ccs_aux_surface()
4066 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) { in skl_check_ccs_aux_surface()
4089 plane_state->color_plane[ccs_plane].offset = offset; in skl_check_ccs_aux_surface()
4090 plane_state->color_plane[ccs_plane].x = (x * hsub + in skl_check_ccs_aux_surface()
4093 plane_state->color_plane[ccs_plane].y = (y * vsub + in skl_check_ccs_aux_surface()
4103 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_check_plane_surface()
4110 if (!plane_state->uapi.visible) in skl_check_plane_surface()
4117 if (is_ccs_modifier(fb->modifier)) { in skl_check_plane_surface()
4123 if (intel_format_info_is_yuv_semiplanar(fb->format, in skl_check_plane_surface()
4124 fb->modifier)) { in skl_check_plane_surface()
4130 for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane); i++) { in skl_check_plane_surface()
4131 plane_state->color_plane[i].offset = ~0xfff; in skl_check_plane_surface()
4132 plane_state->color_plane[i].x = 0; in skl_check_plane_surface()
4133 plane_state->color_plane[i].y = 0; in skl_check_plane_surface()
4147 const struct drm_framebuffer *fb = plane_state->hw.fb; in i9xx_plane_ratio()
4148 unsigned int cpp = fb->format->cpp[0]; in i9xx_plane_ratio()
4173 * Note that crtc_state->pixel_rate accounts for both in i9xx_plane_min_cdclk()
4175 * Pre-HSW bspec tells us to only consider the horizontal in i9xx_plane_min_cdclk()
4179 pixel_rate = crtc_state->pixel_rate; in i9xx_plane_min_cdclk()
4184 if (crtc_state->double_wide) in i9xx_plane_min_cdclk()
4195 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i9xx_plane_max_stride()
4210 if (plane->i9xx_plane == PLANE_C) in i9xx_plane_max_stride()
4219 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_plane_ctl_crtc()
4220 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_plane_ctl_crtc()
4223 if (crtc_state->gamma_enable) in i9xx_plane_ctl_crtc()
4226 if (crtc_state->csc_enable) in i9xx_plane_ctl_crtc()
4230 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); in i9xx_plane_ctl_crtc()
4239 to_i915(plane_state->uapi.plane->dev); in i9xx_plane_ctl()
4240 const struct drm_framebuffer *fb = plane_state->hw.fb; in i9xx_plane_ctl()
4241 unsigned int rotation = plane_state->hw.rotation; in i9xx_plane_ctl()
4250 switch (fb->format->format) { in i9xx_plane_ctl()
4291 MISSING_CASE(fb->format->format); in i9xx_plane_ctl()
4296 fb->modifier == I915_FORMAT_MOD_X_TILED) in i9xx_plane_ctl()
4311 to_i915(plane_state->uapi.plane->dev); in i9xx_check_plane_surface()
4312 const struct drm_framebuffer *fb = plane_state->hw.fb; in i9xx_check_plane_surface()
4321 if (!plane_state->uapi.visible) in i9xx_check_plane_surface()
4324 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; in i9xx_check_plane_surface()
4325 src_x = plane_state->uapi.src.x1 >> 16; in i9xx_check_plane_surface()
4326 src_y = plane_state->uapi.src.y1 >> 16; in i9xx_check_plane_surface()
4329 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048) in i9xx_check_plane_surface()
4330 return -EINVAL; in i9xx_check_plane_surface()
4344 drm_rect_translate_to(&plane_state->uapi.src, in i9xx_check_plane_surface()
4349 unsigned int rotation = plane_state->hw.rotation; in i9xx_check_plane_surface()
4350 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; in i9xx_check_plane_surface()
4351 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; in i9xx_check_plane_surface()
4354 src_x += src_w - 1; in i9xx_check_plane_surface()
4355 src_y += src_h - 1; in i9xx_check_plane_surface()
4357 src_x += src_w - 1; in i9xx_check_plane_surface()
4361 plane_state->color_plane[0].offset = offset; in i9xx_check_plane_surface()
4362 plane_state->color_plane[0].x = src_x; in i9xx_check_plane_surface()
4363 plane_state->color_plane[0].y = src_y; in i9xx_check_plane_surface()
4370 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i9xx_plane_has_windowing()
4371 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_has_windowing()
4388 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in i9xx_plane_check()
4395 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, in i9xx_plane_check()
4396 &crtc_state->uapi, in i9xx_plane_check()
4408 if (!plane_state->uapi.visible) in i9xx_plane_check()
4415 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); in i9xx_plane_check()
4424 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i9xx_update_plane()
4425 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_update_plane()
4427 int x = plane_state->color_plane[0].x; in i9xx_update_plane()
4428 int y = plane_state->color_plane[0].y; in i9xx_update_plane()
4429 int crtc_x = plane_state->uapi.dst.x1; in i9xx_update_plane()
4430 int crtc_y = plane_state->uapi.dst.y1; in i9xx_update_plane()
4431 int crtc_w = drm_rect_width(&plane_state->uapi.dst); in i9xx_update_plane()
4432 int crtc_h = drm_rect_height(&plane_state->uapi.dst); in i9xx_update_plane()
4437 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); in i9xx_update_plane()
4442 dspaddr_offset = plane_state->color_plane[0].offset; in i9xx_update_plane()
4446 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i9xx_update_plane()
4449 plane_state->color_plane[0].stride); in i9xx_update_plane()
4460 ((crtc_h - 1) << 16) | (crtc_w - 1)); in i9xx_update_plane()
4465 ((crtc_h - 1) << 16) | (crtc_w - 1)); in i9xx_update_plane()
4480 * The control register self-arms if the plane was previously in i9xx_update_plane()
4492 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i9xx_update_plane()
4498 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i9xx_disable_plane()
4499 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_disable_plane()
4509 * On pre-g4x there is no way to gamma correct the in i9xx_disable_plane()
4515 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i9xx_disable_plane()
4523 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i9xx_disable_plane()
4529 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i9xx_plane_get_hw_state()
4531 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_get_hw_state()
4538 * but that's only the case for gen2-4 which don't have any in i9xx_plane_get_hw_state()
4541 power_domain = POWER_DOMAIN_PIPE(plane->pipe); in i9xx_plane_get_hw_state()
4551 *pipe = plane->pipe; in i9xx_plane_get_hw_state()
4563 struct drm_device *dev = intel_crtc->base.dev; in skl_detach_scaler()
4567 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in skl_detach_scaler()
4569 intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0); in skl_detach_scaler()
4570 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); in skl_detach_scaler()
4571 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); in skl_detach_scaler()
4573 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in skl_detach_scaler()
4581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_detach_scalers()
4583 &crtc_state->scaler_state; in skl_detach_scalers()
4587 for (i = 0; i < intel_crtc->num_scalers; i++) { in skl_detach_scalers()
4588 if (!scaler_state->scalers[i].in_use) in skl_detach_scalers()
4611 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_plane_stride()
4612 unsigned int rotation = plane_state->hw.rotation; in skl_plane_stride()
4613 u32 stride = plane_state->color_plane[color_plane].stride; in skl_plane_stride()
4615 if (color_plane >= fb->format->num_planes) in skl_plane_stride()
4685 if (!plane_state->hw.fb->format->has_alpha) in skl_plane_ctl_alpha()
4688 switch (plane_state->hw.pixel_blend_mode) { in skl_plane_ctl_alpha()
4696 MISSING_CASE(plane_state->hw.pixel_blend_mode); in skl_plane_ctl_alpha()
4703 if (!plane_state->hw.fb->format->has_alpha) in glk_plane_color_ctl_alpha()
4706 switch (plane_state->hw.pixel_blend_mode) { in glk_plane_color_ctl_alpha()
4714 MISSING_CASE(plane_state->hw.pixel_blend_mode); in glk_plane_color_ctl_alpha()
4786 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in skl_plane_ctl_crtc()
4792 if (crtc_state->gamma_enable) in skl_plane_ctl_crtc()
4795 if (crtc_state->csc_enable) in skl_plane_ctl_crtc()
4805 to_i915(plane_state->uapi.plane->dev); in skl_plane_ctl()
4806 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_plane_ctl()
4807 unsigned int rotation = plane_state->hw.rotation; in skl_plane_ctl()
4808 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; in skl_plane_ctl()
4817 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) in skl_plane_ctl()
4820 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) in skl_plane_ctl()
4824 plane_ctl |= skl_plane_ctl_format(fb->format->format); in skl_plane_ctl()
4825 plane_ctl |= skl_plane_ctl_tiling(fb->modifier); in skl_plane_ctl()
4832 if (key->flags & I915_SET_COLORKEY_DESTINATION) in skl_plane_ctl()
4834 else if (key->flags & I915_SET_COLORKEY_SOURCE) in skl_plane_ctl()
4842 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in glk_plane_color_ctl_crtc()
4848 if (crtc_state->gamma_enable) in glk_plane_color_ctl_crtc()
4851 if (crtc_state->csc_enable) in glk_plane_color_ctl_crtc()
4861 to_i915(plane_state->uapi.plane->dev); in glk_plane_color_ctl()
4862 const struct drm_framebuffer *fb = plane_state->hw.fb; in glk_plane_color_ctl()
4863 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in glk_plane_color_ctl()
4869 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { in glk_plane_color_ctl()
4870 switch (plane_state->hw.color_encoding) { in glk_plane_color_ctl()
4882 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) in glk_plane_color_ctl()
4884 } else if (fb->format->is_yuv) { in glk_plane_color_ctl()
4917 crtc_state->mode_changed = true; in __intel_display_resume()
4922 to_intel_atomic_state(state)->skip_intermediate_wm = true; in __intel_display_resume()
4926 drm_WARN_ON(dev, ret == -EDEADLK); in __intel_display_resume()
4932 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && in gpu_reset_clobbers_display()
4933 intel_has_gpu_reset(&dev_priv->gt)); in gpu_reset_clobbers_display()
4938 struct drm_device *dev = &dev_priv->drm; in intel_prepare_reset()
4939 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; in intel_prepare_reset()
4944 if (!dev_priv->params.force_reset_modeset_test && in intel_prepare_reset()
4949 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags); in intel_prepare_reset()
4951 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET); in intel_prepare_reset()
4953 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { in intel_prepare_reset()
4954 drm_dbg_kms(&dev_priv->drm, in intel_prepare_reset()
4956 intel_gt_set_wedged(&dev_priv->gt); in intel_prepare_reset()
4961 * trample ongoing ->detect() and whatnot. in intel_prepare_reset()
4963 mutex_lock(&dev->mode_config.mutex); in intel_prepare_reset()
4967 if (ret != -EDEADLK) in intel_prepare_reset()
4979 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", in intel_prepare_reset()
4986 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", in intel_prepare_reset()
4992 dev_priv->modeset_restore_state = state; in intel_prepare_reset()
4993 state->acquire_ctx = ctx; in intel_prepare_reset()
4998 struct drm_device *dev = &dev_priv->drm; in intel_finish_reset()
4999 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; in intel_finish_reset()
5004 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags)) in intel_finish_reset()
5007 state = fetch_and_zero(&dev_priv->modeset_restore_state); in intel_finish_reset()
5016 drm_err(&dev_priv->drm, in intel_finish_reset()
5021 * so need a full re-initialization. in intel_finish_reset()
5027 spin_lock_irq(&dev_priv->irq_lock); in intel_finish_reset()
5028 if (dev_priv->display.hpd_irq_setup) in intel_finish_reset()
5029 dev_priv->display.hpd_irq_setup(dev_priv); in intel_finish_reset()
5030 spin_unlock_irq(&dev_priv->irq_lock); in intel_finish_reset()
5034 drm_err(&dev_priv->drm, in intel_finish_reset()
5044 mutex_unlock(&dev->mode_config.mutex); in intel_finish_reset()
5046 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags); in intel_finish_reset()
5051 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in icl_set_pipe_chicken()
5052 enum pipe pipe = crtc->pipe; in icl_set_pipe_chicken()
5060 * and rounding for per-pixel values 00 and 0xff in icl_set_pipe_chicken()
5075 struct drm_device *dev = crtc->base.dev; in intel_fdi_normal_train()
5077 enum pipe pipe = crtc->pipe; in intel_fdi_normal_train()
5118 struct drm_device *dev = crtc->base.dev; in ilk_fdi_link_train()
5120 enum pipe pipe = crtc->pipe; in ilk_fdi_link_train()
5125 assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder); in ilk_fdi_link_train()
5141 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); in ilk_fdi_link_train()
5164 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); in ilk_fdi_link_train()
5167 drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n"); in ilk_fdi_link_train()
5173 drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); in ilk_fdi_link_train()
5194 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); in ilk_fdi_link_train()
5199 drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n"); in ilk_fdi_link_train()
5204 drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); in ilk_fdi_link_train()
5206 drm_dbg_kms(&dev_priv->drm, "FDI train done\n"); in ilk_fdi_link_train()
5221 struct drm_device *dev = crtc->base.dev; in gen6_fdi_link_train()
5223 enum pipe pipe = crtc->pipe; in gen6_fdi_link_train()
5242 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); in gen6_fdi_link_train()
5246 /* SNB-B */ in gen6_fdi_link_train()
5280 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); in gen6_fdi_link_train()
5284 drm_dbg_kms(&dev_priv->drm, in gen6_fdi_link_train()
5294 drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); in gen6_fdi_link_train()
5303 /* SNB-B */ in gen6_fdi_link_train()
5335 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); in gen6_fdi_link_train()
5339 drm_dbg_kms(&dev_priv->drm, in gen6_fdi_link_train()
5349 drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); in gen6_fdi_link_train()
5351 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); in gen6_fdi_link_train()
5358 struct drm_device *dev = crtc->base.dev; in ivb_manual_fdi_link_train()
5360 enum pipe pipe = crtc->pipe; in ivb_manual_fdi_link_train()
5375 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n", in ivb_manual_fdi_link_train()
5398 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); in ivb_manual_fdi_link_train()
5420 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); in ivb_manual_fdi_link_train()
5426 drm_dbg_kms(&dev_priv->drm, in ivb_manual_fdi_link_train()
5434 drm_dbg_kms(&dev_priv->drm, in ivb_manual_fdi_link_train()
5458 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); in ivb_manual_fdi_link_train()
5464 drm_dbg_kms(&dev_priv->drm, in ivb_manual_fdi_link_train()
5472 drm_dbg_kms(&dev_priv->drm, in ivb_manual_fdi_link_train()
5477 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); in ivb_manual_fdi_link_train()
5482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_fdi_pll_enable()
5483 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); in ilk_fdi_pll_enable()
5484 enum pipe pipe = intel_crtc->pipe; in ilk_fdi_pll_enable()
5492 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); in ilk_fdi_pll_enable()
5519 struct drm_device *dev = intel_crtc->base.dev; in ilk_fdi_pll_disable()
5521 enum pipe pipe = intel_crtc->pipe; in ilk_fdi_pll_disable()
5549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_fdi_disable()
5550 enum pipe pipe = crtc->pipe; in ilk_fdi_disable()
5604 drm_for_each_crtc(crtc, &dev_priv->drm) { in intel_has_pending_fb_unpin()
5606 spin_lock(&crtc->commit_lock); in intel_has_pending_fb_unpin()
5607 commit = list_first_entry_or_null(&crtc->commit_list, in intel_has_pending_fb_unpin()
5610 try_wait_for_completion(&commit->cleanup_done) : true; in intel_has_pending_fb_unpin()
5611 spin_unlock(&crtc->commit_lock); in intel_has_pending_fb_unpin()
5630 mutex_lock(&dev_priv->sb_lock); in lpt_disable_iclkip()
5636 mutex_unlock(&dev_priv->sb_lock); in lpt_disable_iclkip()
5642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in lpt_program_iclkip()
5643 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in lpt_program_iclkip()
5644 int clock = crtc_state->hw.adjusted_mode.crtc_clock; in lpt_program_iclkip()
5651 * but the adjusted_mode->crtc_clock in in KHz. To get the in lpt_program_iclkip()
5663 divsel = (desired_divisor / iclk_pi_range) - 2; in lpt_program_iclkip()
5668 * out of range for the 7-bit divisor in lpt_program_iclkip()
5675 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) & in lpt_program_iclkip()
5677 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) & in lpt_program_iclkip()
5680 drm_dbg_kms(&dev_priv->drm, in lpt_program_iclkip()
5684 mutex_lock(&dev_priv->sb_lock); in lpt_program_iclkip()
5707 mutex_unlock(&dev_priv->sb_lock); in lpt_program_iclkip()
5726 mutex_lock(&dev_priv->sb_lock); in lpt_get_iclkip()
5730 mutex_unlock(&dev_priv->sb_lock); in lpt_get_iclkip()
5744 mutex_unlock(&dev_priv->sb_lock); in lpt_get_iclkip()
5755 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_pch_transcoder_set_timings()
5756 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_pch_transcoder_set_timings()
5757 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in ilk_pch_transcoder_set_timings()
5784 drm_WARN_ON(&dev_priv->drm, in cpt_set_fdi_bc_bifurcation()
5787 drm_WARN_ON(&dev_priv->drm, in cpt_set_fdi_bc_bifurcation()
5795 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n", in cpt_set_fdi_bc_bifurcation()
5803 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ivb_update_fdi_bc_bifurcation()
5804 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ivb_update_fdi_bc_bifurcation()
5806 switch (crtc->pipe) { in ivb_update_fdi_bc_bifurcation()
5810 if (crtc_state->fdi_lanes > 2) in ivb_update_fdi_bc_bifurcation()
5833 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_get_crtc_new_encoder()
5840 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { in intel_get_crtc_new_encoder()
5841 if (connector_state->crtc != &crtc->base) in intel_get_crtc_new_encoder()
5844 encoder = to_intel_encoder(connector_state->best_encoder); in intel_get_crtc_new_encoder()
5848 drm_WARN(encoder->base.dev, num_encoders != 1, in intel_get_crtc_new_encoder()
5850 num_encoders, pipe_name(crtc->pipe)); in intel_get_crtc_new_encoder()
5857 * - PCH PLLs
5858 * - FDI training & RX/TX
5859 * - update transcoder timings
5860 * - DP transcoding bits
5861 * - transcoder
5866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_pch_enable()
5867 struct drm_device *dev = crtc->base.dev; in ilk_pch_enable()
5869 enum pipe pipe = crtc->pipe; in ilk_pch_enable()
5883 dev_priv->display.fdi_link_train(crtc, crtc_state); in ilk_pch_enable()
5893 if (crtc_state->shared_dpll == in ilk_pch_enable()
5906 * get_shared_dpll unconditionally resets the pll - we need that to have in ilk_pch_enable()
5920 &crtc_state->hw.adjusted_mode; in ilk_pch_enable()
5932 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) in ilk_pch_enable()
5934 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) in ilk_pch_enable()
5937 port = intel_get_crtc_new_encoder(state, crtc_state)->port; in ilk_pch_enable()
5949 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in lpt_pch_enable()
5950 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in lpt_pch_enable()
5951 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in lpt_pch_enable()
5973 drm_err(&dev_priv->drm, in cpt_verify_modeset()
5982 * -0.5. That matches how the hardware calculates the scaling
5983 * factors (from top-left of the first pixel to bottom-right
5994 * The same behaviour is observed on pre-SKL platforms as well.
5996 * Theory behind the formula (note that we ignore sub-pixel
6002 * -0.5
6011 * -0.5
6012 * | -0.375 (initial phase)
6021 int phase = -0x8000; in skl_scaler_calc_phase()
6025 phase += (sub - 1) * 0x8000 / sub; in skl_scaler_calc_phase()
6030 * Hardware initial phase limited to [-0.5:1.5]. in skl_scaler_calc_phase()
6034 WARN_ON(phase < -0x8000 || phase > 0x18000); in skl_scaler_calc_phase()
6067 &crtc_state->scaler_state; in skl_update_scaler()
6069 to_intel_crtc(crtc_state->uapi.crtc); in skl_update_scaler()
6070 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); in skl_update_scaler()
6072 &crtc_state->hw.adjusted_mode; in skl_update_scaler()
6083 * Scaling/fitting not supported in IF-ID mode in GEN9+ in skl_update_scaler()
6088 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable && in skl_update_scaler()
6089 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { in skl_update_scaler()
6090 drm_dbg_kms(&dev_priv->drm, in skl_update_scaler()
6091 "Pipe/Plane scaling not supported with IF-ID mode\n"); in skl_update_scaler()
6092 return -EINVAL; in skl_update_scaler()
6097 * - free scaler binded to this plane/crtc in skl_update_scaler()
6098 * - in order to do this, update crtc->scaler_usage in skl_update_scaler()
6102 * update to free the scaler is done in plane/panel-fit programming. in skl_update_scaler()
6103 * For this purpose crtc/plane_state->scaler_id isn't reset here. in skl_update_scaler()
6107 scaler_state->scaler_users &= ~(1 << scaler_user); in skl_update_scaler()
6108 scaler_state->scalers[*scaler_id].in_use = 0; in skl_update_scaler()
6110 drm_dbg_kms(&dev_priv->drm, in skl_update_scaler()
6113 intel_crtc->pipe, scaler_user, *scaler_id, in skl_update_scaler()
6114 scaler_state->scaler_users); in skl_update_scaler()
6115 *scaler_id = -1; in skl_update_scaler()
6122 drm_dbg_kms(&dev_priv->drm, in skl_update_scaler()
6124 return -EINVAL; in skl_update_scaler()
6136 drm_dbg_kms(&dev_priv->drm, in skl_update_scaler()
6139 intel_crtc->pipe, scaler_user, src_w, src_h, in skl_update_scaler()
6141 return -EINVAL; in skl_update_scaler()
6145 scaler_state->scaler_users |= (1 << scaler_user); in skl_update_scaler()
6146 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: " in skl_update_scaler()
6147 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", in skl_update_scaler()
6148 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, in skl_update_scaler()
6149 scaler_state->scaler_users); in skl_update_scaler()
6157 &crtc_state->hw.adjusted_mode; in skl_update_scaler_crtc()
6160 if (crtc_state->pch_pfit.enabled) { in skl_update_scaler_crtc()
6161 width = drm_rect_width(&crtc_state->pch_pfit.dst); in skl_update_scaler_crtc()
6162 height = drm_rect_height(&crtc_state->pch_pfit.dst); in skl_update_scaler_crtc()
6164 width = adjusted_mode->crtc_hdisplay; in skl_update_scaler_crtc()
6165 height = adjusted_mode->crtc_vdisplay; in skl_update_scaler_crtc()
6168 return skl_update_scaler(crtc_state, !crtc_state->hw.active, in skl_update_scaler_crtc()
6170 &crtc_state->scaler_state.scaler_id, in skl_update_scaler_crtc()
6171 crtc_state->pipe_src_w, crtc_state->pipe_src_h, in skl_update_scaler_crtc()
6173 crtc_state->pch_pfit.enabled); in skl_update_scaler_crtc()
6177 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
6182 * 0 - scaler_usage updated successfully
6183 * error - requested scaling cannot be supported or other error condition
6189 to_intel_plane(plane_state->uapi.plane); in skl_update_scaler_plane()
6190 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); in skl_update_scaler_plane()
6191 struct drm_framebuffer *fb = plane_state->hw.fb; in skl_update_scaler_plane()
6193 bool force_detach = !fb || !plane_state->uapi.visible; in skl_update_scaler_plane()
6196 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */ in skl_update_scaler_plane()
6197 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) && in skl_update_scaler_plane()
6198 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) in skl_update_scaler_plane()
6202 drm_plane_index(&intel_plane->base), in skl_update_scaler_plane()
6203 &plane_state->scaler_id, in skl_update_scaler_plane()
6204 drm_rect_width(&plane_state->uapi.src) >> 16, in skl_update_scaler_plane()
6205 drm_rect_height(&plane_state->uapi.src) >> 16, in skl_update_scaler_plane()
6206 drm_rect_width(&plane_state->uapi.dst), in skl_update_scaler_plane()
6207 drm_rect_height(&plane_state->uapi.dst), in skl_update_scaler_plane()
6208 fb ? fb->format : NULL, in skl_update_scaler_plane()
6209 fb ? fb->modifier : 0, in skl_update_scaler_plane()
6212 if (ret || plane_state->scaler_id < 0) in skl_update_scaler_plane()
6216 if (plane_state->ckey.flags) { in skl_update_scaler_plane()
6217 drm_dbg_kms(&dev_priv->drm, in skl_update_scaler_plane()
6219 intel_plane->base.base.id, in skl_update_scaler_plane()
6220 intel_plane->base.name); in skl_update_scaler_plane()
6221 return -EINVAL; in skl_update_scaler_plane()
6225 switch (fb->format->format) { in skl_update_scaler_plane()
6259 drm_dbg_kms(&dev_priv->drm, in skl_update_scaler_plane()
6261 intel_plane->base.base.id, intel_plane->base.name, in skl_update_scaler_plane()
6262 fb->base.id, fb->format->format); in skl_update_scaler_plane()
6263 return -EINVAL; in skl_update_scaler_plane()
6271 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in skl_scaler_disable()
6274 for (i = 0; i < crtc->num_scalers; i++) in skl_scaler_disable()
6280 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_pfit_enable()
6281 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in skl_pfit_enable()
6283 &crtc_state->scaler_state; in skl_pfit_enable()
6285 .x2 = crtc_state->pipe_src_w << 16, in skl_pfit_enable()
6286 .y2 = crtc_state->pipe_src_h << 16, in skl_pfit_enable()
6288 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; in skl_pfit_enable()
6290 enum pipe pipe = crtc->pipe; in skl_pfit_enable()
6293 int x = dst->x1; in skl_pfit_enable()
6294 int y = dst->y1; in skl_pfit_enable()
6299 if (!crtc_state->pch_pfit.enabled) in skl_pfit_enable()
6302 if (drm_WARN_ON(&dev_priv->drm, in skl_pfit_enable()
6303 crtc_state->scaler_state.scaler_id < 0)) in skl_pfit_enable()
6312 id = scaler_state->scaler_id; in skl_pfit_enable()
6314 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in skl_pfit_enable()
6317 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); in skl_pfit_enable()
6327 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in skl_pfit_enable()
6332 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_pfit_enable()
6333 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_pfit_enable()
6334 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; in ilk_pfit_enable()
6335 enum pipe pipe = crtc->pipe; in ilk_pfit_enable()
6338 int x = dst->x1; in ilk_pfit_enable()
6339 int y = dst->y1; in ilk_pfit_enable()
6341 if (!crtc_state->pch_pfit.enabled) in ilk_pfit_enable()
6344 /* Force use of hard-coded filter coefficients in ilk_pfit_enable()
6345 * as some pre-programmed values are broken, in ilk_pfit_enable()
6360 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_enable_ips()
6361 struct drm_device *dev = crtc->base.dev; in hsw_enable_ips()
6364 if (!crtc_state->ips_enabled) in hsw_enable_ips()
6372 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); in hsw_enable_ips()
6390 drm_err(&dev_priv->drm, in hsw_enable_ips()
6397 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_disable_ips()
6398 struct drm_device *dev = crtc->base.dev; in hsw_disable_ips()
6401 if (!crtc_state->ips_enabled) in hsw_disable_ips()
6413 drm_err(&dev_priv->drm, in hsw_disable_ips()
6421 intel_wait_for_vblank(dev_priv, crtc->pipe); in hsw_disable_ips()
6426 if (intel_crtc->overlay) in intel_crtc_dpms_overlay_disable()
6427 (void) intel_overlay_switch_off(intel_crtc->overlay); in intel_crtc_dpms_overlay_disable()
6437 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); in hsw_pre_update_disable_ips()
6438 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_pre_update_disable_ips()
6440 if (!old_crtc_state->ips_enabled) in hsw_pre_update_disable_ips()
6453 (new_crtc_state->uapi.color_mgmt_changed || in hsw_pre_update_disable_ips()
6454 new_crtc_state->update_pipe) && in hsw_pre_update_disable_ips()
6455 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) in hsw_pre_update_disable_ips()
6458 return !new_crtc_state->ips_enabled; in hsw_pre_update_disable_ips()
6464 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); in hsw_post_update_enable_ips()
6465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_post_update_enable_ips()
6467 if (!new_crtc_state->ips_enabled) in hsw_post_update_enable_ips()
6477 * Re-enable IPS after the LUT has been programmed. in hsw_post_update_enable_ips()
6480 (new_crtc_state->uapi.color_mgmt_changed || in hsw_post_update_enable_ips()
6481 new_crtc_state->update_pipe) && in hsw_post_update_enable_ips()
6482 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) in hsw_post_update_enable_ips()
6489 if (new_crtc_state->update_pipe && old_crtc_state->inherited) in hsw_post_update_enable_ips()
6492 return !old_crtc_state->ips_enabled; in hsw_post_update_enable_ips()
6497 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in needs_nv12_wa()
6499 if (!crtc_state->nv12_planes) in needs_nv12_wa()
6511 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in needs_scalerclk_wa()
6514 if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11)) in needs_scalerclk_wa()
6523 return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) && in planes_enabling()
6524 new_crtc_state->active_planes; in planes_enabling()
6530 return old_crtc_state->active_planes && in planes_disabling()
6531 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state)); in planes_disabling()
6537 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_post_plane_update()
6542 enum pipe pipe = crtc->pipe; in intel_post_plane_update()
6544 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); in intel_post_plane_update()
6546 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) in intel_post_plane_update()
6566 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_pre_plane_update()
6571 enum pipe pipe = crtc->pipe; in intel_pre_plane_update()
6591 * are blocked if the memory self-refresh mode is active at that in intel_pre_plane_update()
6593 * first the self-refresh mode. The self-refresh enable bit in turn in intel_pre_plane_update()
6596 * wait-for-vblank between disabling the plane and the pipe. in intel_pre_plane_update()
6598 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && in intel_pre_plane_update()
6599 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) in intel_pre_plane_update()
6604 * one frame before enabling scaling. LP watermarks can be re-enabled in intel_pre_plane_update()
6609 if (old_crtc_state->hw.active && in intel_pre_plane_update()
6610 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) in intel_pre_plane_update()
6615 * pre-vblank watermark programming here. in intel_pre_plane_update()
6620 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these in intel_pre_plane_update()
6621 * will be the intermediate values that are safe for both pre- and in intel_pre_plane_update()
6622 * post- vblank; when vblank happens, the 'active' values will be set in intel_pre_plane_update()
6632 if (dev_priv->display.initial_watermarks) in intel_pre_plane_update()
6633 dev_priv->display.initial_watermarks(state, crtc); in intel_pre_plane_update()
6634 else if (new_crtc_state->update_wm_pre) in intel_pre_plane_update()
6653 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_disable_planes()
6656 unsigned int update_mask = new_crtc_state->update_planes; in intel_crtc_disable_planes()
6665 if (crtc->pipe != plane->pipe || in intel_crtc_disable_planes()
6666 !(update_mask & BIT(plane->id))) in intel_crtc_disable_planes()
6671 if (old_plane_state->uapi.visible) in intel_crtc_disable_planes()
6672 fb_bits |= plane->frontbuffer_bit; in intel_crtc_disable_planes()
6679 * intel_connector_primary_encoder - get the primary encoder for a connector
6683 * all connectors to their encoder, except for DP-MST connectors which have
6684 * both a virtual and a primary encoder. These DP-MST primary encoders can be
6685 * pointed to by as many DP-MST connectors as there are pipes.
6692 if (connector->mst_port) in intel_connector_primary_encoder()
6693 return &dp_to_dig_port(connector->mst_port)->base; in intel_connector_primary_encoder()
6696 drm_WARN_ON(connector->base.dev, !encoder); in intel_connector_primary_encoder()
6707 for_each_new_connector_in_state(&state->base, connector, new_conn_state, in intel_encoders_update_prepare()
6718 if (!encoder->update_prepare) in intel_encoders_update_prepare()
6721 crtc = new_conn_state->crtc ? in intel_encoders_update_prepare()
6722 to_intel_crtc(new_conn_state->crtc) : NULL; in intel_encoders_update_prepare()
6723 encoder->update_prepare(state, encoder, crtc); in intel_encoders_update_prepare()
6733 for_each_new_connector_in_state(&state->base, connector, new_conn_state, in intel_encoders_update_complete()
6744 if (!encoder->update_complete) in intel_encoders_update_complete()
6747 crtc = new_conn_state->crtc ? in intel_encoders_update_complete()
6748 to_intel_crtc(new_conn_state->crtc) : NULL; in intel_encoders_update_complete()
6749 encoder->update_complete(state, encoder, crtc); in intel_encoders_update_complete()
6762 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in intel_encoders_pre_pll_enable()
6764 to_intel_encoder(conn_state->best_encoder); in intel_encoders_pre_pll_enable()
6766 if (conn_state->crtc != &crtc->base) in intel_encoders_pre_pll_enable()
6769 if (encoder->pre_pll_enable) in intel_encoders_pre_pll_enable()
6770 encoder->pre_pll_enable(state, encoder, in intel_encoders_pre_pll_enable()
6784 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in intel_encoders_pre_enable()
6786 to_intel_encoder(conn_state->best_encoder); in intel_encoders_pre_enable()
6788 if (conn_state->crtc != &crtc->base) in intel_encoders_pre_enable()
6791 if (encoder->pre_enable) in intel_encoders_pre_enable()
6792 encoder->pre_enable(state, encoder, in intel_encoders_pre_enable()
6806 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in intel_encoders_enable()
6808 to_intel_encoder(conn_state->best_encoder); in intel_encoders_enable()
6810 if (conn_state->crtc != &crtc->base) in intel_encoders_enable()
6813 if (encoder->enable) in intel_encoders_enable()
6814 encoder->enable(state, encoder, in intel_encoders_enable()
6829 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { in intel_encoders_disable()
6831 to_intel_encoder(old_conn_state->best_encoder); in intel_encoders_disable()
6833 if (old_conn_state->crtc != &crtc->base) in intel_encoders_disable()
6837 if (encoder->disable) in intel_encoders_disable()
6838 encoder->disable(state, encoder, in intel_encoders_disable()
6852 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { in intel_encoders_post_disable()
6854 to_intel_encoder(old_conn_state->best_encoder); in intel_encoders_post_disable()
6856 if (old_conn_state->crtc != &crtc->base) in intel_encoders_post_disable()
6859 if (encoder->post_disable) in intel_encoders_post_disable()
6860 encoder->post_disable(state, encoder, in intel_encoders_post_disable()
6874 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { in intel_encoders_post_pll_disable()
6876 to_intel_encoder(old_conn_state->best_encoder); in intel_encoders_post_pll_disable()
6878 if (old_conn_state->crtc != &crtc->base) in intel_encoders_post_pll_disable()
6881 if (encoder->post_pll_disable) in intel_encoders_post_pll_disable()
6882 encoder->post_pll_disable(state, encoder, in intel_encoders_post_pll_disable()
6896 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in intel_encoders_update_pipe()
6898 to_intel_encoder(conn_state->best_encoder); in intel_encoders_update_pipe()
6900 if (conn_state->crtc != &crtc->base) in intel_encoders_update_pipe()
6903 if (encoder->update_pipe) in intel_encoders_update_pipe()
6904 encoder->update_pipe(state, encoder, in intel_encoders_update_pipe()
6911 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_disable_primary_plane()
6912 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in intel_disable_primary_plane()
6914 plane->disable_plane(plane, crtc_state); in intel_disable_primary_plane()
6922 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_crtc_enable()
6923 enum pipe pipe = crtc->pipe; in ilk_crtc_enable()
6925 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) in ilk_crtc_enable()
6941 if (new_crtc_state->has_pch_encoder) in ilk_crtc_enable()
6950 if (new_crtc_state->has_pch_encoder) in ilk_crtc_enable()
6952 &new_crtc_state->fdi_m_n, NULL); in ilk_crtc_enable()
6956 crtc->active = true; in ilk_crtc_enable()
6960 if (new_crtc_state->has_pch_encoder) { in ilk_crtc_enable()
6981 if (dev_priv->display.initial_watermarks) in ilk_crtc_enable()
6982 dev_priv->display.initial_watermarks(state, crtc); in ilk_crtc_enable()
6985 if (new_crtc_state->has_pch_encoder) in ilk_crtc_enable()
7001 if (new_crtc_state->has_pch_encoder) { in ilk_crtc_enable()
7012 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; in hsw_crtc_supports_ips()
7031 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in icl_pipe_mbus_enable()
7032 enum pipe pipe = crtc->pipe; in icl_pipe_mbus_enable()
7050 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_set_linetime_wm()
7051 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_set_linetime_wm()
7053 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), in hsw_set_linetime_wm()
7054 HSW_LINETIME(crtc_state->linetime) | in hsw_set_linetime_wm()
7055 HSW_IPS_LINETIME(crtc_state->ips_linetime)); in hsw_set_linetime_wm()
7060 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_set_frame_start_delay()
7061 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_set_frame_start_delay()
7062 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); in hsw_set_frame_start_delay()
7076 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_crtc_enable()
7077 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; in hsw_crtc_enable()
7078 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; in hsw_crtc_enable()
7081 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) in hsw_crtc_enable()
7086 if (new_crtc_state->shared_dpll) in hsw_crtc_enable()
7099 new_crtc_state->pixel_multiplier - 1); in hsw_crtc_enable()
7101 if (new_crtc_state->has_pch_encoder) in hsw_crtc_enable()
7103 &new_crtc_state->fdi_m_n, NULL); in hsw_crtc_enable()
7113 crtc->active = true; in hsw_crtc_enable()
7117 new_crtc_state->pch_pfit.enabled; in hsw_crtc_enable()
7141 if (dev_priv->display.initial_watermarks) in hsw_crtc_enable()
7142 dev_priv->display.initial_watermarks(state, crtc); in hsw_crtc_enable()
7156 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; in hsw_crtc_enable()
7165 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in ilk_pfit_disable()
7166 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_pfit_disable()
7167 enum pipe pipe = crtc->pipe; in ilk_pfit_disable()
7171 if (!old_crtc_state->pch_pfit.enabled) in ilk_pfit_disable()
7184 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_crtc_disable()
7185 enum pipe pipe = crtc->pipe; in ilk_crtc_disable()
7203 if (old_crtc_state->has_pch_encoder) in ilk_crtc_disable()
7208 if (old_crtc_state->has_pch_encoder) { in ilk_crtc_disable()
7241 * Need care with mst->ddi interactions. in hsw_crtc_disable()
7249 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_pfit_enable()
7250 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_pfit_enable()
7252 if (!crtc_state->gmch_pfit.control) in i9xx_pfit_enable()
7259 drm_WARN_ON(&dev_priv->drm, in i9xx_pfit_enable()
7261 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_pfit_enable()
7264 crtc_state->gmch_pfit.pgm_ratios); in i9xx_pfit_enable()
7265 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); in i9xx_pfit_enable()
7269 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); in i9xx_pfit_enable()
7301 return (enum phy)port - 1; in intel_port_to_phy()
7314 return port - PORT_D; in intel_port_to_tc()
7316 return port - PORT_C; in intel_port_to_tc()
7349 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_aux_power_domain()
7350 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); in intel_aux_power_domain()
7353 dig_port->tc_mode == TC_PORT_TBT_ALT) { in intel_aux_power_domain()
7354 switch (dig_port->aux_ch) { in intel_aux_power_domain()
7370 MISSING_CASE(dig_port->aux_ch); in intel_aux_power_domain()
7375 return intel_legacy_aux_to_power_domain(dig_port->aux_ch); in intel_aux_power_domain()
7412 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in get_crtc_power_domains()
7413 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in get_crtc_power_domains()
7415 enum pipe pipe = crtc->pipe; in get_crtc_power_domains()
7417 enum transcoder transcoder = crtc_state->cpu_transcoder; in get_crtc_power_domains()
7419 if (!crtc_state->hw.active) in get_crtc_power_domains()
7424 if (crtc_state->pch_pfit.enabled || in get_crtc_power_domains()
7425 crtc_state->pch_pfit.force_thru) in get_crtc_power_domains()
7428 drm_for_each_encoder_mask(encoder, &dev_priv->drm, in get_crtc_power_domains()
7429 crtc_state->uapi.encoder_mask) { in get_crtc_power_domains()
7432 mask |= BIT_ULL(intel_encoder->power_domain); in get_crtc_power_domains()
7435 if (HAS_DDI(dev_priv) && crtc_state->has_audio) in get_crtc_power_domains()
7438 if (crtc_state->shared_dpll) in get_crtc_power_domains()
7447 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in modeset_get_crtc_power_domains()
7448 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in modeset_get_crtc_power_domains()
7452 old_domains = crtc->enabled_power_domains; in modeset_get_crtc_power_domains()
7453 crtc->enabled_power_domains = new_domains = in modeset_get_crtc_power_domains()
7478 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in valleyview_crtc_enable()
7479 enum pipe pipe = crtc->pipe; in valleyview_crtc_enable()
7481 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) in valleyview_crtc_enable()
7497 crtc->active = true; in valleyview_crtc_enable()
7520 dev_priv->display.initial_watermarks(state, crtc); in valleyview_crtc_enable()
7530 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_set_pll_dividers()
7531 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_set_pll_dividers()
7533 intel_de_write(dev_priv, FP0(crtc->pipe), in i9xx_set_pll_dividers()
7534 crtc_state->dpll_hw_state.fp0); in i9xx_set_pll_dividers()
7535 intel_de_write(dev_priv, FP1(crtc->pipe), in i9xx_set_pll_dividers()
7536 crtc_state->dpll_hw_state.fp1); in i9xx_set_pll_dividers()
7544 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_crtc_enable()
7545 enum pipe pipe = crtc->pipe; in i9xx_crtc_enable()
7547 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) in i9xx_crtc_enable()
7560 crtc->active = true; in i9xx_crtc_enable()
7576 if (dev_priv->display.initial_watermarks) in i9xx_crtc_enable()
7577 dev_priv->display.initial_watermarks(state, crtc); in i9xx_crtc_enable()
7593 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in i9xx_pfit_disable()
7594 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_pfit_disable()
7596 if (!old_crtc_state->gmch_pfit.control) in i9xx_pfit_disable()
7599 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder); in i9xx_pfit_disable()
7601 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", in i9xx_pfit_disable()
7611 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_crtc_disable()
7612 enum pipe pipe = crtc->pipe; in i9xx_crtc_disable()
7645 if (!dev_priv->display.initial_watermarks) in i9xx_crtc_disable()
7657 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_disable_noatomic()
7659 to_intel_bw_state(dev_priv->bw_obj.state); in intel_crtc_disable_noatomic()
7661 to_intel_cdclk_state(dev_priv->cdclk.obj.state); in intel_crtc_disable_noatomic()
7663 to_intel_dbuf_state(dev_priv->dbuf.obj.state); in intel_crtc_disable_noatomic()
7665 to_intel_crtc_state(crtc->base.state); in intel_crtc_disable_noatomic()
7670 enum pipe pipe = crtc->pipe; in intel_crtc_disable_noatomic()
7674 if (!crtc_state->hw.active) in intel_crtc_disable_noatomic()
7677 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { in intel_crtc_disable_noatomic()
7679 to_intel_plane_state(plane->base.state); in intel_crtc_disable_noatomic()
7681 if (plane_state->uapi.visible) in intel_crtc_disable_noatomic()
7685 state = drm_atomic_state_alloc(&dev_priv->drm); in intel_crtc_disable_noatomic()
7687 drm_dbg_kms(&dev_priv->drm, in intel_crtc_disable_noatomic()
7689 crtc->base.base.id, crtc->base.name); in intel_crtc_disable_noatomic()
7693 state->acquire_ctx = ctx; in intel_crtc_disable_noatomic()
7695 /* Everything's already locked, -EDEADLK can't happen. */ in intel_crtc_disable_noatomic()
7697 ret = drm_atomic_add_affected_connectors(state, &crtc->base); in intel_crtc_disable_noatomic()
7699 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); in intel_crtc_disable_noatomic()
7701 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc); in intel_crtc_disable_noatomic()
7705 drm_dbg_kms(&dev_priv->drm, in intel_crtc_disable_noatomic()
7707 crtc->base.base.id, crtc->base.name); in intel_crtc_disable_noatomic()
7709 crtc->active = false; in intel_crtc_disable_noatomic()
7710 crtc->base.enabled = false; in intel_crtc_disable_noatomic()
7712 drm_WARN_ON(&dev_priv->drm, in intel_crtc_disable_noatomic()
7713 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); in intel_crtc_disable_noatomic()
7714 crtc_state->uapi.active = false; in intel_crtc_disable_noatomic()
7715 crtc_state->uapi.connector_mask = 0; in intel_crtc_disable_noatomic()
7716 crtc_state->uapi.encoder_mask = 0; in intel_crtc_disable_noatomic()
7718 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); in intel_crtc_disable_noatomic()
7720 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) in intel_crtc_disable_noatomic()
7721 encoder->base.crtc = NULL; in intel_crtc_disable_noatomic()
7727 domains = crtc->enabled_power_domains; in intel_crtc_disable_noatomic()
7730 crtc->enabled_power_domains = 0; in intel_crtc_disable_noatomic()
7732 dev_priv->active_pipes &= ~BIT(pipe); in intel_crtc_disable_noatomic()
7733 cdclk_state->min_cdclk[pipe] = 0; in intel_crtc_disable_noatomic()
7734 cdclk_state->min_voltage_level[pipe] = 0; in intel_crtc_disable_noatomic()
7735 cdclk_state->active_pipes &= ~BIT(pipe); in intel_crtc_disable_noatomic()
7737 dbuf_state->active_pipes &= ~BIT(pipe); in intel_crtc_disable_noatomic()
7739 bw_state->data_rate[pipe] = 0; in intel_crtc_disable_noatomic()
7740 bw_state->num_active_planes[pipe] = 0; in intel_crtc_disable_noatomic()
7756 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", in intel_display_suspend()
7759 dev_priv->modeset_restore_state = state; in intel_display_suspend()
7776 struct intel_connector *connector = to_intel_connector(conn_state->connector); in intel_connector_verify_state()
7777 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_connector_verify_state()
7779 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", in intel_connector_verify_state()
7780 connector->base.base.id, connector->base.name); in intel_connector_verify_state()
7782 if (connector->get_hw_state(connector)) { in intel_connector_verify_state()
7791 I915_STATE_WARN(!crtc_state->hw.active, in intel_connector_verify_state()
7794 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) in intel_connector_verify_state()
7797 I915_STATE_WARN(conn_state->best_encoder != &encoder->base, in intel_connector_verify_state()
7800 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, in intel_connector_verify_state()
7803 I915_STATE_WARN(crtc_state && crtc_state->hw.active, in intel_connector_verify_state()
7805 I915_STATE_WARN(!crtc_state && conn_state->best_encoder, in intel_connector_verify_state()
7812 if (crtc_state->hw.enable && crtc_state->has_pch_encoder) in pipe_required_fdi_lanes()
7813 return crtc_state->fdi_lanes; in pipe_required_fdi_lanes()
7822 struct drm_atomic_state *state = pipe_config->uapi.state; in ilk_check_fdi_lanes()
7826 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
7828 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
7829 if (pipe_config->fdi_lanes > 4) { in ilk_check_fdi_lanes()
7830 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
7832 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
7833 return -EINVAL; in ilk_check_fdi_lanes()
7837 if (pipe_config->fdi_lanes > 2) { in ilk_check_fdi_lanes()
7838 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
7840 pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
7841 return -EINVAL; in ilk_check_fdi_lanes()
7855 if (pipe_config->fdi_lanes <= 2) in ilk_check_fdi_lanes()
7865 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
7867 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
7868 return -EINVAL; in ilk_check_fdi_lanes()
7872 if (pipe_config->fdi_lanes > 2) { in ilk_check_fdi_lanes()
7873 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
7875 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
7876 return -EINVAL; in ilk_check_fdi_lanes()
7886 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
7888 return -EINVAL; in ilk_check_fdi_lanes()
7900 struct drm_device *dev = intel_crtc->base.dev; in ilk_fdi_compute_config()
7902 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in ilk_fdi_compute_config()
7916 fdi_dotclock = adjusted_mode->crtc_clock; in ilk_fdi_compute_config()
7919 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
7921 pipe_config->fdi_lanes = lane; in ilk_fdi_compute_config()
7923 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ilk_fdi_compute_config()
7924 link_bw, &pipe_config->fdi_m_n, false, false); in ilk_fdi_compute_config()
7926 ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); in ilk_fdi_compute_config()
7927 if (ret == -EDEADLK) in ilk_fdi_compute_config()
7930 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ilk_fdi_compute_config()
7931 pipe_config->pipe_bpp -= 2*3; in ilk_fdi_compute_config()
7932 drm_dbg_kms(&i915->drm, in ilk_fdi_compute_config()
7934 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
7936 pipe_config->bw_constrained = true; in ilk_fdi_compute_config()
7949 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_crtc_state_ips_capable()
7950 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_crtc_state_ips_capable()
7956 if (!dev_priv->params.enable_ips) in hsw_crtc_state_ips_capable()
7959 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
7970 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100) in hsw_crtc_state_ips_capable()
7979 to_i915(crtc_state->uapi.crtc->dev); in hsw_compute_ips_config()
7981 to_intel_atomic_state(crtc_state->uapi.state); in hsw_compute_ips_config()
7983 crtc_state->ips_enabled = false; in hsw_compute_ips_config()
7994 if (crtc_state->crc_enabled) in hsw_compute_ips_config()
7998 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))) in hsw_compute_ips_config()
8009 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_compute_ips_config()
8013 crtc_state->ips_enabled = true; in hsw_compute_ips_config()
8020 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_supports_double_wide()
8024 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); in intel_crtc_supports_double_wide()
8029 u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock; in ilk_pipe_pixel_rate()
8033 * We only use IF-ID interlacing. If we ever use in ilk_pipe_pixel_rate()
8034 * PF-ID we'll need to adjust the pixel_rate here. in ilk_pipe_pixel_rate()
8037 if (!crtc_state->pch_pfit.enabled) in ilk_pipe_pixel_rate()
8040 pipe_w = crtc_state->pipe_src_w; in ilk_pipe_pixel_rate()
8041 pipe_h = crtc_state->pipe_src_h; in ilk_pipe_pixel_rate()
8043 pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst); in ilk_pipe_pixel_rate()
8044 pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst); in ilk_pipe_pixel_rate()
8051 if (drm_WARN_ON(crtc_state->uapi.crtc->dev, in ilk_pipe_pixel_rate()
8061 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_crtc_compute_pixel_rate()
8065 crtc_state->pixel_rate = in intel_crtc_compute_pixel_rate()
8066 crtc_state->hw.adjusted_mode.crtc_clock; in intel_crtc_compute_pixel_rate()
8068 crtc_state->pixel_rate = in intel_crtc_compute_pixel_rate()
8075 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_compute_config()
8076 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_crtc_compute_config()
8077 int clock_limit = dev_priv->max_dotclk_freq; in intel_crtc_compute_config()
8080 clock_limit = dev_priv->max_cdclk_freq * 9 / 10; in intel_crtc_compute_config()
8087 adjusted_mode->crtc_clock > clock_limit) { in intel_crtc_compute_config()
8088 clock_limit = dev_priv->max_dotclk_freq; in intel_crtc_compute_config()
8089 pipe_config->double_wide = true; in intel_crtc_compute_config()
8093 if (adjusted_mode->crtc_clock > clock_limit) { in intel_crtc_compute_config()
8094 drm_dbg_kms(&dev_priv->drm, in intel_crtc_compute_config()
8096 adjusted_mode->crtc_clock, clock_limit, in intel_crtc_compute_config()
8097 yesno(pipe_config->double_wide)); in intel_crtc_compute_config()
8098 return -EINVAL; in intel_crtc_compute_config()
8101 if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || in intel_crtc_compute_config()
8102 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) && in intel_crtc_compute_config()
8103 pipe_config->hw.ctm) { in intel_crtc_compute_config()
8106 * for output conversion from RGB->YCBCR. So if CTM is already in intel_crtc_compute_config()
8109 drm_dbg_kms(&dev_priv->drm, in intel_crtc_compute_config()
8111 return -EINVAL; in intel_crtc_compute_config()
8116 * - DVO ganged mode in intel_crtc_compute_config()
8117 * - LVDS dual channel mode in intel_crtc_compute_config()
8118 * - Double wide pipe in intel_crtc_compute_config()
8120 if (pipe_config->pipe_src_w & 1) { in intel_crtc_compute_config()
8121 if (pipe_config->double_wide) { in intel_crtc_compute_config()
8122 drm_dbg_kms(&dev_priv->drm, in intel_crtc_compute_config()
8124 return -EINVAL; in intel_crtc_compute_config()
8129 drm_dbg_kms(&dev_priv->drm, in intel_crtc_compute_config()
8131 return -EINVAL; in intel_crtc_compute_config()
8139 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) in intel_crtc_compute_config()
8140 return -EINVAL; in intel_crtc_compute_config()
8144 if (pipe_config->has_pch_encoder) in intel_crtc_compute_config()
8191 m_n->tu = 64; in intel_link_compute_m_n()
8194 &m_n->gmch_m, &m_n->gmch_n, in intel_link_compute_m_n()
8198 &m_n->link_m, &m_n->link_n, in intel_link_compute_m_n()
8215 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { in intel_panel_sanitize_ssc()
8216 drm_dbg_kms(&dev_priv->drm, in intel_panel_sanitize_ssc()
8219 enableddisabled(dev_priv->vbt.lvds_use_ssc)); in intel_panel_sanitize_ssc()
8220 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; in intel_panel_sanitize_ssc()
8227 if (dev_priv->params.panel_use_ssc >= 0) in intel_panel_use_ssc()
8228 return dev_priv->params.panel_use_ssc != 0; in intel_panel_use_ssc()
8229 return dev_priv->vbt.lvds_use_ssc in intel_panel_use_ssc()
8230 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); in intel_panel_use_ssc()
8235 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
8240 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
8247 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_update_pll_dividers()
8251 fp = pnv_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
8255 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
8260 crtc_state->dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers()
8264 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
8266 crtc_state->dpll_hw_state.fp1 = fp; in i9xx_update_pll_dividers()
8302 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_pch_transcoder_set_m_n()
8303 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_pch_transcoder_set_m_n()
8304 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_set_m_n()
8307 TU_SIZE(m_n->tu) | m_n->gmch_m); in intel_pch_transcoder_set_m_n()
8308 intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); in intel_pch_transcoder_set_m_n()
8309 intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m); in intel_pch_transcoder_set_m_n()
8310 intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n); in intel_pch_transcoder_set_m_n()
8330 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_cpu_transcoder_set_m_n()
8331 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_cpu_transcoder_set_m_n()
8332 enum pipe pipe = crtc->pipe; in intel_cpu_transcoder_set_m_n()
8333 enum transcoder transcoder = crtc_state->cpu_transcoder; in intel_cpu_transcoder_set_m_n()
8337 TU_SIZE(m_n->tu) | m_n->gmch_m); in intel_cpu_transcoder_set_m_n()
8339 m_n->gmch_n); in intel_cpu_transcoder_set_m_n()
8341 m_n->link_m); in intel_cpu_transcoder_set_m_n()
8343 m_n->link_n); in intel_cpu_transcoder_set_m_n()
8348 if (m2_n2 && crtc_state->has_drrs && in intel_cpu_transcoder_set_m_n()
8351 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); in intel_cpu_transcoder_set_m_n()
8353 m2_n2->gmch_n); in intel_cpu_transcoder_set_m_n()
8355 m2_n2->link_m); in intel_cpu_transcoder_set_m_n()
8357 m2_n2->link_n); in intel_cpu_transcoder_set_m_n()
8361 TU_SIZE(m_n->tu) | m_n->gmch_m); in intel_cpu_transcoder_set_m_n()
8362 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n); in intel_cpu_transcoder_set_m_n()
8363 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m); in intel_cpu_transcoder_set_m_n()
8364 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n); in intel_cpu_transcoder_set_m_n()
8371 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_dp_set_m_n()
8374 dp_m_n = &crtc_state->dp_m_n; in intel_dp_set_m_n()
8375 dp_m2_n2 = &crtc_state->dp_m2_n2; in intel_dp_set_m_n()
8382 dp_m_n = &crtc_state->dp_m2_n2; in intel_dp_set_m_n()
8384 drm_err(&i915->drm, "Unsupported divider value\n"); in intel_dp_set_m_n()
8388 if (crtc_state->has_pch_encoder) in intel_dp_set_m_n()
8389 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n); in intel_dp_set_m_n()
8397 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
8399 if (crtc->pipe != PIPE_A) in vlv_compute_dpll()
8400 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
8404 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
8407 pipe_config->dpll_hw_state.dpll_md = in vlv_compute_dpll()
8408 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in vlv_compute_dpll()
8414 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
8416 if (crtc->pipe != PIPE_A) in chv_compute_dpll()
8417 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
8421 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
8423 pipe_config->dpll_hw_state.dpll_md = in chv_compute_dpll()
8424 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in chv_compute_dpll()
8430 struct drm_device *dev = crtc->base.dev; in vlv_prepare_pll()
8432 enum pipe pipe = crtc->pipe; in vlv_prepare_pll()
8437 /* Enable Refclk */ in vlv_prepare_pll()
8439 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); in vlv_prepare_pll()
8442 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_prepare_pll()
8447 bestn = pipe_config->dpll.n; in vlv_prepare_pll()
8448 bestm1 = pipe_config->dpll.m1; in vlv_prepare_pll()
8449 bestm2 = pipe_config->dpll.m2; in vlv_prepare_pll()
8450 bestp1 = pipe_config->dpll.p1; in vlv_prepare_pll()
8451 bestp2 = pipe_config->dpll.p2; in vlv_prepare_pll()
8488 if (pipe_config->port_clock == 162000 || in vlv_prepare_pll()
8529 struct drm_device *dev = crtc->base.dev; in chv_prepare_pll()
8531 enum pipe pipe = crtc->pipe; in chv_prepare_pll()
8538 /* Enable Refclk and SSC */ in chv_prepare_pll()
8540 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
8543 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_prepare_pll()
8546 bestn = pipe_config->dpll.n; in chv_prepare_pll()
8547 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; in chv_prepare_pll()
8548 bestm1 = pipe_config->dpll.m1; in chv_prepare_pll()
8549 bestm2 = pipe_config->dpll.m2 >> 22; in chv_prepare_pll()
8550 bestp1 = pipe_config->dpll.p1; in chv_prepare_pll()
8551 bestp2 = pipe_config->dpll.p2; in chv_prepare_pll()
8552 vco = pipe_config->dpll.vco; in chv_prepare_pll()
8565 /* Feedback post-divider - m2 */ in chv_prepare_pll()
8568 /* Feedback refclk divider - n and m1 */ in chv_prepare_pll()
8632 * vlv_force_pll_on - forcibly enable just the PLL
8649 return -ENOMEM; in vlv_force_pll_on()
8651 pipe_config->cpu_transcoder = (enum transcoder)pipe; in vlv_force_pll_on()
8652 pipe_config->pixel_multiplier = 1; in vlv_force_pll_on()
8653 pipe_config->dpll = *dpll; in vlv_force_pll_on()
8671 * vlv_force_pll_off - forcibly disable just the PLL
8690 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_compute_dpll()
8692 struct dpll *clock = &crtc_state->dpll; in i9xx_compute_dpll()
8705 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
8718 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
8720 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
8722 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
8724 switch (clock->p2) { in i9xx_compute_dpll()
8741 if (crtc_state->sdvo_tv_clock) in i9xx_compute_dpll()
8750 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
8753 u32 dpll_md = (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
8755 crtc_state->dpll_hw_state.dpll_md = dpll_md; in i9xx_compute_dpll()
8763 struct drm_device *dev = crtc->base.dev; in i8xx_compute_dpll()
8766 struct dpll *clock = &crtc_state->dpll; in i8xx_compute_dpll()
8773 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
8775 if (clock->p1 == 2) in i8xx_compute_dpll()
8778 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
8779 if (clock->p2 == 4) in i8xx_compute_dpll()
8789 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." in i8xx_compute_dpll()
8806 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
8811 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_set_pipe_timings()
8812 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_set_pipe_timings()
8813 enum pipe pipe = crtc->pipe; in intel_set_pipe_timings()
8814 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_set_pipe_timings()
8815 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_set_pipe_timings()
8821 crtc_vtotal = adjusted_mode->crtc_vtotal; in intel_set_pipe_timings()
8822 crtc_vblank_end = adjusted_mode->crtc_vblank_end; in intel_set_pipe_timings()
8824 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { in intel_set_pipe_timings()
8826 crtc_vtotal -= 1; in intel_set_pipe_timings()
8827 crtc_vblank_end -= 1; in intel_set_pipe_timings()
8830 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; in intel_set_pipe_timings()
8832 vsyncshift = adjusted_mode->crtc_hsync_start - in intel_set_pipe_timings()
8833 adjusted_mode->crtc_htotal / 2; in intel_set_pipe_timings()
8835 vsyncshift += adjusted_mode->crtc_htotal; in intel_set_pipe_timings()
8843 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); in intel_set_pipe_timings()
8845 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); in intel_set_pipe_timings()
8847 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); in intel_set_pipe_timings()
8850 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); in intel_set_pipe_timings()
8852 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); in intel_set_pipe_timings()
8854 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); in intel_set_pipe_timings()
8869 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_set_pipe_src_size()
8870 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_set_pipe_src_size()
8871 enum pipe pipe = crtc->pipe; in intel_set_pipe_src_size()
8877 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1)); in intel_set_pipe_src_size()
8882 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_pipe_is_interlaced()
8883 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_pipe_is_interlaced()
8898 struct drm_device *dev = crtc->base.dev; in intel_get_pipe_timings()
8900 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_get_pipe_timings()
8904 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
8905 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
8909 pipe_config->hw.adjusted_mode.crtc_hblank_start = in intel_get_pipe_timings()
8911 pipe_config->hw.adjusted_mode.crtc_hblank_end = in intel_get_pipe_timings()
8915 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
8916 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
8919 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
8920 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
8924 pipe_config->hw.adjusted_mode.crtc_vblank_start = in intel_get_pipe_timings()
8926 pipe_config->hw.adjusted_mode.crtc_vblank_end = in intel_get_pipe_timings()
8930 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
8931 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
8934 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; in intel_get_pipe_timings()
8935 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; in intel_get_pipe_timings()
8936 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; in intel_get_pipe_timings()
8943 struct drm_device *dev = crtc->base.dev; in intel_get_pipe_src_size()
8947 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); in intel_get_pipe_src_size()
8948 pipe_config->pipe_src_h = (tmp & 0xffff) + 1; in intel_get_pipe_src_size()
8949 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_src_size()
8951 pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h; in intel_get_pipe_src_size()
8952 pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w; in intel_get_pipe_src_size()
8958 mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay; in intel_mode_from_pipe_config()
8959 mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal; in intel_mode_from_pipe_config()
8960 mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start; in intel_mode_from_pipe_config()
8961 mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end; in intel_mode_from_pipe_config()
8963 mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay; in intel_mode_from_pipe_config()
8964 mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal; in intel_mode_from_pipe_config()
8965 mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start; in intel_mode_from_pipe_config()
8966 mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end; in intel_mode_from_pipe_config()
8968 mode->flags = pipe_config->hw.adjusted_mode.flags; in intel_mode_from_pipe_config()
8969 mode->type = DRM_MODE_TYPE_DRIVER; in intel_mode_from_pipe_config()
8971 mode->clock = pipe_config->hw.adjusted_mode.crtc_clock; in intel_mode_from_pipe_config()
8978 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_set_pipeconf()
8979 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_set_pipeconf()
8986 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE; in i9xx_set_pipeconf()
8988 if (crtc_state->double_wide) in i9xx_set_pipeconf()
8995 if (crtc_state->dither && crtc_state->pipe_bpp != 30) in i9xx_set_pipeconf()
8999 switch (crtc_state->pipe_bpp) { in i9xx_set_pipeconf()
9015 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { in i9xx_set_pipeconf()
9026 crtc_state->limited_color_range) in i9xx_set_pipeconf()
9029 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); in i9xx_set_pipeconf()
9033 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); in i9xx_set_pipeconf()
9034 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); in i9xx_set_pipeconf()
9040 struct drm_device *dev = crtc->base.dev; in i8xx_crtc_compute_clock()
9043 int refclk = 48000; in i8xx_crtc_compute_clock() local
9045 memset(&crtc_state->dpll_hw_state, 0, in i8xx_crtc_compute_clock()
9046 sizeof(crtc_state->dpll_hw_state)); in i8xx_crtc_compute_clock()
9050 refclk = dev_priv->vbt.lvds_ssc_freq; in i8xx_crtc_compute_clock()
9051 drm_dbg_kms(&dev_priv->drm, in i8xx_crtc_compute_clock()
9053 refclk); in i8xx_crtc_compute_clock()
9063 if (!crtc_state->clock_set && in i8xx_crtc_compute_clock()
9064 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i8xx_crtc_compute_clock()
9065 refclk, NULL, &crtc_state->dpll)) { in i8xx_crtc_compute_clock()
9066 drm_err(&dev_priv->drm, in i8xx_crtc_compute_clock()
9068 return -EINVAL; in i8xx_crtc_compute_clock()
9079 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in g4x_crtc_compute_clock()
9081 int refclk = 96000; in g4x_crtc_compute_clock() local
9083 memset(&crtc_state->dpll_hw_state, 0, in g4x_crtc_compute_clock()
9084 sizeof(crtc_state->dpll_hw_state)); in g4x_crtc_compute_clock()
9088 refclk = dev_priv->vbt.lvds_ssc_freq; in g4x_crtc_compute_clock()
9089 drm_dbg_kms(&dev_priv->drm, in g4x_crtc_compute_clock()
9091 refclk); in g4x_crtc_compute_clock()
9108 if (!crtc_state->clock_set && in g4x_crtc_compute_clock()
9109 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
9110 refclk, NULL, &crtc_state->dpll)) { in g4x_crtc_compute_clock()
9111 drm_err(&dev_priv->drm, in g4x_crtc_compute_clock()
9113 return -EINVAL; in g4x_crtc_compute_clock()
9124 struct drm_device *dev = crtc->base.dev; in pnv_crtc_compute_clock()
9127 int refclk = 96000; in pnv_crtc_compute_clock() local
9129 memset(&crtc_state->dpll_hw_state, 0, in pnv_crtc_compute_clock()
9130 sizeof(crtc_state->dpll_hw_state)); in pnv_crtc_compute_clock()
9134 refclk = dev_priv->vbt.lvds_ssc_freq; in pnv_crtc_compute_clock()
9135 drm_dbg_kms(&dev_priv->drm, in pnv_crtc_compute_clock()
9137 refclk); in pnv_crtc_compute_clock()
9145 if (!crtc_state->clock_set && in pnv_crtc_compute_clock()
9146 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
9147 refclk, NULL, &crtc_state->dpll)) { in pnv_crtc_compute_clock()
9148 drm_err(&dev_priv->drm, in pnv_crtc_compute_clock()
9150 return -EINVAL; in pnv_crtc_compute_clock()
9161 struct drm_device *dev = crtc->base.dev; in i9xx_crtc_compute_clock()
9164 int refclk = 96000; in i9xx_crtc_compute_clock() local
9166 memset(&crtc_state->dpll_hw_state, 0, in i9xx_crtc_compute_clock()
9167 sizeof(crtc_state->dpll_hw_state)); in i9xx_crtc_compute_clock()
9171 refclk = dev_priv->vbt.lvds_ssc_freq; in i9xx_crtc_compute_clock()
9172 drm_dbg_kms(&dev_priv->drm, in i9xx_crtc_compute_clock()
9174 refclk); in i9xx_crtc_compute_clock()
9182 if (!crtc_state->clock_set && in i9xx_crtc_compute_clock()
9183 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i9xx_crtc_compute_clock()
9184 refclk, NULL, &crtc_state->dpll)) { in i9xx_crtc_compute_clock()
9185 drm_err(&dev_priv->drm, in i9xx_crtc_compute_clock()
9187 return -EINVAL; in i9xx_crtc_compute_clock()
9198 int refclk = 100000; in chv_crtc_compute_clock() local
9200 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in chv_crtc_compute_clock()
9202 memset(&crtc_state->dpll_hw_state, 0, in chv_crtc_compute_clock()
9203 sizeof(crtc_state->dpll_hw_state)); in chv_crtc_compute_clock()
9205 if (!crtc_state->clock_set && in chv_crtc_compute_clock()
9206 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
9207 refclk, NULL, &crtc_state->dpll)) { in chv_crtc_compute_clock()
9208 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); in chv_crtc_compute_clock()
9209 return -EINVAL; in chv_crtc_compute_clock()
9220 int refclk = 100000; in vlv_crtc_compute_clock() local
9222 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in vlv_crtc_compute_clock()
9224 memset(&crtc_state->dpll_hw_state, 0, in vlv_crtc_compute_clock()
9225 sizeof(crtc_state->dpll_hw_state)); in vlv_crtc_compute_clock()
9227 if (!crtc_state->clock_set && in vlv_crtc_compute_clock()
9228 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
9229 refclk, NULL, &crtc_state->dpll)) { in vlv_crtc_compute_clock()
9230 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); in vlv_crtc_compute_clock()
9231 return -EINVAL; in vlv_crtc_compute_clock()
9250 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_get_pfit_config()
9251 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_get_pfit_config()
9263 if (crtc->pipe != PIPE_B) in i9xx_get_pfit_config()
9266 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) in i9xx_get_pfit_config()
9270 crtc_state->gmch_pfit.control = tmp; in i9xx_get_pfit_config()
9271 crtc_state->gmch_pfit.pgm_ratios = in i9xx_get_pfit_config()
9278 struct drm_device *dev = crtc->base.dev; in vlv_crtc_clock_get()
9280 enum pipe pipe = crtc->pipe; in vlv_crtc_clock_get()
9283 int refclk = 100000; in vlv_crtc_clock_get() local
9286 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
9299 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
9306 struct drm_device *dev = crtc->base.dev; in i9xx_get_initial_plane_config()
9308 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in i9xx_get_initial_plane_config()
9309 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_get_initial_plane_config()
9317 if (!plane->get_hw_state(plane, &pipe)) in i9xx_get_initial_plane_config()
9320 drm_WARN_ON(dev, pipe != crtc->pipe); in i9xx_get_initial_plane_config()
9324 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); in i9xx_get_initial_plane_config()
9328 fb = &intel_fb->base; in i9xx_get_initial_plane_config()
9330 fb->dev = dev; in i9xx_get_initial_plane_config()
9336 plane_config->tiling = I915_TILING_X; in i9xx_get_initial_plane_config()
9337 fb->modifier = I915_FORMAT_MOD_X_TILED; in i9xx_get_initial_plane_config()
9341 plane_config->rotation = DRM_MODE_ROTATE_180; in i9xx_get_initial_plane_config()
9346 plane_config->rotation |= DRM_MODE_REFLECT_X; in i9xx_get_initial_plane_config()
9350 fb->format = drm_format_info(fourcc); in i9xx_get_initial_plane_config()
9356 if (plane_config->tiling) in i9xx_get_initial_plane_config()
9366 plane_config->base = base; in i9xx_get_initial_plane_config()
9369 fb->width = ((val >> 16) & 0xfff) + 1; in i9xx_get_initial_plane_config()
9370 fb->height = ((val >> 0) & 0xfff) + 1; in i9xx_get_initial_plane_config()
9373 fb->pitches[0] = val & 0xffffffc0; in i9xx_get_initial_plane_config()
9375 aligned_height = intel_fb_align_height(fb, 0, fb->height); in i9xx_get_initial_plane_config()
9377 plane_config->size = fb->pitches[0] * aligned_height; in i9xx_get_initial_plane_config()
9379 drm_dbg_kms(&dev_priv->drm, in i9xx_get_initial_plane_config()
9381 crtc->base.name, plane->base.name, fb->width, fb->height, in i9xx_get_initial_plane_config()
9382 fb->format->cpp[0] * 8, base, fb->pitches[0], in i9xx_get_initial_plane_config()
9383 plane_config->size); in i9xx_get_initial_plane_config()
9385 plane_config->fb = intel_fb; in i9xx_get_initial_plane_config()
9391 struct drm_device *dev = crtc->base.dev; in chv_crtc_clock_get()
9393 enum pipe pipe = crtc->pipe; in chv_crtc_clock_get()
9397 int refclk = 100000; in chv_crtc_clock_get() local
9400 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
9419 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
9425 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in bdw_get_pipemisc_output_format()
9428 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); in bdw_get_pipemisc_output_format()
9432 drm_WARN_ON(&dev_priv->drm, in bdw_get_pipemisc_output_format()
9445 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_get_pipe_color_config()
9446 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in i9xx_get_pipe_color_config()
9447 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_get_pipe_color_config()
9448 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_get_pipe_color_config()
9454 crtc_state->gamma_enable = true; in i9xx_get_pipe_color_config()
9458 crtc_state->csc_enable = true; in i9xx_get_pipe_color_config()
9464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_get_pipe_config()
9470 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); in i9xx_get_pipe_config()
9475 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in i9xx_get_pipe_config()
9476 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in i9xx_get_pipe_config()
9477 pipe_config->shared_dpll = NULL; in i9xx_get_pipe_config()
9481 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); in i9xx_get_pipe_config()
9489 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
9492 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
9495 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
9504 pipe_config->limited_color_range = true; in i9xx_get_pipe_config()
9506 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >> in i9xx_get_pipe_config()
9510 pipe_config->cgm_mode = intel_de_read(dev_priv, in i9xx_get_pipe_config()
9511 CGM_PIPE_MODE(crtc->pipe)); in i9xx_get_pipe_config()
9517 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; in i9xx_get_pipe_config()
9526 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) in i9xx_get_pipe_config()
9527 tmp = dev_priv->chv_dpll_md[crtc->pipe]; in i9xx_get_pipe_config()
9529 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); in i9xx_get_pipe_config()
9530 pipe_config->pixel_multiplier = in i9xx_get_pipe_config()
9533 pipe_config->dpll_hw_state.dpll_md = tmp; in i9xx_get_pipe_config()
9536 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); in i9xx_get_pipe_config()
9537 pipe_config->pixel_multiplier = in i9xx_get_pipe_config()
9542 * port and will be fixed up in the encoder->get_config in i9xx_get_pipe_config()
9544 pipe_config->pixel_multiplier = 1; in i9xx_get_pipe_config()
9546 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, in i9xx_get_pipe_config()
9547 DPLL(crtc->pipe)); in i9xx_get_pipe_config()
9549 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, in i9xx_get_pipe_config()
9550 FP0(crtc->pipe)); in i9xx_get_pipe_config()
9551 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, in i9xx_get_pipe_config()
9552 FP1(crtc->pipe)); in i9xx_get_pipe_config()
9554 /* Mask out read-only status bits. */ in i9xx_get_pipe_config()
9555 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
9572 pipe_config->hw.adjusted_mode.crtc_clock = in i9xx_get_pipe_config()
9573 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
9596 for_each_intel_encoder(&dev_priv->drm, encoder) { in ilk_init_pch_refclk()
9597 switch (encoder->type) { in ilk_init_pch_refclk()
9604 if (encoder->port == PORT_A) in ilk_init_pch_refclk()
9613 has_ck505 = dev_priv->vbt.display_clock_mode; in ilk_init_pch_refclk()
9621 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in ilk_init_pch_refclk()
9634 drm_dbg_kms(&dev_priv->drm, in ilk_init_pch_refclk()
9695 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n"); in ilk_init_pch_refclk()
9710 drm_dbg_kms(&dev_priv->drm, in ilk_init_pch_refclk()
9722 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n"); in ilk_init_pch_refclk()
9734 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n"); in ilk_init_pch_refclk()
9762 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n"); in lpt_reset_fdi_mphy()
9770 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n"); in lpt_reset_fdi_mphy()
9850 * - Sequence to enable CLKOUT_DP
9851 * - Sequence to enable CLKOUT_DP without spread
9852 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9859 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread, in lpt_enable_clkout_dp()
9862 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) && in lpt_enable_clkout_dp()
9866 mutex_lock(&dev_priv->sb_lock); in lpt_enable_clkout_dp()
9891 mutex_unlock(&dev_priv->sb_lock); in lpt_enable_clkout_dp()
9899 mutex_lock(&dev_priv->sb_lock); in lpt_disable_clkout_dp()
9917 mutex_unlock(&dev_priv->sb_lock); in lpt_disable_clkout_dp()
9934 [BEND_IDX( -5)] = 0x0025,
9935 [BEND_IDX(-10)] = 0x0125,
9936 [BEND_IDX(-15)] = 0x0125,
9937 [BEND_IDX(-20)] = 0x0225,
9938 [BEND_IDX(-25)] = 0x0225,
9939 [BEND_IDX(-30)] = 0x0325,
9940 [BEND_IDX(-35)] = 0x0325,
9941 [BEND_IDX(-40)] = 0x0425,
9942 [BEND_IDX(-45)] = 0x0425,
9943 [BEND_IDX(-50)] = 0x0525,
9948 * steps -50 to 50 inclusive, in steps of 5
9950 * change in clock period = -(steps / 10) * 5.787 ps
9957 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0)) in lpt_bend_clkout_dp()
9960 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase))) in lpt_bend_clkout_dp()
9963 mutex_lock(&dev_priv->sb_lock); in lpt_bend_clkout_dp()
9976 mutex_unlock(&dev_priv->sb_lock); in lpt_bend_clkout_dp()
10025 for_each_intel_encoder(&dev_priv->drm, encoder) { in lpt_init_pch_refclk()
10026 switch (encoder->type) { in lpt_init_pch_refclk()
10050 dev_priv->pch_ssc_use = 0; in lpt_init_pch_refclk()
10053 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n"); in lpt_init_pch_refclk()
10054 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL); in lpt_init_pch_refclk()
10058 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n"); in lpt_init_pch_refclk()
10059 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1); in lpt_init_pch_refclk()
10063 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n"); in lpt_init_pch_refclk()
10064 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2); in lpt_init_pch_refclk()
10067 if (dev_priv->pch_ssc_use) in lpt_init_pch_refclk()
10091 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_set_pipeconf()
10092 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_set_pipeconf()
10093 enum pipe pipe = crtc->pipe; in ilk_set_pipeconf()
10098 switch (crtc_state->pipe_bpp) { in ilk_set_pipeconf()
10116 if (crtc_state->dither) in ilk_set_pipeconf()
10119 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in ilk_set_pipeconf()
10128 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && in ilk_set_pipeconf()
10129 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); in ilk_set_pipeconf()
10131 if (crtc_state->limited_color_range && in ilk_set_pipeconf()
10135 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) in ilk_set_pipeconf()
10138 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); in ilk_set_pipeconf()
10148 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_set_pipeconf()
10149 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_set_pipeconf()
10150 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_set_pipeconf()
10153 if (IS_HASWELL(dev_priv) && crtc_state->dither) in hsw_set_pipeconf()
10156 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in hsw_set_pipeconf()
10162 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) in hsw_set_pipeconf()
10171 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in bdw_set_pipemisc()
10172 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in bdw_set_pipemisc()
10175 switch (crtc_state->pipe_bpp) { in bdw_set_pipemisc()
10189 MISSING_CASE(crtc_state->pipe_bpp); in bdw_set_pipemisc()
10193 if (crtc_state->dither) in bdw_set_pipemisc()
10196 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || in bdw_set_pipemisc()
10197 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) in bdw_set_pipemisc()
10200 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in bdw_set_pipemisc()
10205 (crtc_state->active_planes & ~(icl_hdr_plane_mask() | in bdw_set_pipemisc()
10212 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); in bdw_set_pipemisc()
10217 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in bdw_get_pipemisc_bpp()
10220 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); in bdw_get_pipemisc_bpp()
10250 return i9xx_dpll_compute_m(dpll) < factor * dpll->n; in ilk_needs_fb_cb_tune()
10257 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_compute_dpll()
10265 dev_priv->vbt.lvds_ssc_freq == 100000) || in ilk_compute_dpll()
10269 } else if (crtc_state->sdvo_tv_clock) { in ilk_compute_dpll()
10273 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in ilk_compute_dpll()
10275 if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor)) in ilk_compute_dpll()
10281 if (reduced_clock->m < factor * reduced_clock->n) in ilk_compute_dpll()
10294 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_compute_dpll()
10316 * this on ILK at all since it has a fixed DPLL<->pipe mapping. in ilk_compute_dpll()
10323 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
10325 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
10327 switch (crtc_state->dpll.p2) { in ilk_compute_dpll()
10350 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
10351 crtc_state->dpll_hw_state.fp0 = fp; in ilk_compute_dpll()
10352 crtc_state->dpll_hw_state.fp1 = fp2; in ilk_compute_dpll()
10358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_crtc_compute_clock()
10360 to_intel_atomic_state(crtc_state->uapi.state); in ilk_crtc_compute_clock()
10362 int refclk = 120000; in ilk_crtc_compute_clock() local
10364 memset(&crtc_state->dpll_hw_state, 0, in ilk_crtc_compute_clock()
10365 sizeof(crtc_state->dpll_hw_state)); in ilk_crtc_compute_clock()
10368 if (!crtc_state->has_pch_encoder) in ilk_crtc_compute_clock()
10373 drm_dbg_kms(&dev_priv->drm, in ilk_crtc_compute_clock()
10375 dev_priv->vbt.lvds_ssc_freq); in ilk_crtc_compute_clock()
10376 refclk = dev_priv->vbt.lvds_ssc_freq; in ilk_crtc_compute_clock()
10380 if (refclk == 100000) in ilk_crtc_compute_clock()
10385 if (refclk == 100000) in ilk_crtc_compute_clock()
10394 if (!crtc_state->clock_set && in ilk_crtc_compute_clock()
10395 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
10396 refclk, NULL, &crtc_state->dpll)) { in ilk_crtc_compute_clock()
10397 drm_err(&dev_priv->drm, in ilk_crtc_compute_clock()
10399 return -EINVAL; in ilk_crtc_compute_clock()
10405 drm_dbg_kms(&dev_priv->drm, in ilk_crtc_compute_clock()
10407 pipe_name(crtc->pipe)); in ilk_crtc_compute_clock()
10408 return -EINVAL; in ilk_crtc_compute_clock()
10417 struct drm_device *dev = crtc->base.dev; in intel_pch_transcoder_get_m_n()
10419 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_get_m_n()
10421 m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe)); in intel_pch_transcoder_get_m_n()
10422 m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe)); in intel_pch_transcoder_get_m_n()
10423 m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe)) in intel_pch_transcoder_get_m_n()
10425 m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe)); in intel_pch_transcoder_get_m_n()
10426 m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe)) in intel_pch_transcoder_get_m_n()
10435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_cpu_transcoder_get_m_n()
10436 enum pipe pipe = crtc->pipe; in intel_cpu_transcoder_get_m_n()
10439 m_n->link_m = intel_de_read(dev_priv, in intel_cpu_transcoder_get_m_n()
10441 m_n->link_n = intel_de_read(dev_priv, in intel_cpu_transcoder_get_m_n()
10443 m_n->gmch_m = intel_de_read(dev_priv, in intel_cpu_transcoder_get_m_n()
10446 m_n->gmch_n = intel_de_read(dev_priv, in intel_cpu_transcoder_get_m_n()
10448 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder)) in intel_cpu_transcoder_get_m_n()
10452 m2_n2->link_m = intel_de_read(dev_priv, in intel_cpu_transcoder_get_m_n()
10454 m2_n2->link_n = intel_de_read(dev_priv, in intel_cpu_transcoder_get_m_n()
10456 m2_n2->gmch_m = intel_de_read(dev_priv, in intel_cpu_transcoder_get_m_n()
10459 m2_n2->gmch_n = intel_de_read(dev_priv, in intel_cpu_transcoder_get_m_n()
10461 m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder)) in intel_cpu_transcoder_get_m_n()
10465 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
10466 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
10467 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe)) in intel_cpu_transcoder_get_m_n()
10469 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
10470 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe)) in intel_cpu_transcoder_get_m_n()
10478 if (pipe_config->has_pch_encoder) in intel_dp_get_m_n()
10479 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); in intel_dp_get_m_n()
10481 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, in intel_dp_get_m_n()
10482 &pipe_config->dp_m_n, in intel_dp_get_m_n()
10483 &pipe_config->dp_m2_n2); in intel_dp_get_m_n()
10489 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, in ilk_get_fdi_m_n_config()
10490 &pipe_config->fdi_m_n, NULL); in ilk_get_fdi_m_n_config()
10496 drm_rect_init(&crtc_state->pch_pfit.dst, in ilk_get_pfit_pos_size()
10503 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_get_pfit_config()
10504 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in skl_get_pfit_config()
10505 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; in skl_get_pfit_config()
10506 int id = -1; in skl_get_pfit_config()
10510 for (i = 0; i < crtc->num_scalers; i++) { in skl_get_pfit_config()
10513 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); in skl_get_pfit_config()
10518 crtc_state->pch_pfit.enabled = true; in skl_get_pfit_config()
10520 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); in skl_get_pfit_config()
10521 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); in skl_get_pfit_config()
10525 scaler_state->scalers[i].in_use = true; in skl_get_pfit_config()
10529 scaler_state->scaler_id = id; in skl_get_pfit_config()
10531 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); in skl_get_pfit_config()
10533 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); in skl_get_pfit_config()
10540 struct drm_device *dev = crtc->base.dev; in skl_get_initial_plane_config()
10542 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in skl_get_initial_plane_config()
10543 enum plane_id plane_id = plane->id; in skl_get_initial_plane_config()
10551 if (!plane->get_hw_state(plane, &pipe)) in skl_get_initial_plane_config()
10554 drm_WARN_ON(dev, pipe != crtc->pipe); in skl_get_initial_plane_config()
10558 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); in skl_get_initial_plane_config()
10562 fb = &intel_fb->base; in skl_get_initial_plane_config()
10564 fb->dev = dev; in skl_get_initial_plane_config()
10583 fb->format = drm_format_info(fourcc); in skl_get_initial_plane_config()
10588 fb->modifier = DRM_FORMAT_MOD_LINEAR; in skl_get_initial_plane_config()
10591 plane_config->tiling = I915_TILING_X; in skl_get_initial_plane_config()
10592 fb->modifier = I915_FORMAT_MOD_X_TILED; in skl_get_initial_plane_config()
10595 plane_config->tiling = I915_TILING_Y; in skl_get_initial_plane_config()
10597 fb->modifier = INTEL_GEN(dev_priv) >= 12 ? in skl_get_initial_plane_config()
10601 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; in skl_get_initial_plane_config()
10603 fb->modifier = I915_FORMAT_MOD_Y_TILED; in skl_get_initial_plane_config()
10607 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; in skl_get_initial_plane_config()
10609 fb->modifier = I915_FORMAT_MOD_Yf_TILED; in skl_get_initial_plane_config()
10622 plane_config->rotation = DRM_MODE_ROTATE_0; in skl_get_initial_plane_config()
10625 plane_config->rotation = DRM_MODE_ROTATE_270; in skl_get_initial_plane_config()
10628 plane_config->rotation = DRM_MODE_ROTATE_180; in skl_get_initial_plane_config()
10631 plane_config->rotation = DRM_MODE_ROTATE_90; in skl_get_initial_plane_config()
10637 plane_config->rotation |= DRM_MODE_REFLECT_X; in skl_get_initial_plane_config()
10640 if (drm_rotation_90_or_270(plane_config->rotation)) in skl_get_initial_plane_config()
10644 plane_config->base = base; in skl_get_initial_plane_config()
10649 fb->height = ((val >> 16) & 0xffff) + 1; in skl_get_initial_plane_config()
10650 fb->width = ((val >> 0) & 0xffff) + 1; in skl_get_initial_plane_config()
10654 fb->pitches[0] = (val & 0x3ff) * stride_mult; in skl_get_initial_plane_config()
10656 aligned_height = intel_fb_align_height(fb, 0, fb->height); in skl_get_initial_plane_config()
10658 plane_config->size = fb->pitches[0] * aligned_height; in skl_get_initial_plane_config()
10660 drm_dbg_kms(&dev_priv->drm, in skl_get_initial_plane_config()
10662 crtc->base.name, plane->base.name, fb->width, fb->height, in skl_get_initial_plane_config()
10663 fb->format->cpp[0] * 8, base, fb->pitches[0], in skl_get_initial_plane_config()
10664 plane_config->size); in skl_get_initial_plane_config()
10666 plane_config->fb = intel_fb; in skl_get_initial_plane_config()
10675 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_get_pfit_config()
10676 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_get_pfit_config()
10679 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); in ilk_get_pfit_config()
10683 crtc_state->pch_pfit.enabled = true; in ilk_get_pfit_config()
10685 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); in ilk_get_pfit_config()
10686 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); in ilk_get_pfit_config()
10695 drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) && in ilk_get_pfit_config()
10696 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); in ilk_get_pfit_config()
10702 struct drm_device *dev = crtc->base.dev; in ilk_get_pipe_config()
10709 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); in ilk_get_pipe_config()
10714 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in ilk_get_pipe_config()
10715 pipe_config->shared_dpll = NULL; in ilk_get_pipe_config()
10718 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); in ilk_get_pipe_config()
10724 pipe_config->pipe_bpp = 18; in ilk_get_pipe_config()
10727 pipe_config->pipe_bpp = 24; in ilk_get_pipe_config()
10730 pipe_config->pipe_bpp = 30; in ilk_get_pipe_config()
10733 pipe_config->pipe_bpp = 36; in ilk_get_pipe_config()
10740 pipe_config->limited_color_range = true; in ilk_get_pipe_config()
10745 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; in ilk_get_pipe_config()
10748 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in ilk_get_pipe_config()
10752 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >> in ilk_get_pipe_config()
10755 pipe_config->csc_mode = intel_de_read(dev_priv, in ilk_get_pipe_config()
10756 PIPE_CSC_MODE(crtc->pipe)); in ilk_get_pipe_config()
10761 if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { in ilk_get_pipe_config()
10765 pipe_config->has_pch_encoder = true; in ilk_get_pipe_config()
10767 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe)); in ilk_get_pipe_config()
10768 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> in ilk_get_pipe_config()
10775 * The pipe->pch transcoder and pch transcoder->pll in ilk_get_pipe_config()
10778 pll_id = (enum intel_dpll_id) crtc->pipe; in ilk_get_pipe_config()
10781 if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) in ilk_get_pipe_config()
10787 pipe_config->shared_dpll = in ilk_get_pipe_config()
10789 pll = pipe_config->shared_dpll; in ilk_get_pipe_config()
10791 drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll, in ilk_get_pipe_config()
10792 &pipe_config->dpll_hw_state)); in ilk_get_pipe_config()
10794 tmp = pipe_config->dpll_hw_state.dpll; in ilk_get_pipe_config()
10795 pipe_config->pixel_multiplier = in ilk_get_pipe_config()
10801 pipe_config->pixel_multiplier = 1; in ilk_get_pipe_config()
10820 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_crtc_compute_clock()
10822 to_intel_atomic_state(crtc_state->uapi.state); in hsw_crtc_compute_clock()
10830 drm_dbg_kms(&dev_priv->drm, in hsw_crtc_compute_clock()
10832 pipe_name(crtc->pipe)); in hsw_crtc_compute_clock()
10833 return -EINVAL; in hsw_crtc_compute_clock()
10849 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2)) in cnl_get_ddi_pll()
10852 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); in cnl_get_ddi_pll()
10885 drm_WARN_ON(&dev_priv->drm, in icl_get_ddi_pll()
10891 drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port); in icl_get_ddi_pll()
10895 pipe_config->icl_port_dplls[port_dpll_id].pll = in icl_get_ddi_pll()
10918 drm_err(&dev_priv->drm, "Incorrect port type\n"); in bxt_get_ddi_pll()
10922 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); in bxt_get_ddi_pll()
10934 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3)) in skl_get_ddi_pll()
10937 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); in skl_get_ddi_pll()
10972 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); in hsw_get_ddi_pll()
10980 struct drm_device *dev = crtc->base.dev; in hsw_get_transcoder_state()
10994 * The pipe->transcoder mapping is fixed with the exception of the eDP in hsw_get_transcoder_state()
10997 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in hsw_get_transcoder_state()
11045 if (trans_pipe == crtc->pipe) { in hsw_get_transcoder_state()
11046 pipe_config->cpu_transcoder = panel_transcoder; in hsw_get_transcoder_state()
11047 pipe_config->pch_pfit.force_thru = force_thru; in hsw_get_transcoder_state()
11057 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); in hsw_get_transcoder_state()
11067 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); in hsw_get_transcoder_state()
11077 struct drm_device *dev = crtc->base.dev; in bxt_get_dsi_transcoder_state()
11117 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) in bxt_get_dsi_transcoder_state()
11120 pipe_config->cpu_transcoder = cpu_transcoder; in bxt_get_dsi_transcoder_state()
11124 return transcoder_is_dsi(pipe_config->cpu_transcoder); in bxt_get_dsi_transcoder_state()
11130 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_get_ddi_port_state()
11131 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in hsw_get_ddi_port_state()
11159 pll = pipe_config->shared_dpll; in hsw_get_ddi_port_state()
11161 drm_WARN_ON(&dev_priv->drm, in hsw_get_ddi_port_state()
11162 !pll->info->funcs->get_hw_state(dev_priv, pll, in hsw_get_ddi_port_state()
11163 &pipe_config->dpll_hw_state)); in hsw_get_ddi_port_state()
11173 pipe_config->has_pch_encoder = true; in hsw_get_ddi_port_state()
11176 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> in hsw_get_ddi_port_state()
11186 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_get_pipe_config()
11193 pipe_config->master_transcoder = INVALID_TRANSCODER; in hsw_get_pipe_config()
11195 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); in hsw_get_pipe_config()
11203 pipe_config->shared_dpll = NULL; in hsw_get_pipe_config()
11211 drm_WARN_ON(&dev_priv->drm, active); in hsw_get_pipe_config()
11218 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || in hsw_get_pipe_config()
11228 PIPECONF(pipe_config->cpu_transcoder)); in hsw_get_pipe_config()
11231 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; in hsw_get_pipe_config()
11233 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in hsw_get_pipe_config()
11235 pipe_config->output_format = in hsw_get_pipe_config()
11247 pipe_config->lspcon_downsampling = in hsw_get_pipe_config()
11248 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444; in hsw_get_pipe_config()
11251 pipe_config->gamma_mode = intel_de_read(dev_priv, in hsw_get_pipe_config()
11252 GAMMA_MODE(crtc->pipe)); in hsw_get_pipe_config()
11254 pipe_config->csc_mode = intel_de_read(dev_priv, in hsw_get_pipe_config()
11255 PIPE_CSC_MODE(crtc->pipe)); in hsw_get_pipe_config()
11258 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); in hsw_get_pipe_config()
11261 pipe_config->gamma_enable = true; in hsw_get_pipe_config()
11264 pipe_config->csc_enable = true; in hsw_get_pipe_config()
11271 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); in hsw_get_pipe_config()
11272 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); in hsw_get_pipe_config()
11274 pipe_config->ips_linetime = in hsw_get_pipe_config()
11277 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); in hsw_get_pipe_config()
11278 drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain)); in hsw_get_pipe_config()
11293 pipe_config->ips_enabled = intel_de_read(dev_priv, in hsw_get_pipe_config()
11301 pipe_config->ips_enabled = true; in hsw_get_pipe_config()
11305 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && in hsw_get_pipe_config()
11306 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { in hsw_get_pipe_config()
11307 pipe_config->pixel_multiplier = in hsw_get_pipe_config()
11309 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; in hsw_get_pipe_config()
11311 pipe_config->pixel_multiplier = 1; in hsw_get_pipe_config()
11325 to_i915(plane_state->uapi.plane->dev); in intel_cursor_base()
11326 const struct drm_framebuffer *fb = plane_state->hw.fb; in intel_cursor_base()
11330 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical) in intel_cursor_base()
11331 base = sg_dma_address(obj->mm.pages->sgl); in intel_cursor_base()
11335 return base + plane_state->color_plane[0].offset; in intel_cursor_base()
11340 int x = plane_state->uapi.dst.x1; in intel_cursor_position()
11341 int y = plane_state->uapi.dst.y1; in intel_cursor_position()
11346 x = -x; in intel_cursor_position()
11352 y = -y; in intel_cursor_position()
11362 &plane_state->uapi.plane->dev->mode_config; in intel_cursor_size_ok()
11363 int width = drm_rect_width(&plane_state->uapi.dst); in intel_cursor_size_ok()
11364 int height = drm_rect_height(&plane_state->uapi.dst); in intel_cursor_size_ok()
11366 return width > 0 && width <= config->cursor_width && in intel_cursor_size_ok()
11367 height > 0 && height <= config->cursor_height; in intel_cursor_size_ok()
11373 to_i915(plane_state->uapi.plane->dev); in intel_cursor_check_surface()
11374 unsigned int rotation = plane_state->hw.rotation; in intel_cursor_check_surface()
11383 if (!plane_state->uapi.visible) in intel_cursor_check_surface()
11386 src_x = plane_state->uapi.src.x1 >> 16; in intel_cursor_check_surface()
11387 src_y = plane_state->uapi.src.y1 >> 16; in intel_cursor_check_surface()
11394 drm_dbg_kms(&dev_priv->drm, in intel_cursor_check_surface()
11396 return -EINVAL; in intel_cursor_check_surface()
11403 drm_rect_translate_to(&plane_state->uapi.src, in intel_cursor_check_surface()
11408 const struct drm_framebuffer *fb = plane_state->hw.fb; in intel_cursor_check_surface()
11409 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; in intel_cursor_check_surface()
11410 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; in intel_cursor_check_surface()
11412 offset += (src_h * src_w - 1) * fb->format->cpp[0]; in intel_cursor_check_surface()
11415 plane_state->color_plane[0].offset = offset; in intel_cursor_check_surface()
11416 plane_state->color_plane[0].x = src_x; in intel_cursor_check_surface()
11417 plane_state->color_plane[0].y = src_y; in intel_cursor_check_surface()
11425 const struct drm_framebuffer *fb = plane_state->hw.fb; in intel_check_cursor()
11426 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); in intel_check_cursor()
11429 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { in intel_check_cursor()
11430 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n"); in intel_check_cursor()
11431 return -EINVAL; in intel_check_cursor()
11434 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, in intel_check_cursor()
11435 &crtc_state->uapi, in intel_check_cursor()
11443 plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi); in intel_check_cursor()
11444 plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi); in intel_check_cursor()
11450 if (!plane_state->uapi.visible) in intel_check_cursor()
11472 if (crtc_state->gamma_enable) in i845_cursor_ctl_crtc()
11483 CURSOR_STRIDE(plane_state->color_plane[0].stride); in i845_cursor_ctl()
11488 int width = drm_rect_width(&plane_state->uapi.dst); in i845_cursor_size_ok()
11500 const struct drm_framebuffer *fb = plane_state->hw.fb; in i845_check_cursor()
11501 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); in i845_check_cursor()
11514 drm_dbg_kms(&i915->drm, in i845_check_cursor()
11516 drm_rect_width(&plane_state->uapi.dst), in i845_check_cursor()
11517 drm_rect_height(&plane_state->uapi.dst)); in i845_check_cursor()
11518 return -EINVAL; in i845_check_cursor()
11521 drm_WARN_ON(&i915->drm, plane_state->uapi.visible && in i845_check_cursor()
11522 plane_state->color_plane[0].stride != fb->pitches[0]); in i845_check_cursor()
11524 switch (fb->pitches[0]) { in i845_check_cursor()
11531 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n", in i845_check_cursor()
11532 fb->pitches[0]); in i845_check_cursor()
11533 return -EINVAL; in i845_check_cursor()
11536 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); in i845_check_cursor()
11545 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i845_update_cursor()
11549 if (plane_state && plane_state->uapi.visible) { in i845_update_cursor()
11550 unsigned int width = drm_rect_width(&plane_state->uapi.dst); in i845_update_cursor()
11551 unsigned int height = drm_rect_height(&plane_state->uapi.dst); in i845_update_cursor()
11553 cntl = plane_state->ctl | in i845_update_cursor()
11562 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i845_update_cursor()
11567 if (plane->cursor.base != base || in i845_update_cursor()
11568 plane->cursor.size != size || in i845_update_cursor()
11569 plane->cursor.cntl != cntl) { in i845_update_cursor()
11576 plane->cursor.base = base; in i845_update_cursor()
11577 plane->cursor.size = size; in i845_update_cursor()
11578 plane->cursor.cntl = cntl; in i845_update_cursor()
11583 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i845_update_cursor()
11595 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i845_cursor_get_hw_state()
11619 return plane->base.dev->mode_config.cursor_width * 4; in i9xx_cursor_max_stride()
11624 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_cursor_ctl_crtc()
11625 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_cursor_ctl_crtc()
11631 if (crtc_state->gamma_enable) in i9xx_cursor_ctl_crtc()
11634 if (crtc_state->csc_enable) in i9xx_cursor_ctl_crtc()
11638 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); in i9xx_cursor_ctl_crtc()
11647 to_i915(plane_state->uapi.plane->dev); in i9xx_cursor_ctl()
11653 switch (drm_rect_width(&plane_state->uapi.dst)) { in i9xx_cursor_ctl()
11664 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst)); in i9xx_cursor_ctl()
11668 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180) in i9xx_cursor_ctl()
11677 to_i915(plane_state->uapi.plane->dev); in i9xx_cursor_size_ok()
11678 int width = drm_rect_width(&plane_state->uapi.dst); in i9xx_cursor_size_ok()
11679 int height = drm_rect_height(&plane_state->uapi.dst); in i9xx_cursor_size_ok()
11684 /* Cursor width is limited to a few power-of-two sizes */ in i9xx_cursor_size_ok()
11701 plane_state->hw.rotation & DRM_MODE_ROTATE_0) { in i9xx_cursor_size_ok()
11715 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in i9xx_check_cursor()
11716 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i9xx_check_cursor()
11717 const struct drm_framebuffer *fb = plane_state->hw.fb; in i9xx_check_cursor()
11718 enum pipe pipe = plane->pipe; in i9xx_check_cursor()
11731 drm_dbg(&dev_priv->drm, in i9xx_check_cursor()
11733 drm_rect_width(&plane_state->uapi.dst), in i9xx_check_cursor()
11734 drm_rect_height(&plane_state->uapi.dst)); in i9xx_check_cursor()
11735 return -EINVAL; in i9xx_check_cursor()
11738 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && in i9xx_check_cursor()
11739 plane_state->color_plane[0].stride != fb->pitches[0]); in i9xx_check_cursor()
11741 if (fb->pitches[0] != in i9xx_check_cursor()
11742 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { in i9xx_check_cursor()
11743 drm_dbg_kms(&dev_priv->drm, in i9xx_check_cursor()
11745 fb->pitches[0], in i9xx_check_cursor()
11746 drm_rect_width(&plane_state->uapi.dst)); in i9xx_check_cursor()
11747 return -EINVAL; in i9xx_check_cursor()
11761 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { in i9xx_check_cursor()
11762 drm_dbg_kms(&dev_priv->drm, in i9xx_check_cursor()
11764 return -EINVAL; in i9xx_check_cursor()
11767 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); in i9xx_check_cursor()
11776 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i9xx_update_cursor()
11777 enum pipe pipe = plane->pipe; in i9xx_update_cursor()
11781 if (plane_state && plane_state->uapi.visible) { in i9xx_update_cursor()
11782 unsigned width = drm_rect_width(&plane_state->uapi.dst); in i9xx_update_cursor()
11783 unsigned height = drm_rect_height(&plane_state->uapi.dst); in i9xx_update_cursor()
11785 cntl = plane_state->ctl | in i9xx_update_cursor()
11789 fbc_ctl = CUR_FBC_CTL_EN | (height - 1); in i9xx_update_cursor()
11795 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i9xx_update_cursor()
11820 if (plane->cursor.base != base || in i9xx_update_cursor()
11821 plane->cursor.size != fbc_ctl || in i9xx_update_cursor()
11822 plane->cursor.cntl != cntl) { in i9xx_update_cursor()
11830 plane->cursor.base = base; in i9xx_update_cursor()
11831 plane->cursor.size = fbc_ctl; in i9xx_update_cursor()
11832 plane->cursor.cntl = cntl; in i9xx_update_cursor()
11838 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i9xx_update_cursor()
11850 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i9xx_cursor_get_hw_state()
11858 * but that's only the case for gen2-3 which don't have any in i9xx_cursor_get_hw_state()
11861 power_domain = POWER_DOMAIN_PIPE(plane->pipe); in i9xx_cursor_get_hw_state()
11866 val = intel_de_read(dev_priv, CURCNTR(plane->pipe)); in i9xx_cursor_get_hw_state()
11871 *pipe = plane->pipe; in i9xx_cursor_get_hw_state()
11896 return ERR_PTR(-ENOMEM); in intel_framebuffer_create()
11902 return &intel_fb->base; in intel_framebuffer_create()
11921 if (plane_state->crtc != crtc) in intel_modeset_disable_planes()
11942 struct drm_encoder *encoder = &intel_encoder->base; in intel_get_load_detect_pipe()
11944 struct drm_device *dev = encoder->dev; in intel_get_load_detect_pipe()
11946 struct drm_mode_config *config = &dev->mode_config; in intel_get_load_detect_pipe()
11950 int ret, i = -1; in intel_get_load_detect_pipe()
11952 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", in intel_get_load_detect_pipe()
11953 connector->base.id, connector->name, in intel_get_load_detect_pipe()
11954 encoder->base.id, encoder->name); in intel_get_load_detect_pipe()
11956 old->restore_state = NULL; in intel_get_load_detect_pipe()
11958 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); in intel_get_load_detect_pipe()
11963 * - if the connector already has an assigned crtc, use it (but make in intel_get_load_detect_pipe()
11966 * - try to find the first unused crtc that can drive this connector, in intel_get_load_detect_pipe()
11971 if (connector->state->crtc) { in intel_get_load_detect_pipe()
11972 crtc = connector->state->crtc; in intel_get_load_detect_pipe()
11974 ret = drm_modeset_lock(&crtc->mutex, ctx); in intel_get_load_detect_pipe()
11985 if (!(encoder->possible_crtcs & (1 << i))) in intel_get_load_detect_pipe()
11988 ret = drm_modeset_lock(&possible_crtc->mutex, ctx); in intel_get_load_detect_pipe()
11992 if (possible_crtc->state->enable) { in intel_get_load_detect_pipe()
11993 drm_modeset_unlock(&possible_crtc->mutex); in intel_get_load_detect_pipe()
12005 drm_dbg_kms(&dev_priv->drm, in intel_get_load_detect_pipe()
12006 "no pipe available for load-detect\n"); in intel_get_load_detect_pipe()
12007 ret = -ENODEV; in intel_get_load_detect_pipe()
12017 ret = -ENOMEM; in intel_get_load_detect_pipe()
12021 state->acquire_ctx = ctx; in intel_get_load_detect_pipe()
12022 restore_state->acquire_ctx = ctx; in intel_get_load_detect_pipe()
12040 crtc_state->uapi.active = true; in intel_get_load_detect_pipe()
12042 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, in intel_get_load_detect_pipe()
12057 drm_dbg_kms(&dev_priv->drm, in intel_get_load_detect_pipe()
12065 drm_dbg_kms(&dev_priv->drm, in intel_get_load_detect_pipe()
12066 "failed to set mode on load-detect pipe\n"); in intel_get_load_detect_pipe()
12070 old->restore_state = restore_state; in intel_get_load_detect_pipe()
12074 intel_wait_for_vblank(dev_priv, intel_crtc->pipe); in intel_get_load_detect_pipe()
12087 if (ret == -EDEADLK) in intel_get_load_detect_pipe()
12099 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); in intel_release_load_detect_pipe()
12100 struct drm_encoder *encoder = &intel_encoder->base; in intel_release_load_detect_pipe()
12101 struct drm_atomic_state *state = old->restore_state; in intel_release_load_detect_pipe()
12104 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", in intel_release_load_detect_pipe()
12105 connector->base.id, connector->name, in intel_release_load_detect_pipe()
12106 encoder->base.id, encoder->name); in intel_release_load_detect_pipe()
12113 drm_dbg_kms(&i915->drm, in intel_release_load_detect_pipe()
12122 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk()
12125 return dev_priv->vbt.lvds_ssc_freq; in i9xx_pll_refclk()
12138 struct drm_device *dev = crtc->base.dev; in i9xx_crtc_clock_get()
12140 enum pipe pipe = crtc->pipe; in i9xx_crtc_clock_get()
12141 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get()
12145 int refclk = i9xx_pll_refclk(dev, pipe_config); in i9xx_crtc_clock_get() local
12148 fp = pipe_config->dpll_hw_state.fp0; in i9xx_crtc_clock_get()
12150 fp = pipe_config->dpll_hw_state.fp1; in i9xx_crtc_clock_get()
12154 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; in i9xx_crtc_clock_get()
12179 drm_dbg_kms(&dev_priv->drm, in i9xx_crtc_clock_get()
12186 port_clock = pnv_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
12188 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
12215 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
12223 pipe_config->port_clock = port_clock; in i9xx_crtc_clock_get()
12239 if (!m_n->link_n) in intel_dotclock_calculate()
12242 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); in intel_dotclock_calculate()
12248 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_pch_clock_get()
12258 pipe_config->hw.adjusted_mode.crtc_clock = in ilk_pch_clock_get()
12260 &pipe_config->fdi_m_n); in ilk_pch_clock_get()
12268 __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base); in intel_crtc_state_reset()
12270 crtc_state->cpu_transcoder = INVALID_TRANSCODER; in intel_crtc_state_reset()
12271 crtc_state->master_transcoder = INVALID_TRANSCODER; in intel_crtc_state_reset()
12272 crtc_state->hsw_workaround_pipe = INVALID_PIPE; in intel_crtc_state_reset()
12273 crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID; in intel_crtc_state_reset()
12274 crtc_state->scaler_state.scaler_id = -1; in intel_crtc_state_reset()
12275 crtc_state->mst_master_transcoder = INVALID_TRANSCODER; in intel_crtc_state_reset()
12294 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_encoder_current_mode()
12300 if (!encoder->get_hw_state(encoder, &pipe)) in intel_encoder_current_mode()
12315 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) { in intel_encoder_current_mode()
12321 encoder->get_config(encoder, crtc_state); in intel_encoder_current_mode()
12339 * intel_wm_need_update - Check whether watermarks need updating
12352 if (new->uapi.visible != cur->uapi.visible) in intel_wm_need_update()
12355 if (!cur->hw.fb || !new->hw.fb) in intel_wm_need_update()
12358 if (cur->hw.fb->modifier != new->hw.fb->modifier || in intel_wm_need_update()
12359 cur->hw.rotation != new->hw.rotation || in intel_wm_need_update()
12360 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) || in intel_wm_need_update()
12361 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) || in intel_wm_need_update()
12362 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) || in intel_wm_need_update()
12363 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst)) in intel_wm_need_update()
12371 int src_w = drm_rect_width(&state->uapi.src) >> 16; in needs_scaling()
12372 int src_h = drm_rect_height(&state->uapi.src) >> 16; in needs_scaling()
12373 int dst_w = drm_rect_width(&state->uapi.dst); in needs_scaling()
12374 int dst_h = drm_rect_height(&state->uapi.dst); in needs_scaling()
12384 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_plane_atomic_calc_changes()
12385 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_plane_atomic_calc_changes()
12386 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_plane_atomic_calc_changes()
12388 bool was_crtc_enabled = old_crtc_state->hw.active; in intel_plane_atomic_calc_changes()
12389 bool is_crtc_enabled = crtc_state->hw.active; in intel_plane_atomic_calc_changes()
12393 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { in intel_plane_atomic_calc_changes()
12399 was_visible = old_plane_state->uapi.visible; in intel_plane_atomic_calc_changes()
12400 visible = plane_state->uapi.visible; in intel_plane_atomic_calc_changes()
12402 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible)) in intel_plane_atomic_calc_changes()
12412 * per-plane wm computation to the .check_plane() hook, and in intel_plane_atomic_calc_changes()
12426 drm_dbg_atomic(&dev_priv->drm, in intel_plane_atomic_calc_changes()
12427 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", in intel_plane_atomic_calc_changes()
12428 crtc->base.base.id, crtc->base.name, in intel_plane_atomic_calc_changes()
12429 plane->base.base.id, plane->base.name, in intel_plane_atomic_calc_changes()
12435 crtc_state->update_wm_pre = true; in intel_plane_atomic_calc_changes()
12438 if (plane->id != PLANE_CURSOR) in intel_plane_atomic_calc_changes()
12439 crtc_state->disable_cxsr = true; in intel_plane_atomic_calc_changes()
12442 crtc_state->update_wm_post = true; in intel_plane_atomic_calc_changes()
12445 if (plane->id != PLANE_CURSOR) in intel_plane_atomic_calc_changes()
12446 crtc_state->disable_cxsr = true; in intel_plane_atomic_calc_changes()
12450 crtc_state->update_wm_pre = true; in intel_plane_atomic_calc_changes()
12451 crtc_state->update_wm_post = true; in intel_plane_atomic_calc_changes()
12456 crtc_state->fb_bits |= plane->frontbuffer_bit; in intel_plane_atomic_calc_changes()
12491 if (plane->id != PLANE_CURSOR && in intel_plane_atomic_calc_changes()
12496 crtc_state->disable_lp_wm = true; in intel_plane_atomic_calc_changes()
12505 return a == b || (a->cloneable & (1 << b->type) && in encoders_cloneable()
12506 b->cloneable & (1 << a->type)); in encoders_cloneable()
12519 if (connector_state->crtc != &crtc->base) in check_single_encoder_cloning()
12523 to_intel_encoder(connector_state->best_encoder); in check_single_encoder_cloning()
12538 linked = plane_state->planar_linked_plane; in icl_add_linked_planes()
12547 drm_WARN_ON(state->base.dev, in icl_add_linked_planes()
12548 linked_plane_state->planar_linked_plane != plane); in icl_add_linked_planes()
12549 drm_WARN_ON(state->base.dev, in icl_add_linked_planes()
12550 linked_plane_state->planar_slave == plane_state->planar_slave); in icl_add_linked_planes()
12558 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in icl_check_nv12_planes()
12559 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in icl_check_nv12_planes()
12560 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); in icl_check_nv12_planes()
12570 * in the crtc_state->active_planes mask. in icl_check_nv12_planes()
12573 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) in icl_check_nv12_planes()
12576 plane_state->planar_linked_plane = NULL; in icl_check_nv12_planes()
12577 if (plane_state->planar_slave && !plane_state->uapi.visible) { in icl_check_nv12_planes()
12578 crtc_state->active_planes &= ~BIT(plane->id); in icl_check_nv12_planes()
12579 crtc_state->update_planes |= BIT(plane->id); in icl_check_nv12_planes()
12582 plane_state->planar_slave = false; in icl_check_nv12_planes()
12585 if (!crtc_state->nv12_planes) in icl_check_nv12_planes()
12591 if (plane->pipe != crtc->pipe || in icl_check_nv12_planes()
12592 !(crtc_state->nv12_planes & BIT(plane->id))) in icl_check_nv12_planes()
12595 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { in icl_check_nv12_planes()
12596 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) in icl_check_nv12_planes()
12599 if (crtc_state->active_planes & BIT(linked->id)) in icl_check_nv12_planes()
12610 drm_dbg_kms(&dev_priv->drm, in icl_check_nv12_planes()
12612 hweight8(crtc_state->nv12_planes)); in icl_check_nv12_planes()
12614 return -EINVAL; in icl_check_nv12_planes()
12617 plane_state->planar_linked_plane = linked; in icl_check_nv12_planes()
12619 linked_state->planar_slave = true; in icl_check_nv12_planes()
12620 linked_state->planar_linked_plane = plane; in icl_check_nv12_planes()
12621 crtc_state->active_planes |= BIT(linked->id); in icl_check_nv12_planes()
12622 crtc_state->update_planes |= BIT(linked->id); in icl_check_nv12_planes()
12623 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", in icl_check_nv12_planes()
12624 linked->base.name, plane->base.name); in icl_check_nv12_planes()
12627 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; in icl_check_nv12_planes()
12628 linked_state->color_ctl = plane_state->color_ctl; in icl_check_nv12_planes()
12629 linked_state->view = plane_state->view; in icl_check_nv12_planes()
12630 memcpy(linked_state->color_plane, plane_state->color_plane, in icl_check_nv12_planes()
12631 sizeof(linked_state->color_plane)); in icl_check_nv12_planes()
12634 linked_state->uapi.src = plane_state->uapi.src; in icl_check_nv12_planes()
12635 linked_state->uapi.dst = plane_state->uapi.dst; in icl_check_nv12_planes()
12637 if (icl_is_hdr_plane(dev_priv, plane->id)) { in icl_check_nv12_planes()
12638 if (linked->id == PLANE_SPRITE5) in icl_check_nv12_planes()
12639 plane_state->cus_ctl |= PLANE_CUS_PLANE_7; in icl_check_nv12_planes()
12640 else if (linked->id == PLANE_SPRITE4) in icl_check_nv12_planes()
12641 plane_state->cus_ctl |= PLANE_CUS_PLANE_6; in icl_check_nv12_planes()
12642 else if (linked->id == PLANE_SPRITE3) in icl_check_nv12_planes()
12643 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL; in icl_check_nv12_planes()
12644 else if (linked->id == PLANE_SPRITE2) in icl_check_nv12_planes()
12645 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL; in icl_check_nv12_planes()
12647 MISSING_CASE(linked->id); in icl_check_nv12_planes()
12656 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); in c8_planes_changed()
12658 to_intel_atomic_state(new_crtc_state->uapi.state); in c8_planes_changed()
12662 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; in c8_planes_changed()
12668 &crtc_state->hw.adjusted_mode; in hsw_linetime_wm()
12671 if (!crtc_state->hw.enable) in hsw_linetime_wm()
12674 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, in hsw_linetime_wm()
12675 adjusted_mode->crtc_clock); in hsw_linetime_wm()
12684 &crtc_state->hw.adjusted_mode; in hsw_ips_linetime_wm()
12687 if (!crtc_state->hw.enable) in hsw_ips_linetime_wm()
12690 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, in hsw_ips_linetime_wm()
12691 cdclk_state->logical.cdclk); in hsw_ips_linetime_wm()
12698 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_linetime_wm()
12699 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in skl_linetime_wm()
12701 &crtc_state->hw.adjusted_mode; in skl_linetime_wm()
12704 if (!crtc_state->hw.enable) in skl_linetime_wm()
12707 linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8, in skl_linetime_wm()
12708 crtc_state->pixel_rate); in skl_linetime_wm()
12711 if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) in skl_linetime_wm()
12720 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_compute_linetime_wm()
12726 crtc_state->linetime = skl_linetime_wm(crtc_state); in hsw_compute_linetime_wm()
12728 crtc_state->linetime = hsw_linetime_wm(crtc_state); in hsw_compute_linetime_wm()
12737 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, in hsw_compute_linetime_wm()
12746 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_atomic_check()
12753 mode_changed && !crtc_state->hw.active) in intel_crtc_atomic_check()
12754 crtc_state->update_wm_post = true; in intel_crtc_atomic_check()
12756 if (mode_changed && crtc_state->hw.enable && in intel_crtc_atomic_check()
12757 dev_priv->display.crtc_compute_clock && in intel_crtc_atomic_check()
12758 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) { in intel_crtc_atomic_check()
12759 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state); in intel_crtc_atomic_check()
12769 crtc_state->uapi.color_mgmt_changed = true; in intel_crtc_atomic_check()
12771 if (mode_changed || crtc_state->update_pipe || in intel_crtc_atomic_check()
12772 crtc_state->uapi.color_mgmt_changed) { in intel_crtc_atomic_check()
12778 if (dev_priv->display.compute_pipe_wm) { in intel_crtc_atomic_check()
12779 ret = dev_priv->display.compute_pipe_wm(crtc_state); in intel_crtc_atomic_check()
12781 drm_dbg_kms(&dev_priv->drm, in intel_crtc_atomic_check()
12787 if (dev_priv->display.compute_intermediate_wm) { in intel_crtc_atomic_check()
12788 if (drm_WARN_ON(&dev_priv->drm, in intel_crtc_atomic_check()
12789 !dev_priv->display.compute_pipe_wm)) in intel_crtc_atomic_check()
12797 ret = dev_priv->display.compute_intermediate_wm(crtc_state); in intel_crtc_atomic_check()
12799 drm_dbg_kms(&dev_priv->drm, in intel_crtc_atomic_check()
12806 if (mode_changed || crtc_state->update_pipe) { in intel_crtc_atomic_check()
12844 if (connector->base.state->crtc) in intel_modeset_update_connector_atomic_state()
12845 drm_connector_put(&connector->base); in intel_modeset_update_connector_atomic_state()
12847 if (connector->base.encoder) { in intel_modeset_update_connector_atomic_state()
12848 connector->base.state->best_encoder = in intel_modeset_update_connector_atomic_state()
12849 connector->base.encoder; in intel_modeset_update_connector_atomic_state()
12850 connector->base.state->crtc = in intel_modeset_update_connector_atomic_state()
12851 connector->base.encoder->crtc; in intel_modeset_update_connector_atomic_state()
12853 drm_connector_get(&connector->base); in intel_modeset_update_connector_atomic_state()
12855 connector->base.state->best_encoder = NULL; in intel_modeset_update_connector_atomic_state()
12856 connector->base.state->crtc = NULL; in intel_modeset_update_connector_atomic_state()
12866 struct drm_connector *connector = conn_state->connector; in compute_sink_pipe_bpp()
12867 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); in compute_sink_pipe_bpp()
12868 const struct drm_display_info *info = &connector->display_info; in compute_sink_pipe_bpp()
12871 switch (conn_state->max_bpc) { in compute_sink_pipe_bpp()
12885 MISSING_CASE(conn_state->max_bpc); in compute_sink_pipe_bpp()
12886 return -EINVAL; in compute_sink_pipe_bpp()
12889 if (bpp < pipe_config->pipe_bpp) { in compute_sink_pipe_bpp()
12890 drm_dbg_kms(&i915->drm, in compute_sink_pipe_bpp()
12893 connector->base.id, connector->name, in compute_sink_pipe_bpp()
12894 bpp, 3 * info->bpc, in compute_sink_pipe_bpp()
12895 3 * conn_state->max_requested_bpc, in compute_sink_pipe_bpp()
12896 pipe_config->pipe_bpp); in compute_sink_pipe_bpp()
12898 pipe_config->pipe_bpp = bpp; in compute_sink_pipe_bpp()
12908 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in compute_baseline_pipe_bpp()
12909 struct drm_atomic_state *state = pipe_config->uapi.state; in compute_baseline_pipe_bpp()
12922 pipe_config->pipe_bpp = bpp; in compute_baseline_pipe_bpp()
12928 if (connector_state->crtc != &crtc->base) in compute_baseline_pipe_bpp()
12942 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " in intel_dump_crtc_timings()
12944 mode->crtc_clock, in intel_dump_crtc_timings()
12945 mode->crtc_hdisplay, mode->crtc_hsync_start, in intel_dump_crtc_timings()
12946 mode->crtc_hsync_end, mode->crtc_htotal, in intel_dump_crtc_timings()
12947 mode->crtc_vdisplay, mode->crtc_vsync_start, in intel_dump_crtc_timings()
12948 mode->crtc_vsync_end, mode->crtc_vtotal, in intel_dump_crtc_timings()
12949 mode->type, mode->flags); in intel_dump_crtc_timings()
12957 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); in intel_dump_m_n_config()
12959 drm_dbg_kms(&i915->drm, in intel_dump_m_n_config()
12962 m_n->gmch_m, m_n->gmch_n, in intel_dump_m_n_config()
12963 m_n->link_m, m_n->link_n, m_n->tu); in intel_dump_m_n_config()
12973 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); in intel_dump_infoframe()
12983 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); in intel_dump_dp_vsc_sdp()
13024 len -= r; in snprintf_output_types()
13048 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_dump_plane_state()
13049 struct drm_i915_private *i915 = to_i915(plane->base.dev); in intel_dump_plane_state()
13050 const struct drm_framebuffer *fb = plane_state->hw.fb; in intel_dump_plane_state()
13054 drm_dbg_kms(&i915->drm, in intel_dump_plane_state()
13056 plane->base.base.id, plane->base.name, in intel_dump_plane_state()
13057 yesno(plane_state->uapi.visible)); in intel_dump_plane_state()
13061 drm_dbg_kms(&i915->drm, in intel_dump_plane_state()
13063 plane->base.base.id, plane->base.name, in intel_dump_plane_state()
13064 fb->base.id, fb->width, fb->height, in intel_dump_plane_state()
13065 drm_get_format_name(fb->format->format, &format_name), in intel_dump_plane_state()
13066 yesno(plane_state->uapi.visible)); in intel_dump_plane_state()
13067 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", in intel_dump_plane_state()
13068 plane_state->hw.rotation, plane_state->scaler_id); in intel_dump_plane_state()
13069 if (plane_state->uapi.visible) in intel_dump_plane_state()
13070 drm_dbg_kms(&i915->drm, in intel_dump_plane_state()
13072 DRM_RECT_FP_ARG(&plane_state->uapi.src), in intel_dump_plane_state()
13073 DRM_RECT_ARG(&plane_state->uapi.dst)); in intel_dump_plane_state()
13080 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dump_pipe_config()
13081 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dump_pipe_config()
13087 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", in intel_dump_pipe_config()
13088 crtc->base.base.id, crtc->base.name, in intel_dump_pipe_config()
13089 yesno(pipe_config->hw.enable), context); in intel_dump_pipe_config()
13091 if (!pipe_config->hw.enable) in intel_dump_pipe_config()
13094 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); in intel_dump_pipe_config()
13095 drm_dbg_kms(&dev_priv->drm, in intel_dump_pipe_config()
13097 yesno(pipe_config->hw.active), in intel_dump_pipe_config()
13098 buf, pipe_config->output_types, in intel_dump_pipe_config()
13099 output_formats(pipe_config->output_format)); in intel_dump_pipe_config()
13101 drm_dbg_kms(&dev_priv->drm, in intel_dump_pipe_config()
13103 transcoder_name(pipe_config->cpu_transcoder), in intel_dump_pipe_config()
13104 pipe_config->pipe_bpp, pipe_config->dither); in intel_dump_pipe_config()
13106 drm_dbg_kms(&dev_priv->drm, in intel_dump_pipe_config()
13108 transcoder_name(pipe_config->master_transcoder), in intel_dump_pipe_config()
13109 pipe_config->sync_mode_slaves_mask); in intel_dump_pipe_config()
13111 if (pipe_config->has_pch_encoder) in intel_dump_pipe_config()
13113 pipe_config->fdi_lanes, in intel_dump_pipe_config()
13114 &pipe_config->fdi_m_n); in intel_dump_pipe_config()
13118 pipe_config->lane_count, &pipe_config->dp_m_n); in intel_dump_pipe_config()
13119 if (pipe_config->has_drrs) in intel_dump_pipe_config()
13121 pipe_config->lane_count, in intel_dump_pipe_config()
13122 &pipe_config->dp_m2_n2); in intel_dump_pipe_config()
13125 drm_dbg_kms(&dev_priv->drm, in intel_dump_pipe_config()
13127 pipe_config->has_audio, pipe_config->has_infoframe, in intel_dump_pipe_config()
13128 pipe_config->infoframes.enable); in intel_dump_pipe_config()
13130 if (pipe_config->infoframes.enable & in intel_dump_pipe_config()
13132 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", in intel_dump_pipe_config()
13133 pipe_config->infoframes.gcp); in intel_dump_pipe_config()
13134 if (pipe_config->infoframes.enable & in intel_dump_pipe_config()
13136 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); in intel_dump_pipe_config()
13137 if (pipe_config->infoframes.enable & in intel_dump_pipe_config()
13139 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); in intel_dump_pipe_config()
13140 if (pipe_config->infoframes.enable & in intel_dump_pipe_config()
13142 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); in intel_dump_pipe_config()
13143 if (pipe_config->infoframes.enable & in intel_dump_pipe_config()
13145 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); in intel_dump_pipe_config()
13146 if (pipe_config->infoframes.enable & in intel_dump_pipe_config()
13148 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); in intel_dump_pipe_config()
13149 if (pipe_config->infoframes.enable & in intel_dump_pipe_config()
13151 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); in intel_dump_pipe_config()
13153 drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); in intel_dump_pipe_config()
13154 drm_mode_debug_printmodeline(&pipe_config->hw.mode); in intel_dump_pipe_config()
13155 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n"); in intel_dump_pipe_config()
13156 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode); in intel_dump_pipe_config()
13157 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); in intel_dump_pipe_config()
13158 drm_dbg_kms(&dev_priv->drm, in intel_dump_pipe_config()
13160 pipe_config->port_clock, in intel_dump_pipe_config()
13161 pipe_config->pipe_src_w, pipe_config->pipe_src_h, in intel_dump_pipe_config()
13162 pipe_config->pixel_rate); in intel_dump_pipe_config()
13164 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", in intel_dump_pipe_config()
13165 pipe_config->linetime, pipe_config->ips_linetime); in intel_dump_pipe_config()
13168 drm_dbg_kms(&dev_priv->drm, in intel_dump_pipe_config()
13170 crtc->num_scalers, in intel_dump_pipe_config()
13171 pipe_config->scaler_state.scaler_users, in intel_dump_pipe_config()
13172 pipe_config->scaler_state.scaler_id); in intel_dump_pipe_config()
13175 drm_dbg_kms(&dev_priv->drm, in intel_dump_pipe_config()
13177 pipe_config->gmch_pfit.control, in intel_dump_pipe_config()
13178 pipe_config->gmch_pfit.pgm_ratios, in intel_dump_pipe_config()
13179 pipe_config->gmch_pfit.lvds_border_bits); in intel_dump_pipe_config()
13181 drm_dbg_kms(&dev_priv->drm, in intel_dump_pipe_config()
13183 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), in intel_dump_pipe_config()
13184 enableddisabled(pipe_config->pch_pfit.enabled), in intel_dump_pipe_config()
13185 yesno(pipe_config->pch_pfit.force_thru)); in intel_dump_pipe_config()
13187 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n", in intel_dump_pipe_config()
13188 pipe_config->ips_enabled, pipe_config->double_wide); in intel_dump_pipe_config()
13190 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); in intel_dump_pipe_config()
13193 drm_dbg_kms(&dev_priv->drm, in intel_dump_pipe_config()
13195 pipe_config->cgm_mode, pipe_config->gamma_mode, in intel_dump_pipe_config()
13196 pipe_config->gamma_enable, pipe_config->csc_enable); in intel_dump_pipe_config()
13198 drm_dbg_kms(&dev_priv->drm, in intel_dump_pipe_config()
13200 pipe_config->csc_mode, pipe_config->gamma_mode, in intel_dump_pipe_config()
13201 pipe_config->gamma_enable, pipe_config->csc_enable); in intel_dump_pipe_config()
13203 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", in intel_dump_pipe_config()
13204 transcoder_name(pipe_config->mst_master_transcoder)); in intel_dump_pipe_config()
13211 if (plane->pipe == crtc->pipe) in intel_dump_pipe_config()
13218 struct drm_device *dev = state->base.dev; in check_digital_port_conflicts()
13226 * We're going to peek into connector->state, in check_digital_port_conflicts()
13229 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); in check_digital_port_conflicts()
13242 drm_atomic_get_new_connector_state(&state->base, in check_digital_port_conflicts()
13245 connector_state = connector->state; in check_digital_port_conflicts()
13247 if (!connector_state->best_encoder) in check_digital_port_conflicts()
13250 encoder = to_intel_encoder(connector_state->best_encoder); in check_digital_port_conflicts()
13252 drm_WARN_ON(dev, !connector_state->crtc); in check_digital_port_conflicts()
13254 switch (encoder->type) { in check_digital_port_conflicts()
13263 if (used_ports & BIT(encoder->port)) in check_digital_port_conflicts()
13266 used_ports |= BIT(encoder->port); in check_digital_port_conflicts()
13270 1 << encoder->port; in check_digital_port_conflicts()
13294 crtc_state->hw.enable = crtc_state->uapi.enable; in intel_crtc_copy_uapi_to_hw_state()
13295 crtc_state->hw.active = crtc_state->uapi.active; in intel_crtc_copy_uapi_to_hw_state()
13296 crtc_state->hw.mode = crtc_state->uapi.mode; in intel_crtc_copy_uapi_to_hw_state()
13297 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode; in intel_crtc_copy_uapi_to_hw_state()
13303 crtc_state->uapi.enable = crtc_state->hw.enable; in intel_crtc_copy_hw_to_uapi_state()
13304 crtc_state->uapi.active = crtc_state->hw.active; in intel_crtc_copy_hw_to_uapi_state()
13305 drm_WARN_ON(crtc_state->uapi.crtc->dev, in intel_crtc_copy_hw_to_uapi_state()
13306 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); in intel_crtc_copy_hw_to_uapi_state()
13308 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; in intel_crtc_copy_hw_to_uapi_state()
13311 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, in intel_crtc_copy_hw_to_uapi_state()
13312 crtc_state->hw.degamma_lut); in intel_crtc_copy_hw_to_uapi_state()
13313 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, in intel_crtc_copy_hw_to_uapi_state()
13314 crtc_state->hw.gamma_lut); in intel_crtc_copy_hw_to_uapi_state()
13315 drm_property_replace_blob(&crtc_state->uapi.ctm, in intel_crtc_copy_hw_to_uapi_state()
13316 crtc_state->hw.ctm); in intel_crtc_copy_hw_to_uapi_state()
13322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_prepare_cleared_state()
13323 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_prepare_cleared_state()
13328 return -ENOMEM; in intel_crtc_prepare_cleared_state()
13330 /* free the old crtc_state->hw members */ in intel_crtc_prepare_cleared_state()
13338 saved_state->uapi = crtc_state->uapi; in intel_crtc_prepare_cleared_state()
13339 saved_state->scaler_state = crtc_state->scaler_state; in intel_crtc_prepare_cleared_state()
13340 saved_state->shared_dpll = crtc_state->shared_dpll; in intel_crtc_prepare_cleared_state()
13341 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; in intel_crtc_prepare_cleared_state()
13342 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, in intel_crtc_prepare_cleared_state()
13343 sizeof(saved_state->icl_port_dplls)); in intel_crtc_prepare_cleared_state()
13344 saved_state->crc_enabled = crtc_state->crc_enabled; in intel_crtc_prepare_cleared_state()
13347 saved_state->wm = crtc_state->wm; in intel_crtc_prepare_cleared_state()
13360 struct drm_crtc *crtc = pipe_config->uapi.crtc; in intel_modeset_pipe_config()
13361 struct drm_atomic_state *state = pipe_config->uapi.state; in intel_modeset_pipe_config()
13362 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); in intel_modeset_pipe_config()
13368 pipe_config->cpu_transcoder = in intel_modeset_pipe_config()
13369 (enum transcoder) to_intel_crtc(crtc)->pipe; in intel_modeset_pipe_config()
13376 if (!(pipe_config->hw.adjusted_mode.flags & in intel_modeset_pipe_config()
13378 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; in intel_modeset_pipe_config()
13380 if (!(pipe_config->hw.adjusted_mode.flags & in intel_modeset_pipe_config()
13382 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; in intel_modeset_pipe_config()
13389 base_bpp = pipe_config->pipe_bpp; in intel_modeset_pipe_config()
13399 drm_mode_get_hv_timing(&pipe_config->hw.mode, in intel_modeset_pipe_config()
13400 &pipe_config->pipe_src_w, in intel_modeset_pipe_config()
13401 &pipe_config->pipe_src_h); in intel_modeset_pipe_config()
13405 to_intel_encoder(connector_state->best_encoder); in intel_modeset_pipe_config()
13407 if (connector_state->crtc != crtc) in intel_modeset_pipe_config()
13411 drm_dbg_kms(&i915->drm, in intel_modeset_pipe_config()
13413 return -EINVAL; in intel_modeset_pipe_config()
13420 if (encoder->compute_output_type) in intel_modeset_pipe_config()
13421 pipe_config->output_types |= in intel_modeset_pipe_config()
13422 BIT(encoder->compute_output_type(encoder, pipe_config, in intel_modeset_pipe_config()
13425 pipe_config->output_types |= BIT(encoder->type); in intel_modeset_pipe_config()
13430 pipe_config->port_clock = 0; in intel_modeset_pipe_config()
13431 pipe_config->pixel_multiplier = 1; in intel_modeset_pipe_config()
13434 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode, in intel_modeset_pipe_config()
13443 to_intel_encoder(connector_state->best_encoder); in intel_modeset_pipe_config()
13445 if (connector_state->crtc != crtc) in intel_modeset_pipe_config()
13448 ret = encoder->compute_config(encoder, pipe_config, in intel_modeset_pipe_config()
13451 if (ret != -EDEADLK) in intel_modeset_pipe_config()
13452 drm_dbg_kms(&i915->drm, in intel_modeset_pipe_config()
13461 if (!pipe_config->port_clock) in intel_modeset_pipe_config()
13462 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock in intel_modeset_pipe_config()
13463 * pipe_config->pixel_multiplier; in intel_modeset_pipe_config()
13466 if (ret == -EDEADLK) in intel_modeset_pipe_config()
13469 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n"); in intel_modeset_pipe_config()
13474 if (drm_WARN(&i915->drm, !retry, in intel_modeset_pipe_config()
13476 return -EINVAL; in intel_modeset_pipe_config()
13478 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n"); in intel_modeset_pipe_config()
13483 /* Dithering seems to not pass-through bits correctly when it should, so in intel_modeset_pipe_config()
13487 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && in intel_modeset_pipe_config()
13488 !pipe_config->dither_force_disable; in intel_modeset_pipe_config()
13489 drm_dbg_kms(&i915->drm, in intel_modeset_pipe_config()
13491 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); in intel_modeset_pipe_config()
13500 to_intel_atomic_state(crtc_state->uapi.state); in intel_modeset_pipe_config_late()
13501 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_modeset_pipe_config_late()
13506 for_each_new_connector_in_state(&state->base, connector, in intel_modeset_pipe_config_late()
13509 to_intel_encoder(conn_state->best_encoder); in intel_modeset_pipe_config_late()
13512 if (conn_state->crtc != &crtc->base || in intel_modeset_pipe_config_late()
13513 !encoder->compute_config_late) in intel_modeset_pipe_config_late()
13516 ret = encoder->compute_config_late(encoder, crtc_state, in intel_modeset_pipe_config_late()
13535 diff = abs(clock1 - clock2); in intel_fuzzy_clock_check()
13579 return m_n->tu == m2_n2->tu && in intel_compare_link_m_n()
13580 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, in intel_compare_link_m_n()
13581 m2_n2->gmch_m, m2_n2->gmch_n, exact) && in intel_compare_link_m_n()
13582 intel_compare_m_n(m_n->link_m, m_n->link_n, in intel_compare_link_m_n()
13583 m2_n2->link_m, m2_n2->link_n, exact); in intel_compare_link_m_n()
13610 drm_dbg_kms(&dev_priv->drm, in pipe_config_infoframe_mismatch()
13612 drm_dbg_kms(&dev_priv->drm, "expected:\n"); in pipe_config_infoframe_mismatch()
13613 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); in pipe_config_infoframe_mismatch()
13614 drm_dbg_kms(&dev_priv->drm, "found:\n"); in pipe_config_infoframe_mismatch()
13615 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); in pipe_config_infoframe_mismatch()
13617 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); in pipe_config_infoframe_mismatch()
13618 drm_err(&dev_priv->drm, "expected:\n"); in pipe_config_infoframe_mismatch()
13619 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); in pipe_config_infoframe_mismatch()
13620 drm_err(&dev_priv->drm, "found:\n"); in pipe_config_infoframe_mismatch()
13621 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); in pipe_config_infoframe_mismatch()
13635 drm_dbg_kms(&dev_priv->drm, in pipe_config_dp_vsc_sdp_mismatch()
13637 drm_dbg_kms(&dev_priv->drm, "expected:\n"); in pipe_config_dp_vsc_sdp_mismatch()
13638 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); in pipe_config_dp_vsc_sdp_mismatch()
13639 drm_dbg_kms(&dev_priv->drm, "found:\n"); in pipe_config_dp_vsc_sdp_mismatch()
13640 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); in pipe_config_dp_vsc_sdp_mismatch()
13642 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); in pipe_config_dp_vsc_sdp_mismatch()
13643 drm_err(&dev_priv->drm, "expected:\n"); in pipe_config_dp_vsc_sdp_mismatch()
13644 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); in pipe_config_dp_vsc_sdp_mismatch()
13645 drm_err(&dev_priv->drm, "found:\n"); in pipe_config_dp_vsc_sdp_mismatch()
13646 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); in pipe_config_dp_vsc_sdp_mismatch()
13654 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in pipe_config_mismatch()
13663 drm_dbg_kms(&i915->drm, in pipe_config_mismatch()
13665 crtc->base.base.id, crtc->base.name, name, &vaf); in pipe_config_mismatch()
13667 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", in pipe_config_mismatch()
13668 crtc->base.base.id, crtc->base.name, name, &vaf); in pipe_config_mismatch()
13675 if (dev_priv->params.fastboot != -1) in fastboot_enabled()
13676 return dev_priv->params.fastboot; in fastboot_enabled()
13695 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); in intel_pipe_config_compare()
13696 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_pipe_config_compare()
13700 current_config->inherited && !pipe_config->inherited; in intel_pipe_config_compare()
13703 drm_dbg_kms(&dev_priv->drm, in intel_pipe_config_compare()
13709 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
13712 current_config->name, \ in intel_pipe_config_compare()
13713 pipe_config->name); \ in intel_pipe_config_compare()
13719 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
13722 current_config->name, \ in intel_pipe_config_compare()
13723 pipe_config->name); \ in intel_pipe_config_compare()
13729 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
13732 yesno(current_config->name), \ in intel_pipe_config_compare()
13733 yesno(pipe_config->name)); \ in intel_pipe_config_compare()
13744 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ in intel_pipe_config_compare()
13749 yesno(current_config->name), \ in intel_pipe_config_compare()
13750 yesno(pipe_config->name)); \ in intel_pipe_config_compare()
13756 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
13759 current_config->name, \ in intel_pipe_config_compare()
13760 pipe_config->name); \ in intel_pipe_config_compare()
13766 if (!intel_compare_link_m_n(¤t_config->name, \ in intel_pipe_config_compare()
13767 &pipe_config->name,\ in intel_pipe_config_compare()
13772 current_config->name.tu, \ in intel_pipe_config_compare()
13773 current_config->name.gmch_m, \ in intel_pipe_config_compare()
13774 current_config->name.gmch_n, \ in intel_pipe_config_compare()
13775 current_config->name.link_m, \ in intel_pipe_config_compare()
13776 current_config->name.link_n, \ in intel_pipe_config_compare()
13777 pipe_config->name.tu, \ in intel_pipe_config_compare()
13778 pipe_config->name.gmch_m, \ in intel_pipe_config_compare()
13779 pipe_config->name.gmch_n, \ in intel_pipe_config_compare()
13780 pipe_config->name.link_m, \ in intel_pipe_config_compare()
13781 pipe_config->name.link_n); \ in intel_pipe_config_compare()
13792 if (!intel_compare_link_m_n(¤t_config->name, \ in intel_pipe_config_compare()
13793 &pipe_config->name, !fastset) && \ in intel_pipe_config_compare()
13794 !intel_compare_link_m_n(¤t_config->alt_name, \ in intel_pipe_config_compare()
13795 &pipe_config->name, !fastset)) { \ in intel_pipe_config_compare()
13800 current_config->name.tu, \ in intel_pipe_config_compare()
13801 current_config->name.gmch_m, \ in intel_pipe_config_compare()
13802 current_config->name.gmch_n, \ in intel_pipe_config_compare()
13803 current_config->name.link_m, \ in intel_pipe_config_compare()
13804 current_config->name.link_n, \ in intel_pipe_config_compare()
13805 current_config->alt_name.tu, \ in intel_pipe_config_compare()
13806 current_config->alt_name.gmch_m, \ in intel_pipe_config_compare()
13807 current_config->alt_name.gmch_n, \ in intel_pipe_config_compare()
13808 current_config->alt_name.link_m, \ in intel_pipe_config_compare()
13809 current_config->alt_name.link_n, \ in intel_pipe_config_compare()
13810 pipe_config->name.tu, \ in intel_pipe_config_compare()
13811 pipe_config->name.gmch_m, \ in intel_pipe_config_compare()
13812 pipe_config->name.gmch_n, \ in intel_pipe_config_compare()
13813 pipe_config->name.link_m, \ in intel_pipe_config_compare()
13814 pipe_config->name.link_n); \ in intel_pipe_config_compare()
13820 if ((current_config->name ^ pipe_config->name) & (mask)) { \ in intel_pipe_config_compare()
13824 current_config->name & (mask), \ in intel_pipe_config_compare()
13825 pipe_config->name & (mask)); \ in intel_pipe_config_compare()
13831 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ in intel_pipe_config_compare()
13834 current_config->name, \ in intel_pipe_config_compare()
13835 pipe_config->name); \ in intel_pipe_config_compare()
13841 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ in intel_pipe_config_compare()
13842 &pipe_config->infoframes.name)) { \ in intel_pipe_config_compare()
13844 ¤t_config->infoframes.name, \ in intel_pipe_config_compare()
13845 &pipe_config->infoframes.name); \ in intel_pipe_config_compare()
13851 if (!current_config->has_psr && !pipe_config->has_psr && \ in intel_pipe_config_compare()
13852 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ in intel_pipe_config_compare()
13853 &pipe_config->infoframes.name)) { \ in intel_pipe_config_compare()
13855 ¤t_config->infoframes.name, \ in intel_pipe_config_compare()
13856 &pipe_config->infoframes.name); \ in intel_pipe_config_compare()
13862 if (current_config->name1 != pipe_config->name1) { \ in intel_pipe_config_compare()
13865 current_config->name1, \ in intel_pipe_config_compare()
13866 pipe_config->name1); \ in intel_pipe_config_compare()
13869 if (!intel_color_lut_equal(current_config->name2, \ in intel_pipe_config_compare()
13870 pipe_config->name2, pipe_config->name1, \ in intel_pipe_config_compare()
13880 ((current_config->quirks | pipe_config->quirks) & (quirk)) in intel_pipe_config_compare()
13894 if (current_config->has_drrs) in intel_pipe_config_compare()
13960 if (current_config->pch_pfit.enabled) { in intel_pipe_config_compare()
14001 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); in intel_pipe_config_compare()
14065 if (pipe_config->has_pch_encoder) { in intel_pipe_config_sanity_check()
14067 &pipe_config->fdi_m_n); in intel_pipe_config_sanity_check()
14068 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; in intel_pipe_config_sanity_check()
14074 drm_WARN(&dev_priv->drm, in intel_pipe_config_sanity_check()
14084 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in verify_wm_state()
14093 const enum pipe pipe = crtc->pipe; in verify_wm_state()
14096 if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active) in verify_wm_state()
14103 skl_pipe_wm_get_hw_state(crtc, &hw->wm); in verify_wm_state()
14104 sw_wm = &new_crtc_state->wm.skl.optimal; in verify_wm_state()
14106 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv); in verify_wm_state()
14111 hw_enabled_slices != dev_priv->dbuf.enabled_slices) in verify_wm_state()
14112 drm_err(&dev_priv->drm, in verify_wm_state()
14114 dev_priv->dbuf.enabled_slices, in verify_wm_state()
14121 hw_plane_wm = &hw->wm.planes[plane]; in verify_wm_state()
14122 sw_plane_wm = &sw_wm->planes[plane]; in verify_wm_state()
14126 if (skl_wm_level_equals(&hw_plane_wm->wm[level], in verify_wm_state()
14127 &sw_plane_wm->wm[level]) || in verify_wm_state()
14128 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level], in verify_wm_state()
14129 &sw_plane_wm->sagv_wm0))) in verify_wm_state()
14132 drm_err(&dev_priv->drm, in verify_wm_state()
14135 sw_plane_wm->wm[level].plane_en, in verify_wm_state()
14136 sw_plane_wm->wm[level].plane_res_b, in verify_wm_state()
14137 sw_plane_wm->wm[level].plane_res_l, in verify_wm_state()
14138 hw_plane_wm->wm[level].plane_en, in verify_wm_state()
14139 hw_plane_wm->wm[level].plane_res_b, in verify_wm_state()
14140 hw_plane_wm->wm[level].plane_res_l); in verify_wm_state()
14143 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, in verify_wm_state()
14144 &sw_plane_wm->trans_wm)) { in verify_wm_state()
14145 drm_err(&dev_priv->drm, in verify_wm_state()
14148 sw_plane_wm->trans_wm.plane_en, in verify_wm_state()
14149 sw_plane_wm->trans_wm.plane_res_b, in verify_wm_state()
14150 sw_plane_wm->trans_wm.plane_res_l, in verify_wm_state()
14151 hw_plane_wm->trans_wm.plane_en, in verify_wm_state()
14152 hw_plane_wm->trans_wm.plane_res_b, in verify_wm_state()
14153 hw_plane_wm->trans_wm.plane_res_l); in verify_wm_state()
14157 hw_ddb_entry = &hw->ddb_y[plane]; in verify_wm_state()
14158 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane]; in verify_wm_state()
14161 drm_err(&dev_priv->drm, in verify_wm_state()
14164 sw_ddb_entry->start, sw_ddb_entry->end, in verify_wm_state()
14165 hw_ddb_entry->start, hw_ddb_entry->end); in verify_wm_state()
14178 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR]; in verify_wm_state()
14179 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; in verify_wm_state()
14183 if (skl_wm_level_equals(&hw_plane_wm->wm[level], in verify_wm_state()
14184 &sw_plane_wm->wm[level]) || in verify_wm_state()
14185 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level], in verify_wm_state()
14186 &sw_plane_wm->sagv_wm0))) in verify_wm_state()
14189 drm_err(&dev_priv->drm, in verify_wm_state()
14192 sw_plane_wm->wm[level].plane_en, in verify_wm_state()
14193 sw_plane_wm->wm[level].plane_res_b, in verify_wm_state()
14194 sw_plane_wm->wm[level].plane_res_l, in verify_wm_state()
14195 hw_plane_wm->wm[level].plane_en, in verify_wm_state()
14196 hw_plane_wm->wm[level].plane_res_b, in verify_wm_state()
14197 hw_plane_wm->wm[level].plane_res_l); in verify_wm_state()
14200 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, in verify_wm_state()
14201 &sw_plane_wm->trans_wm)) { in verify_wm_state()
14202 drm_err(&dev_priv->drm, in verify_wm_state()
14205 sw_plane_wm->trans_wm.plane_en, in verify_wm_state()
14206 sw_plane_wm->trans_wm.plane_res_b, in verify_wm_state()
14207 sw_plane_wm->trans_wm.plane_res_l, in verify_wm_state()
14208 hw_plane_wm->trans_wm.plane_en, in verify_wm_state()
14209 hw_plane_wm->trans_wm.plane_res_b, in verify_wm_state()
14210 hw_plane_wm->trans_wm.plane_res_l); in verify_wm_state()
14214 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR]; in verify_wm_state()
14215 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR]; in verify_wm_state()
14218 drm_err(&dev_priv->drm, in verify_wm_state()
14221 sw_ddb_entry->start, sw_ddb_entry->end, in verify_wm_state()
14222 hw_ddb_entry->start, hw_ddb_entry->end); in verify_wm_state()
14237 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { in verify_connector_state()
14238 struct drm_encoder *encoder = connector->encoder; in verify_connector_state()
14241 if (new_conn_state->crtc != &crtc->base) in verify_connector_state()
14249 I915_STATE_WARN(new_conn_state->best_encoder != encoder, in verify_connector_state()
14262 for_each_intel_encoder(&dev_priv->drm, encoder) { in verify_encoder_state()
14266 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", in verify_encoder_state()
14267 encoder->base.base.id, in verify_encoder_state()
14268 encoder->base.name); in verify_encoder_state()
14270 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, in verify_encoder_state()
14272 if (old_conn_state->best_encoder == &encoder->base) in verify_encoder_state()
14275 if (new_conn_state->best_encoder != &encoder->base) in verify_encoder_state()
14279 I915_STATE_WARN(new_conn_state->crtc != in verify_encoder_state()
14280 encoder->base.crtc, in verify_encoder_state()
14287 I915_STATE_WARN(!!encoder->base.crtc != enabled, in verify_encoder_state()
14290 !!encoder->base.crtc, enabled); in verify_encoder_state()
14292 if (!encoder->base.crtc) { in verify_encoder_state()
14295 active = encoder->get_hw_state(encoder, &pipe); in verify_encoder_state()
14308 struct drm_device *dev = crtc->base.dev; in verify_crtc_state()
14312 struct drm_atomic_state *state = old_crtc_state->uapi.state; in verify_crtc_state()
14314 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); in verify_crtc_state()
14317 old_crtc_state->uapi.state = state; in verify_crtc_state()
14319 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, in verify_crtc_state()
14320 crtc->base.name); in verify_crtc_state()
14322 pipe_config->hw.enable = new_crtc_state->hw.enable; in verify_crtc_state()
14324 pipe_config->hw.active = in verify_crtc_state()
14325 dev_priv->display.get_pipe_config(crtc, pipe_config); in verify_crtc_state()
14328 if (IS_I830(dev_priv) && pipe_config->hw.active) in verify_crtc_state()
14329 pipe_config->hw.active = new_crtc_state->hw.active; in verify_crtc_state()
14331 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active, in verify_crtc_state()
14334 new_crtc_state->hw.active, pipe_config->hw.active); in verify_crtc_state()
14336 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active, in verify_crtc_state()
14339 new_crtc_state->hw.active, crtc->active); in verify_crtc_state()
14341 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { in verify_crtc_state()
14345 active = encoder->get_hw_state(encoder, &pipe); in verify_crtc_state()
14346 I915_STATE_WARN(active != new_crtc_state->hw.active, in verify_crtc_state()
14348 encoder->base.base.id, active, in verify_crtc_state()
14349 new_crtc_state->hw.active); in verify_crtc_state()
14351 I915_STATE_WARN(active && crtc->pipe != pipe, in verify_crtc_state()
14356 encoder->get_config(encoder, pipe_config); in verify_crtc_state()
14361 if (!new_crtc_state->hw.active) in verify_crtc_state()
14383 assert_plane(plane, plane_state->planar_slave || in intel_verify_planes()
14384 plane_state->uapi.visible); in intel_verify_planes()
14399 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); in verify_single_dpll_state()
14401 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state); in verify_single_dpll_state()
14403 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { in verify_single_dpll_state()
14404 I915_STATE_WARN(!pll->on && pll->active_mask, in verify_single_dpll_state()
14406 I915_STATE_WARN(pll->on && !pll->active_mask, in verify_single_dpll_state()
14408 I915_STATE_WARN(pll->on != active, in verify_single_dpll_state()
14410 pll->on, active); in verify_single_dpll_state()
14414 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, in verify_single_dpll_state()
14416 pll->active_mask, pll->state.crtc_mask); in verify_single_dpll_state()
14421 crtc_mask = drm_crtc_mask(&crtc->base); in verify_single_dpll_state()
14423 if (new_crtc_state->hw.active) in verify_single_dpll_state()
14424 I915_STATE_WARN(!(pll->active_mask & crtc_mask), in verify_single_dpll_state()
14426 pipe_name(crtc->pipe), pll->active_mask); in verify_single_dpll_state()
14428 I915_STATE_WARN(pll->active_mask & crtc_mask, in verify_single_dpll_state()
14430 pipe_name(crtc->pipe), pll->active_mask); in verify_single_dpll_state()
14432 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), in verify_single_dpll_state()
14434 crtc_mask, pll->state.crtc_mask); in verify_single_dpll_state()
14436 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, in verify_single_dpll_state()
14447 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in verify_shared_dpll_state()
14449 if (new_crtc_state->shared_dpll) in verify_shared_dpll_state()
14450 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); in verify_shared_dpll_state()
14452 if (old_crtc_state->shared_dpll && in verify_shared_dpll_state()
14453 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { in verify_shared_dpll_state()
14454 unsigned int crtc_mask = drm_crtc_mask(&crtc->base); in verify_shared_dpll_state()
14455 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; in verify_shared_dpll_state()
14457 I915_STATE_WARN(pll->active_mask & crtc_mask, in verify_shared_dpll_state()
14459 pipe_name(crtc->pipe)); in verify_shared_dpll_state()
14460 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, in verify_shared_dpll_state()
14462 pipe_name(crtc->pipe)); in verify_shared_dpll_state()
14472 if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) in intel_modeset_verify_crtc()
14486 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) in verify_disabled_dpll_state()
14488 &dev_priv->dpll.shared_dplls[i], in verify_disabled_dpll_state()
14504 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_update_active_timings()
14505 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_update_active_timings()
14507 &crtc_state->hw.adjusted_mode; in intel_crtc_update_active_timings()
14509 drm_calc_timestamping_constants(&crtc->base, adjusted_mode); in intel_crtc_update_active_timings()
14511 crtc->mode_flags = crtc_state->mode_flags; in intel_crtc_update_active_timings()
14516 * On most platforms it starts counting from vtotal-1 on the in intel_crtc_update_active_timings()
14520 * last active line), the scanline counter will read vblank_start-1. in intel_crtc_update_active_timings()
14523 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 in intel_crtc_update_active_timings()
14543 vtotal = adjusted_mode->crtc_vtotal; in intel_crtc_update_active_timings()
14544 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) in intel_crtc_update_active_timings()
14547 crtc->scanline_offset = vtotal - 1; in intel_crtc_update_active_timings()
14550 crtc->scanline_offset = 2; in intel_crtc_update_active_timings()
14552 crtc->scanline_offset = 1; in intel_crtc_update_active_timings()
14558 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_clear_plls()
14563 if (!dev_priv->display.crtc_compute_clock) in intel_modeset_clear_plls()
14591 if (!crtc_state->hw.active || in hsw_mode_set_planes_workaround()
14600 first_pipe = crtc->pipe; in hsw_mode_set_planes_workaround()
14609 for_each_intel_crtc(state->base.dev, crtc) { in hsw_mode_set_planes_workaround()
14610 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in hsw_mode_set_planes_workaround()
14614 crtc_state->hsw_workaround_pipe = INVALID_PIPE; in hsw_mode_set_planes_workaround()
14616 if (!crtc_state->hw.active || in hsw_mode_set_planes_workaround()
14624 enabled_pipe = crtc->pipe; in hsw_mode_set_planes_workaround()
14628 first_crtc_state->hsw_workaround_pipe = enabled_pipe; in hsw_mode_set_planes_workaround()
14630 other_crtc_state->hsw_workaround_pipe = first_pipe; in hsw_mode_set_planes_workaround()
14643 if (crtc_state->hw.active) in intel_calc_active_pipes()
14644 active_pipes |= BIT(crtc->pipe); in intel_calc_active_pipes()
14646 active_pipes &= ~BIT(crtc->pipe); in intel_calc_active_pipes()
14654 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_checks()
14656 state->modeset = true; in intel_modeset_checks()
14666 * phase. The code here should be run after the per-crtc and per-plane 'check'
14671 struct drm_device *dev = state->base.dev; in calc_watermark_data()
14674 /* Is there platform-specific watermark information to calculate? */ in calc_watermark_data()
14675 if (dev_priv->display.compute_global_watermarks) in calc_watermark_data()
14676 return dev_priv->display.compute_global_watermarks(state); in calc_watermark_data()
14687 new_crtc_state->uapi.mode_changed = false; in intel_crtc_check_fastset()
14688 new_crtc_state->update_pipe = true; in intel_crtc_check_fastset()
14702 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; in intel_crtc_copy_fastset()
14703 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; in intel_crtc_copy_fastset()
14704 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; in intel_crtc_copy_fastset()
14705 new_crtc_state->has_drrs = old_crtc_state->has_drrs; in intel_crtc_copy_fastset()
14712 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_crtc_add_planes_to_state()
14715 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { in intel_crtc_add_planes_to_state()
14718 if ((plane_ids_mask & BIT(plane->id)) == 0) in intel_crtc_add_planes_to_state()
14739 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_check_planes()
14753 drm_dbg_atomic(&dev_priv->drm, in intel_atomic_check_planes()
14755 plane->base.base.id, plane->base.name); in intel_atomic_check_planes()
14776 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); in intel_atomic_check_planes()
14777 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); in intel_atomic_check_planes()
14799 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_check_cdclk()
14824 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) in intel_atomic_check_cdclk()
14827 ret = dev_priv->display.bw_calc_min_cdclk(state); in intel_atomic_check_cdclk()
14837 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); in intel_atomic_check_cdclk()
14842 if (new_bw_state->min_cdclk > min_cdclk) in intel_atomic_check_cdclk()
14857 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_atomic_check_crtcs()
14859 drm_dbg_atomic(&i915->drm, in intel_atomic_check_crtcs()
14861 crtc->base.base.id, crtc->base.name); in intel_atomic_check_crtcs()
14877 if (new_crtc_state->hw.enable && in intel_cpu_transcoders_need_modeset()
14878 transcoders & BIT(new_crtc_state->cpu_transcoder) && in intel_cpu_transcoders_need_modeset()
14887 * intel_atomic_check - validate state object
14903 if (new_crtc_state->inherited != old_crtc_state->inherited) in intel_atomic_check()
14904 new_crtc_state->uapi.mode_changed = true; in intel_atomic_check()
14907 ret = drm_atomic_helper_check_modeset(dev, &state->base); in intel_atomic_check()
14924 if (!new_crtc_state->hw.enable) in intel_atomic_check()
14956 if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state)) in intel_atomic_check()
14960 enum transcoder master = new_crtc_state->mst_master_transcoder; in intel_atomic_check()
14963 new_crtc_state->uapi.mode_changed = true; in intel_atomic_check()
14964 new_crtc_state->update_pipe = false; in intel_atomic_check()
14969 u8 trans = new_crtc_state->sync_mode_slaves_mask; in intel_atomic_check()
14971 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) in intel_atomic_check()
14972 trans |= BIT(new_crtc_state->master_transcoder); in intel_atomic_check()
14975 new_crtc_state->uapi.mode_changed = true; in intel_atomic_check()
14976 new_crtc_state->update_pipe = false; in intel_atomic_check()
14988 if (!new_crtc_state->update_pipe) in intel_atomic_check()
14995 drm_dbg_kms(&dev_priv->drm, in intel_atomic_check()
14997 ret = -EINVAL; in intel_atomic_check()
15001 ret = drm_dp_mst_atomic_check(&state->base); in intel_atomic_check()
15012 * if state->modeset==true. Hence distrust_bios_wm==true && in intel_atomic_check()
15013 * state->modeset==false is an invalid combination which in intel_atomic_check()
15020 if (dev_priv->wm.distrust_bios_wm) in intel_atomic_check()
15055 !new_crtc_state->update_pipe) in intel_atomic_check()
15066 if (ret == -EDEADLK) in intel_atomic_check()
15086 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); in intel_atomic_prepare_commit()
15093 if (mode_changed || crtc_state->update_pipe || in intel_atomic_prepare_commit()
15094 crtc_state->uapi.color_mgmt_changed) { in intel_atomic_prepare_commit()
15104 struct drm_device *dev = crtc->base.dev; in intel_crtc_get_vblank_counter()
15105 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)]; in intel_crtc_get_vblank_counter()
15107 if (!vblank->max_vblank_count) in intel_crtc_get_vblank_counter()
15108 return (u32)drm_crtc_accurate_vblank_count(&crtc->base); in intel_crtc_get_vblank_counter()
15110 return crtc->base.funcs->get_vblank_counter(&crtc->base); in intel_crtc_get_vblank_counter()
15116 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_arm_fifo_underrun()
15118 if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes) in intel_crtc_arm_fifo_underrun()
15119 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); in intel_crtc_arm_fifo_underrun()
15121 if (crtc_state->has_pch_encoder) { in intel_crtc_arm_fifo_underrun()
15132 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); in intel_pipe_fastset()
15133 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_pipe_fastset()
15149 if (new_crtc_state->pch_pfit.enabled) in intel_pipe_fastset()
15152 if (new_crtc_state->pch_pfit.enabled) in intel_pipe_fastset()
15154 else if (old_crtc_state->pch_pfit.enabled) in intel_pipe_fastset()
15177 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in commit_pipe_config()
15189 if (new_crtc_state->uapi.color_mgmt_changed || in commit_pipe_config()
15190 new_crtc_state->update_pipe) in commit_pipe_config()
15199 if (new_crtc_state->update_pipe) in commit_pipe_config()
15205 if (dev_priv->display.atomic_update_watermarks) in commit_pipe_config()
15206 dev_priv->display.atomic_update_watermarks(state, crtc); in commit_pipe_config()
15212 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_enable_crtc()
15221 dev_priv->display.crtc_enable(state, crtc); in intel_enable_crtc()
15223 /* vblanks work again, re-enable pipe CRC. */ in intel_enable_crtc()
15230 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_update_crtc()
15238 if (new_crtc_state->preload_luts && in intel_update_crtc()
15239 (new_crtc_state->uapi.color_mgmt_changed || in intel_update_crtc()
15240 new_crtc_state->update_pipe)) in intel_update_crtc()
15245 if (new_crtc_state->update_pipe) in intel_update_crtc()
15249 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc) in intel_update_crtc()
15272 if (new_crtc_state->update_pipe && !modeset && in intel_update_crtc()
15273 old_crtc_state->inherited) in intel_update_crtc()
15283 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_old_crtc_state_disables()
15293 dev_priv->display.crtc_disable(state, crtc); in intel_old_crtc_state_disables()
15294 crtc->active = false; in intel_old_crtc_state_disables()
15299 if (!new_crtc_state->hw.active && in intel_old_crtc_state_disables()
15301 dev_priv->display.initial_watermarks) in intel_old_crtc_state_disables()
15302 dev_priv->display.initial_watermarks(state, crtc); in intel_old_crtc_state_disables()
15318 if (!old_crtc_state->hw.active) in intel_commit_modeset_disables()
15333 handled |= BIT(crtc->pipe); in intel_commit_modeset_disables()
15340 (handled & BIT(crtc->pipe))) in intel_commit_modeset_disables()
15344 if (old_crtc_state->hw.active) in intel_commit_modeset_disables()
15357 if (!new_crtc_state->hw.active) in intel_commit_modeset_enables()
15367 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in skl_commit_modeset_enables()
15375 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
15377 if (!new_crtc_state->hw.active) in skl_commit_modeset_enables()
15382 entries[pipe] = old_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
15401 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
15406 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
15410 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
15421 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
15422 &old_crtc_state->wm.skl.ddb) && in skl_commit_modeset_enables()
15435 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
15454 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
15468 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
15473 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
15476 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
15482 drm_WARN_ON(&dev_priv->drm, modeset_pipes); in skl_commit_modeset_enables()
15483 drm_WARN_ON(&dev_priv->drm, update_pipes); in skl_commit_modeset_enables()
15491 freed = llist_del_all(&dev_priv->atomic_helper.free_list); in intel_atomic_helper_free_state()
15493 drm_atomic_state_put(&state->base); in intel_atomic_helper_free_state()
15507 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); in intel_atomic_commit_fence_wait()
15512 prepare_to_wait(&intel_state->commit_ready.wait, in intel_atomic_commit_fence_wait()
15514 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags, in intel_atomic_commit_fence_wait()
15519 if (i915_sw_fence_done(&intel_state->commit_ready) || in intel_atomic_commit_fence_wait()
15520 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags)) in intel_atomic_commit_fence_wait()
15525 finish_wait(&intel_state->commit_ready.wait, &wait_fence); in intel_atomic_commit_fence_wait()
15526 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags, in intel_atomic_commit_fence_wait()
15546 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_atomic_cleanup_work()
15549 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); in intel_atomic_cleanup_work()
15550 drm_atomic_helper_commit_cleanup_done(&state->base); in intel_atomic_cleanup_work()
15551 drm_atomic_state_put(&state->base); in intel_atomic_cleanup_work()
15558 struct drm_device *dev = state->base.dev; in intel_atomic_commit_tail()
15568 drm_atomic_helper_wait_for_dependencies(&state->base); in intel_atomic_commit_tail()
15570 if (state->modeset) in intel_atomic_commit_tail()
15576 new_crtc_state->update_pipe) { in intel_atomic_commit_tail()
15578 put_domains[crtc->pipe] = in intel_atomic_commit_tail()
15585 /* FIXME: Eventually get rid of our crtc->config pointer */ in intel_atomic_commit_tail()
15587 crtc->config = new_crtc_state; in intel_atomic_commit_tail()
15589 if (state->modeset) { in intel_atomic_commit_tail()
15590 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); in intel_atomic_commit_tail()
15604 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { in intel_atomic_commit_tail()
15605 spin_lock_irq(&dev->event_lock); in intel_atomic_commit_tail()
15606 drm_crtc_send_vblank_event(&crtc->base, in intel_atomic_commit_tail()
15607 new_crtc_state->uapi.event); in intel_atomic_commit_tail()
15608 spin_unlock_irq(&dev->event_lock); in intel_atomic_commit_tail()
15610 new_crtc_state->uapi.event = NULL; in intel_atomic_commit_tail()
15614 if (state->modeset) in intel_atomic_commit_tail()
15620 dev_priv->display.commit_modeset_enables(state); in intel_atomic_commit_tail()
15622 if (state->modeset) { in intel_atomic_commit_tail()
15631 * - wrap the optimization/post_plane_update stuff into a per-crtc work. in intel_atomic_commit_tail()
15632 * - schedule that vblank worker _before_ calling hw_done in intel_atomic_commit_tail()
15633 * - at the start of commit_tail, cancel it _synchrously in intel_atomic_commit_tail()
15634 * - switch over to the vblank wait helper in the core after that since in intel_atomic_commit_tail()
15637 drm_atomic_helper_wait_for_flip_done(dev, &state->base); in intel_atomic_commit_tail()
15640 if (new_crtc_state->hw.active && in intel_atomic_commit_tail()
15642 !new_crtc_state->preload_luts && in intel_atomic_commit_tail()
15643 (new_crtc_state->uapi.color_mgmt_changed || in intel_atomic_commit_tail()
15644 new_crtc_state->update_pipe)) in intel_atomic_commit_tail()
15650 * optimal watermarks on platforms that need two-step watermark in intel_atomic_commit_tail()
15659 * So re-enable underrun reporting after some planes get enabled. in intel_atomic_commit_tail()
15666 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); in intel_atomic_commit_tail()
15668 if (dev_priv->display.optimize_watermarks) in intel_atomic_commit_tail()
15669 dev_priv->display.optimize_watermarks(state, crtc); in intel_atomic_commit_tail()
15687 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); in intel_atomic_commit_tail()
15694 if (state->modeset) in intel_atomic_commit_tail()
15699 drm_atomic_helper_commit_hw_done(&state->base); in intel_atomic_commit_tail()
15701 if (state->modeset) { in intel_atomic_commit_tail()
15705 * so enable debugging for the next modeset - and hope we catch in intel_atomic_commit_tail()
15708 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); in intel_atomic_commit_tail()
15711 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); in intel_atomic_commit_tail()
15716 * are executed inline. For out-of-line asynchronous modesets/flips, in intel_atomic_commit_tail()
15721 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); in intel_atomic_commit_tail()
15722 queue_work(system_highpri_wq, &state->base.commit_work); in intel_atomic_commit_tail()
15747 &to_i915(state->base.dev)->atomic_helper; in intel_atomic_commit_ready()
15749 if (llist_add(&state->freed, &helper->free_list)) in intel_atomic_commit_ready()
15750 schedule_work(&helper->free_work); in intel_atomic_commit_ready()
15766 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), in intel_atomic_track_fbs()
15767 to_intel_frontbuffer(new_plane_state->hw.fb), in intel_atomic_track_fbs()
15768 plane->frontbuffer_bit); in intel_atomic_track_fbs()
15779 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); in intel_atomic_commit()
15781 drm_atomic_state_get(&state->base); in intel_atomic_commit()
15782 i915_sw_fence_init(&state->commit_ready, in intel_atomic_commit()
15793 * Unset state->legacy_cursor_update before the call to in intel_atomic_commit()
15802 if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) { in intel_atomic_commit()
15808 if (new_crtc_state->wm.need_postvbl_update || in intel_atomic_commit()
15809 new_crtc_state->update_wm_post) in intel_atomic_commit()
15810 state->base.legacy_cursor_update = false; in intel_atomic_commit()
15815 drm_dbg_atomic(&dev_priv->drm, in intel_atomic_commit()
15817 i915_sw_fence_commit(&state->commit_ready); in intel_atomic_commit()
15818 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); in intel_atomic_commit()
15822 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); in intel_atomic_commit()
15824 ret = drm_atomic_helper_swap_state(&state->base, true); in intel_atomic_commit()
15833 i915_sw_fence_commit(&state->commit_ready); in intel_atomic_commit()
15838 drm_atomic_helper_cleanup_planes(dev, &state->base); in intel_atomic_commit()
15839 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); in intel_atomic_commit()
15842 dev_priv->wm.distrust_bios_wm = false; in intel_atomic_commit()
15846 drm_atomic_state_get(&state->base); in intel_atomic_commit()
15847 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); in intel_atomic_commit()
15849 i915_sw_fence_commit(&state->commit_ready); in intel_atomic_commit()
15850 if (nonblock && state->modeset) { in intel_atomic_commit()
15851 queue_work(dev_priv->modeset_wq, &state->base.commit_work); in intel_atomic_commit()
15853 queue_work(dev_priv->flip_wq, &state->base.commit_work); in intel_atomic_commit()
15855 if (state->modeset) in intel_atomic_commit()
15856 flush_workqueue(dev_priv->modeset_wq); in intel_atomic_commit()
15874 struct i915_request *rq = wait->request; in do_rps_boost()
15885 drm_crtc_vblank_put(wait->crtc); in do_rps_boost()
15887 list_del(&wait->wait.entry); in do_rps_boost()
15900 if (INTEL_GEN(to_i915(crtc->dev)) < 6) in add_rps_boost_after_vblank()
15912 wait->request = to_request(dma_fence_get(fence)); in add_rps_boost_after_vblank()
15913 wait->crtc = crtc; in add_rps_boost_after_vblank()
15915 wait->wait.func = do_rps_boost; in add_rps_boost_after_vblank()
15916 wait->wait.flags = 0; in add_rps_boost_after_vblank()
15918 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait); in add_rps_boost_after_vblank()
15923 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_plane_pin_fb()
15924 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in intel_plane_pin_fb()
15925 struct drm_framebuffer *fb = plane_state->hw.fb; in intel_plane_pin_fb()
15928 if (plane->id == PLANE_CURSOR && in intel_plane_pin_fb()
15929 INTEL_INFO(dev_priv)->display.cursor_needs_physical) { in intel_plane_pin_fb()
15940 &plane_state->view, in intel_plane_pin_fb()
15942 &plane_state->flags); in intel_plane_pin_fb()
15946 plane_state->vma = vma; in intel_plane_pin_fb()
15955 vma = fetch_and_zero(&old_plane_state->vma); in intel_plane_unpin_fb()
15957 intel_unpin_fb_vma(vma, old_plane_state->flags); in intel_plane_unpin_fb()
15970 * intel_prepare_plane_fb - Prepare fb for usage on plane
15989 to_intel_atomic_state(new_plane_state->uapi.state); in intel_prepare_plane_fb()
15990 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in intel_prepare_plane_fb()
15993 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb); in intel_prepare_plane_fb()
15994 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb); in intel_prepare_plane_fb()
16000 to_intel_crtc(old_plane_state->hw.crtc)); in intel_prepare_plane_fb()
16014 ret = i915_sw_fence_await_reservation(&state->commit_ready, in intel_prepare_plane_fb()
16015 old_obj->base.resv, NULL, in intel_prepare_plane_fb()
16023 if (new_plane_state->uapi.fence) { /* explicit fencing */ in intel_prepare_plane_fb()
16024 ret = i915_sw_fence_await_dma_fence(&state->commit_ready, in intel_prepare_plane_fb()
16025 new_plane_state->uapi.fence, in intel_prepare_plane_fb()
16048 if (!new_plane_state->uapi.fence) { /* implicit fencing */ in intel_prepare_plane_fb()
16051 ret = i915_sw_fence_await_reservation(&state->commit_ready, in intel_prepare_plane_fb()
16052 obj->base.resv, NULL, in intel_prepare_plane_fb()
16059 fence = dma_resv_get_excl_rcu(obj->base.resv); in intel_prepare_plane_fb()
16061 add_rps_boost_after_vblank(new_plane_state->hw.crtc, in intel_prepare_plane_fb()
16066 add_rps_boost_after_vblank(new_plane_state->hw.crtc, in intel_prepare_plane_fb()
16067 new_plane_state->uapi.fence); in intel_prepare_plane_fb()
16078 if (!state->rps_interactive) { in intel_prepare_plane_fb()
16079 intel_rps_mark_interactive(&dev_priv->gt.rps, true); in intel_prepare_plane_fb()
16080 state->rps_interactive = true; in intel_prepare_plane_fb()
16092 * intel_cleanup_plane_fb - Cleans up an fb after plane use
16105 to_intel_atomic_state(old_plane_state->uapi.state); in intel_cleanup_plane_fb()
16106 struct drm_i915_private *dev_priv = to_i915(plane->dev); in intel_cleanup_plane_fb()
16107 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb); in intel_cleanup_plane_fb()
16112 if (state->rps_interactive) { in intel_cleanup_plane_fb()
16113 intel_rps_mark_interactive(&dev_priv->gt.rps, false); in intel_cleanup_plane_fb()
16114 state->rps_interactive = false; in intel_cleanup_plane_fb()
16122 * intel_plane_destroy - destroy a plane
16225 to_intel_plane_state(plane->base.state); in intel_legacy_cursor_update()
16228 to_intel_crtc_state(crtc->base.state); in intel_legacy_cursor_update()
16236 if (!crtc_state->hw.active || needs_modeset(crtc_state) || in intel_legacy_cursor_update()
16237 crtc_state->update_pipe) in intel_legacy_cursor_update()
16245 if (old_plane_state->uapi.commit && in intel_legacy_cursor_update()
16246 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done)) in intel_legacy_cursor_update()
16254 if (old_plane_state->uapi.crtc != &crtc->base || in intel_legacy_cursor_update()
16255 old_plane_state->uapi.src_w != src_w || in intel_legacy_cursor_update()
16256 old_plane_state->uapi.src_h != src_h || in intel_legacy_cursor_update()
16257 old_plane_state->uapi.crtc_w != crtc_w || in intel_legacy_cursor_update()
16258 old_plane_state->uapi.crtc_h != crtc_h || in intel_legacy_cursor_update()
16259 !old_plane_state->uapi.fb != !fb) in intel_legacy_cursor_update()
16262 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base)); in intel_legacy_cursor_update()
16264 return -ENOMEM; in intel_legacy_cursor_update()
16266 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base)); in intel_legacy_cursor_update()
16268 ret = -ENOMEM; in intel_legacy_cursor_update()
16272 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb); in intel_legacy_cursor_update()
16274 new_plane_state->uapi.src_x = src_x; in intel_legacy_cursor_update()
16275 new_plane_state->uapi.src_y = src_y; in intel_legacy_cursor_update()
16276 new_plane_state->uapi.src_w = src_w; in intel_legacy_cursor_update()
16277 new_plane_state->uapi.src_h = src_h; in intel_legacy_cursor_update()
16278 new_plane_state->uapi.crtc_x = crtc_x; in intel_legacy_cursor_update()
16279 new_plane_state->uapi.crtc_y = crtc_y; in intel_legacy_cursor_update()
16280 new_plane_state->uapi.crtc_w = crtc_w; in intel_legacy_cursor_update()
16281 new_plane_state->uapi.crtc_h = crtc_h; in intel_legacy_cursor_update()
16294 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb), in intel_legacy_cursor_update()
16296 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), in intel_legacy_cursor_update()
16297 to_intel_frontbuffer(new_plane_state->hw.fb), in intel_legacy_cursor_update()
16298 plane->frontbuffer_bit); in intel_legacy_cursor_update()
16301 plane->base.state = &new_plane_state->uapi; in intel_legacy_cursor_update()
16306 * destroy the old state, we will cause a use-after-free there. in intel_legacy_cursor_update()
16313 crtc_state->active_planes = new_crtc_state->active_planes; in intel_legacy_cursor_update()
16315 if (new_plane_state->uapi.visible) in intel_legacy_cursor_update()
16324 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi); in intel_legacy_cursor_update()
16326 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi); in intel_legacy_cursor_update()
16328 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi); in intel_legacy_cursor_update()
16332 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb, in intel_legacy_cursor_update()
16381 plane->pipe = pipe; in intel_primary_plane_create()
16388 plane->i9xx_plane = (enum i9xx_plane_id) !pipe; in intel_primary_plane_create()
16390 plane->i9xx_plane = (enum i9xx_plane_id) pipe; in intel_primary_plane_create()
16391 plane->id = PLANE_PRIMARY; in intel_primary_plane_create()
16392 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); in intel_primary_plane_create()
16394 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane); in intel_primary_plane_create()
16395 if (plane->has_fbc) { in intel_primary_plane_create()
16396 struct intel_fbc *fbc = &dev_priv->fbc; in intel_primary_plane_create()
16398 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; in intel_primary_plane_create()
16407 * "Workaround : When using the 64-bit format, the plane in intel_primary_plane_create()
16436 plane->min_cdclk = vlv_plane_min_cdclk; in intel_primary_plane_create()
16438 plane->min_cdclk = hsw_plane_min_cdclk; in intel_primary_plane_create()
16440 plane->min_cdclk = ivb_plane_min_cdclk; in intel_primary_plane_create()
16442 plane->min_cdclk = i9xx_plane_min_cdclk; in intel_primary_plane_create()
16444 plane->max_stride = i9xx_plane_max_stride; in intel_primary_plane_create()
16445 plane->update_plane = i9xx_update_plane; in intel_primary_plane_create()
16446 plane->disable_plane = i9xx_disable_plane; in intel_primary_plane_create()
16447 plane->get_hw_state = i9xx_plane_get_hw_state; in intel_primary_plane_create()
16448 plane->check_plane = i9xx_plane_check; in intel_primary_plane_create()
16451 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, in intel_primary_plane_create()
16458 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, in intel_primary_plane_create()
16464 plane_name(plane->i9xx_plane)); in intel_primary_plane_create()
16480 drm_plane_create_rotation_property(&plane->base, in intel_primary_plane_create()
16485 drm_plane_create_zpos_immutable_property(&plane->base, zpos); in intel_primary_plane_create()
16487 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); in intel_primary_plane_create()
16508 cursor->pipe = pipe; in intel_cursor_plane_create()
16509 cursor->i9xx_plane = (enum i9xx_plane_id) pipe; in intel_cursor_plane_create()
16510 cursor->id = PLANE_CURSOR; in intel_cursor_plane_create()
16511 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id); in intel_cursor_plane_create()
16514 cursor->max_stride = i845_cursor_max_stride; in intel_cursor_plane_create()
16515 cursor->update_plane = i845_update_cursor; in intel_cursor_plane_create()
16516 cursor->disable_plane = i845_disable_cursor; in intel_cursor_plane_create()
16517 cursor->get_hw_state = i845_cursor_get_hw_state; in intel_cursor_plane_create()
16518 cursor->check_plane = i845_check_cursor; in intel_cursor_plane_create()
16520 cursor->max_stride = i9xx_cursor_max_stride; in intel_cursor_plane_create()
16521 cursor->update_plane = i9xx_update_cursor; in intel_cursor_plane_create()
16522 cursor->disable_plane = i9xx_disable_cursor; in intel_cursor_plane_create()
16523 cursor->get_hw_state = i9xx_cursor_get_hw_state; in intel_cursor_plane_create()
16524 cursor->check_plane = i9xx_check_cursor; in intel_cursor_plane_create()
16527 cursor->cursor.base = ~0; in intel_cursor_plane_create()
16528 cursor->cursor.cntl = ~0; in intel_cursor_plane_create()
16531 cursor->cursor.size = ~0; in intel_cursor_plane_create()
16533 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, in intel_cursor_plane_create()
16544 drm_plane_create_rotation_property(&cursor->base, in intel_cursor_plane_create()
16549 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; in intel_cursor_plane_create()
16550 drm_plane_create_zpos_immutable_property(&cursor->base, zpos); in intel_cursor_plane_create()
16553 drm_plane_enable_fb_damage_clips(&cursor->base); in intel_cursor_plane_create()
16555 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); in intel_cursor_plane_create()
16646 return ERR_PTR(-ENOMEM); in intel_crtc_alloc()
16651 return ERR_PTR(-ENOMEM); in intel_crtc_alloc()
16654 crtc->base.state = &crtc_state->uapi; in intel_crtc_alloc()
16655 crtc->config = crtc_state; in intel_crtc_alloc()
16662 intel_crtc_destroy_state(&crtc->base, crtc->base.state); in intel_crtc_free()
16670 for_each_intel_plane(&dev_priv->drm, plane) { in intel_plane_possible_crtcs_init()
16672 plane->pipe); in intel_plane_possible_crtcs_init()
16674 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); in intel_plane_possible_crtcs_init()
16689 crtc->pipe = pipe; in intel_crtc_init()
16690 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe]; in intel_crtc_init()
16697 crtc->plane_ids_mask |= BIT(primary->id); in intel_crtc_init()
16707 crtc->plane_ids_mask |= BIT(plane->id); in intel_crtc_init()
16715 crtc->plane_ids_mask |= BIT(cursor->id); in intel_crtc_init()
16736 ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base, in intel_crtc_init()
16737 &primary->base, &cursor->base, in intel_crtc_init()
16742 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) || in intel_crtc_init()
16743 dev_priv->pipe_to_crtc_mapping[pipe] != NULL); in intel_crtc_init()
16744 dev_priv->pipe_to_crtc_mapping[pipe] = crtc; in intel_crtc_init()
16747 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane; in intel_crtc_init()
16749 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || in intel_crtc_init()
16750 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL); in intel_crtc_init()
16751 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc; in intel_crtc_init()
16758 drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe); in intel_crtc_init()
16775 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); in intel_get_pipe_from_crtc_id_ioctl()
16777 return -ENOENT; in intel_get_pipe_from_crtc_id_ioctl()
16780 pipe_from_crtc_id->pipe = crtc->pipe; in intel_get_pipe_from_crtc_id_ioctl()
16787 struct drm_device *dev = encoder->base.dev; in intel_encoder_possible_clones()
16793 possible_clones |= drm_encoder_mask(&source_encoder->base); in intel_encoder_possible_clones()
16801 struct drm_device *dev = encoder->base.dev; in intel_encoder_possible_crtcs()
16806 if (encoder->pipe_mask & BIT(crtc->pipe)) in intel_encoder_possible_crtcs()
16807 possible_crtcs |= drm_crtc_mask(&crtc->base); in intel_encoder_possible_crtcs()
16843 if (!dev_priv->vbt.int_crt_support) in intel_ddi_crt_present()
16876 dev_priv->pps_mmio_base = PCH_PPS_BASE; in intel_pps_init()
16878 dev_priv->pps_mmio_base = VLV_PPS_BASE; in intel_pps_init()
16880 dev_priv->pps_mmio_base = PPS_BASE; in intel_pps_init()
16951 * On SKL pre-D0 the strap isn't connected, so we assume in intel_setup_outputs()
16972 * On SKL we don't have a way to detect DDI-E so we rely on VBT. in intel_setup_outputs()
17017 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) in intel_setup_outputs()
17023 * (no way to plug in a DP->HDMI dongle) the DDC pins for in intel_setup_outputs()
17030 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap in intel_setup_outputs()
17074 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); in intel_setup_outputs()
17077 drm_dbg_kms(&dev_priv->drm, in intel_setup_outputs()
17089 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); in intel_setup_outputs()
17096 drm_dbg_kms(&dev_priv->drm, in intel_setup_outputs()
17119 for_each_intel_encoder(&dev_priv->drm, encoder) { in intel_setup_outputs()
17120 encoder->base.possible_crtcs = in intel_setup_outputs()
17122 encoder->base.possible_clones = in intel_setup_outputs()
17128 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); in intel_setup_outputs()
17136 intel_frontbuffer_put(intel_fb->frontbuffer); in intel_user_framebuffer_destroy()
17146 struct drm_i915_private *i915 = to_i915(obj->base.dev); in intel_user_framebuffer_create_handle()
17148 if (obj->userptr.mm) { in intel_user_framebuffer_create_handle()
17149 drm_dbg(&i915->drm, in intel_user_framebuffer_create_handle()
17151 return -EINVAL; in intel_user_framebuffer_create_handle()
17154 return drm_gem_handle_create(file, &obj->base, handle); in intel_user_framebuffer_create_handle()
17181 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); in intel_framebuffer_init()
17182 struct drm_framebuffer *fb = &intel_fb->base; in intel_framebuffer_init()
17185 int ret = -EINVAL; in intel_framebuffer_init()
17188 intel_fb->frontbuffer = intel_frontbuffer_get(obj); in intel_framebuffer_init()
17189 if (!intel_fb->frontbuffer) in intel_framebuffer_init()
17190 return -ENOMEM; in intel_framebuffer_init()
17197 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { in intel_framebuffer_init()
17203 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { in intel_framebuffer_init()
17204 drm_dbg_kms(&dev_priv->drm, in intel_framebuffer_init()
17210 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; in intel_framebuffer_init()
17212 drm_dbg_kms(&dev_priv->drm, in intel_framebuffer_init()
17218 if (!drm_any_plane_has_format(&dev_priv->drm, in intel_framebuffer_init()
17219 mode_cmd->pixel_format, in intel_framebuffer_init()
17220 mode_cmd->modifier[0])) { in intel_framebuffer_init()
17223 drm_dbg_kms(&dev_priv->drm, in intel_framebuffer_init()
17225 drm_get_format_name(mode_cmd->pixel_format, in intel_framebuffer_init()
17227 mode_cmd->modifier[0]); in intel_framebuffer_init()
17236 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { in intel_framebuffer_init()
17237 drm_dbg_kms(&dev_priv->drm, in intel_framebuffer_init()
17242 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format, in intel_framebuffer_init()
17243 mode_cmd->modifier[0]); in intel_framebuffer_init()
17244 if (mode_cmd->pitches[0] > max_stride) { in intel_framebuffer_init()
17245 drm_dbg_kms(&dev_priv->drm, in intel_framebuffer_init()
17247 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? in intel_framebuffer_init()
17249 mode_cmd->pitches[0], max_stride); in intel_framebuffer_init()
17257 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { in intel_framebuffer_init()
17258 drm_dbg_kms(&dev_priv->drm, in intel_framebuffer_init()
17260 mode_cmd->pitches[0], stride); in intel_framebuffer_init()
17265 if (mode_cmd->offsets[0] != 0) { in intel_framebuffer_init()
17266 drm_dbg_kms(&dev_priv->drm, in intel_framebuffer_init()
17268 mode_cmd->offsets[0]); in intel_framebuffer_init()
17272 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); in intel_framebuffer_init()
17274 for (i = 0; i < fb->format->num_planes; i++) { in intel_framebuffer_init()
17277 if (mode_cmd->handles[i] != mode_cmd->handles[0]) { in intel_framebuffer_init()
17278 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n", in intel_framebuffer_init()
17284 if (fb->pitches[i] & (stride_alignment - 1)) { in intel_framebuffer_init()
17285 drm_dbg_kms(&dev_priv->drm, in intel_framebuffer_init()
17287 i, fb->pitches[i], stride_alignment); in intel_framebuffer_init()
17294 if (fb->pitches[i] != ccs_aux_stride) { in intel_framebuffer_init()
17295 drm_dbg_kms(&dev_priv->drm, in intel_framebuffer_init()
17298 fb->pitches[i], ccs_aux_stride); in intel_framebuffer_init()
17303 fb->obj[i] = &obj->base; in intel_framebuffer_init()
17310 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); in intel_framebuffer_init()
17312 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret); in intel_framebuffer_init()
17319 intel_frontbuffer_put(intel_fb->frontbuffer); in intel_framebuffer_init()
17334 return ERR_PTR(-ENOENT); in intel_user_framebuffer_create()
17358 * reject modes with the DBLSCAN flag in encoder->compute_config(). in intel_mode_valid()
17359 * And we always reject DBLSCAN modes in connector->mode_valid() in intel_mode_valid()
17363 if (mode->vscan > 1) in intel_mode_valid()
17366 if (mode->flags & DRM_MODE_FLAG_HSKEW) in intel_mode_valid()
17369 if (mode->flags & (DRM_MODE_FLAG_CSYNC | in intel_mode_valid()
17374 if (mode->flags & (DRM_MODE_FLAG_BCAST | in intel_mode_valid()
17403 if (mode->hdisplay > hdisplay_max || in intel_mode_valid()
17404 mode->hsync_start > htotal_max || in intel_mode_valid()
17405 mode->hsync_end > htotal_max || in intel_mode_valid()
17406 mode->htotal > htotal_max) in intel_mode_valid()
17409 if (mode->vdisplay > vdisplay_max || in intel_mode_valid()
17410 mode->vsync_start > vtotal_max || in intel_mode_valid()
17411 mode->vsync_end > vtotal_max || in intel_mode_valid()
17412 mode->vtotal > vtotal_max) in intel_mode_valid()
17416 if (mode->hdisplay < 64 || in intel_mode_valid()
17417 mode->htotal - mode->hdisplay < 32) in intel_mode_valid()
17420 if (mode->vtotal - mode->vdisplay < 5) in intel_mode_valid()
17423 if (mode->htotal - mode->hdisplay < 32) in intel_mode_valid()
17426 if (mode->vtotal - mode->vdisplay < 3) in intel_mode_valid()
17459 if (mode->hdisplay > plane_width_max) in intel_mode_valid_max_plane_size()
17462 if (mode->vdisplay > plane_height_max) in intel_mode_valid_max_plane_size()
17481 * intel_init_display_hooks - initialize the display modesetting hooks
17489 dev_priv->display.get_pipe_config = hsw_get_pipe_config; in intel_init_display_hooks()
17490 dev_priv->display.get_initial_plane_config = in intel_init_display_hooks()
17492 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock; in intel_init_display_hooks()
17493 dev_priv->display.crtc_enable = hsw_crtc_enable; in intel_init_display_hooks()
17494 dev_priv->display.crtc_disable = hsw_crtc_disable; in intel_init_display_hooks()
17496 dev_priv->display.get_pipe_config = hsw_get_pipe_config; in intel_init_display_hooks()
17497 dev_priv->display.get_initial_plane_config = in intel_init_display_hooks()
17499 dev_priv->display.crtc_compute_clock = in intel_init_display_hooks()
17501 dev_priv->display.crtc_enable = hsw_crtc_enable; in intel_init_display_hooks()
17502 dev_priv->display.crtc_disable = hsw_crtc_disable; in intel_init_display_hooks()
17504 dev_priv->display.get_pipe_config = ilk_get_pipe_config; in intel_init_display_hooks()
17505 dev_priv->display.get_initial_plane_config = in intel_init_display_hooks()
17507 dev_priv->display.crtc_compute_clock = in intel_init_display_hooks()
17509 dev_priv->display.crtc_enable = ilk_crtc_enable; in intel_init_display_hooks()
17510 dev_priv->display.crtc_disable = ilk_crtc_disable; in intel_init_display_hooks()
17512 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; in intel_init_display_hooks()
17513 dev_priv->display.get_initial_plane_config = in intel_init_display_hooks()
17515 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; in intel_init_display_hooks()
17516 dev_priv->display.crtc_enable = valleyview_crtc_enable; in intel_init_display_hooks()
17517 dev_priv->display.crtc_disable = i9xx_crtc_disable; in intel_init_display_hooks()
17519 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; in intel_init_display_hooks()
17520 dev_priv->display.get_initial_plane_config = in intel_init_display_hooks()
17522 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; in intel_init_display_hooks()
17523 dev_priv->display.crtc_enable = valleyview_crtc_enable; in intel_init_display_hooks()
17524 dev_priv->display.crtc_disable = i9xx_crtc_disable; in intel_init_display_hooks()
17526 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; in intel_init_display_hooks()
17527 dev_priv->display.get_initial_plane_config = in intel_init_display_hooks()
17529 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; in intel_init_display_hooks()
17530 dev_priv->display.crtc_enable = i9xx_crtc_enable; in intel_init_display_hooks()
17531 dev_priv->display.crtc_disable = i9xx_crtc_disable; in intel_init_display_hooks()
17533 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; in intel_init_display_hooks()
17534 dev_priv->display.get_initial_plane_config = in intel_init_display_hooks()
17536 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; in intel_init_display_hooks()
17537 dev_priv->display.crtc_enable = i9xx_crtc_enable; in intel_init_display_hooks()
17538 dev_priv->display.crtc_disable = i9xx_crtc_disable; in intel_init_display_hooks()
17540 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; in intel_init_display_hooks()
17541 dev_priv->display.get_initial_plane_config = in intel_init_display_hooks()
17543 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; in intel_init_display_hooks()
17544 dev_priv->display.crtc_enable = i9xx_crtc_enable; in intel_init_display_hooks()
17545 dev_priv->display.crtc_disable = i9xx_crtc_disable; in intel_init_display_hooks()
17547 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; in intel_init_display_hooks()
17548 dev_priv->display.get_initial_plane_config = in intel_init_display_hooks()
17550 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; in intel_init_display_hooks()
17551 dev_priv->display.crtc_enable = i9xx_crtc_enable; in intel_init_display_hooks()
17552 dev_priv->display.crtc_disable = i9xx_crtc_disable; in intel_init_display_hooks()
17556 dev_priv->display.fdi_link_train = ilk_fdi_link_train; in intel_init_display_hooks()
17558 dev_priv->display.fdi_link_train = gen6_fdi_link_train; in intel_init_display_hooks()
17561 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; in intel_init_display_hooks()
17565 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables; in intel_init_display_hooks()
17567 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables; in intel_init_display_hooks()
17574 to_intel_cdclk_state(i915->cdclk.obj.state); in intel_modeset_init_hw()
17576 to_intel_dbuf_state(i915->dbuf.obj.state); in intel_modeset_init_hw()
17579 intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK"); in intel_modeset_init_hw()
17580 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; in intel_modeset_init_hw()
17582 dbuf_state->enabled_slices = i915->dbuf.enabled_slices; in intel_modeset_init_hw()
17590 for_each_intel_crtc(state->dev, crtc) { in sanitize_watermarks_add_affected()
17597 if (crtc_state->hw.active) { in sanitize_watermarks_add_affected()
17602 crtc_state->inherited = true; in sanitize_watermarks_add_affected()
17606 drm_for_each_plane(plane, state->dev) { in sanitize_watermarks_add_affected()
17638 if (!dev_priv->display.optimize_watermarks) in sanitize_watermarks()
17641 state = drm_atomic_state_alloc(&dev_priv->drm); in sanitize_watermarks()
17642 if (drm_WARN_ON(&dev_priv->drm, !state)) in sanitize_watermarks()
17650 state->acquire_ctx = &ctx; in sanitize_watermarks()
17658 intel_state->skip_intermediate_wm = true; in sanitize_watermarks()
17664 ret = intel_atomic_check(&dev_priv->drm, state); in sanitize_watermarks()
17670 crtc_state->wm.need_postvbl_update = true; in sanitize_watermarks()
17671 dev_priv->display.optimize_watermarks(intel_state, crtc); in sanitize_watermarks()
17673 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; in sanitize_watermarks()
17677 if (ret == -EDEADLK) { in sanitize_watermarks()
17692 * BIOS-programmed watermarks untouched and hope for the best. in sanitize_watermarks()
17694 drm_WARN(&dev_priv->drm, ret, in sanitize_watermarks()
17709 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000; in intel_update_fdi_pll_freq()
17711 dev_priv->fdi_pll_freq = 270000; in intel_update_fdi_pll_freq()
17716 drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq); in intel_update_fdi_pll_freq()
17728 return -ENOMEM; in intel_initial_commit()
17733 state->acquire_ctx = &ctx; in intel_initial_commit()
17744 if (crtc_state->hw.active) { in intel_initial_commit()
17752 crtc_state->inherited = true; in intel_initial_commit()
17754 ret = drm_atomic_add_affected_planes(state, &crtc->base); in intel_initial_commit()
17764 crtc_state->uapi.color_mgmt_changed = true; in intel_initial_commit()
17771 * config comparison of crtc_state->dsc, we have no way in intel_initial_commit()
17775 if (crtc_state->dsc.compression_enable) { in intel_initial_commit()
17777 &crtc->base); in intel_initial_commit()
17780 crtc_state->uapi.mode_changed = true; in intel_initial_commit()
17789 if (ret == -EDEADLK) { in intel_initial_commit()
17805 struct drm_mode_config *mode_config = &i915->drm.mode_config; in intel_mode_config_init()
17807 drm_mode_config_init(&i915->drm); in intel_mode_config_init()
17808 INIT_LIST_HEAD(&i915->global_obj_list); in intel_mode_config_init()
17810 mode_config->min_width = 0; in intel_mode_config_init()
17811 mode_config->min_height = 0; in intel_mode_config_init()
17813 mode_config->preferred_depth = 24; in intel_mode_config_init()
17814 mode_config->prefer_shadow = 1; in intel_mode_config_init()
17816 mode_config->allow_fb_modifiers = true; in intel_mode_config_init()
17818 mode_config->funcs = &intel_mode_funcs; in intel_mode_config_init()
17825 mode_config->max_width = 16384; in intel_mode_config_init()
17826 mode_config->max_height = 16384; in intel_mode_config_init()
17828 mode_config->max_width = 8192; in intel_mode_config_init()
17829 mode_config->max_height = 8192; in intel_mode_config_init()
17831 mode_config->max_width = 4096; in intel_mode_config_init()
17832 mode_config->max_height = 4096; in intel_mode_config_init()
17834 mode_config->max_width = 2048; in intel_mode_config_init()
17835 mode_config->max_height = 2048; in intel_mode_config_init()
17839 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; in intel_mode_config_init()
17840 mode_config->cursor_height = 1023; in intel_mode_config_init()
17843 mode_config->cursor_width = 64; in intel_mode_config_init()
17844 mode_config->cursor_height = 64; in intel_mode_config_init()
17846 mode_config->cursor_width = 256; in intel_mode_config_init()
17847 mode_config->cursor_height = 256; in intel_mode_config_init()
17854 drm_mode_config_cleanup(&i915->drm); in intel_mode_config_cleanup()
17859 if (plane_config->fb) { in plane_config_fini()
17860 struct drm_framebuffer *fb = &plane_config->fb->base; in plane_config_fini()
17869 if (plane_config->vma) in plane_config_fini()
17870 i915_vma_put(plane_config->vma); in plane_config_fini()
17879 return -ENODEV; in intel_modeset_init_noirq()
17882 ret = drm_vblank_init(&i915->drm, in intel_modeset_init_noirq()
17899 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); in intel_modeset_init_noirq()
17900 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | in intel_modeset_init_noirq()
17917 init_llist_head(&i915->atomic_helper.free_list); in intel_modeset_init_noirq()
17918 INIT_WORK(&i915->atomic_helper.free_work, in intel_modeset_init_noirq()
17940 struct drm_device *dev = &i915->drm; in intel_modeset_init_nogem()
17951 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", in intel_modeset_init_nogem()
17974 if (i915->max_cdclk_freq == 0) in intel_modeset_init_nogem()
17981 if (INTEL_INFO(i915)->display.has_hti) in intel_modeset_init_nogem()
17982 i915->hti_state = intel_de_read(i915, HDPORT_STATE); in intel_modeset_init_nogem()
17989 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); in intel_modeset_init_nogem()
17995 if (!crtc->active) in intel_modeset_init_nogem()
18005 i915->display.get_initial_plane_config(crtc, &plane_config); in intel_modeset_init_nogem()
18019 * since the watermark calculation done here will use pstate->fb. in intel_modeset_init_nogem()
18041 ret = intel_initial_commit(&i915->drm); in intel_modeset_init()
18043 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); in intel_modeset_init()
18047 ret = intel_fbdev_init(&i915->drm); in intel_modeset_init()
18056 intel_psr_set_force_mode_changed(i915->psr.dp); in intel_modeset_init()
18075 drm_WARN_ON(&dev_priv->drm, in i830_enable_pipe()
18078 drm_dbg_kms(&dev_priv->drm, in i830_enable_pipe()
18085 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | in i830_enable_pipe()
18093 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); in i830_enable_pipe()
18094 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); in i830_enable_pipe()
18095 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); in i830_enable_pipe()
18096 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); in i830_enable_pipe()
18097 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); in i830_enable_pipe()
18098 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); in i830_enable_pipe()
18099 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); in i830_enable_pipe()
18138 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", in i830_disable_pipe()
18141 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
18144 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
18147 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
18150 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
18152 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
18172 for_each_intel_crtc(&dev_priv->drm, crtc) { in intel_sanitize_plane_mapping()
18174 to_intel_plane(crtc->base.primary); in intel_sanitize_plane_mapping()
18178 if (!plane->get_hw_state(plane, &pipe)) in intel_sanitize_plane_mapping()
18181 if (pipe == crtc->pipe) in intel_sanitize_plane_mapping()
18184 drm_dbg_kms(&dev_priv->drm, in intel_sanitize_plane_mapping()
18186 plane->base.base.id, plane->base.name); in intel_sanitize_plane_mapping()
18195 struct drm_device *dev = crtc->base.dev; in intel_crtc_has_encoders()
18198 for_each_encoder_on_crtc(dev, &crtc->base, encoder) in intel_crtc_has_encoders()
18206 struct drm_device *dev = encoder->base.dev; in intel_encoder_find_connector()
18209 for_each_connector_on_encoder(dev, &encoder->base, connector) in intel_encoder_find_connector()
18224 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_sanitize_frame_start_delay()
18225 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_sanitize_frame_start_delay()
18226 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_sanitize_frame_start_delay()
18250 if (!crtc_state->has_pch_encoder) in intel_sanitize_frame_start_delay()
18254 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe); in intel_sanitize_frame_start_delay()
18276 struct drm_device *dev = crtc->base.dev; in intel_sanitize_crtc()
18278 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); in intel_sanitize_crtc()
18280 if (crtc_state->hw.active) { in intel_sanitize_crtc()
18289 to_intel_plane_state(plane->base.state); in intel_sanitize_crtc()
18291 if (plane_state->uapi.visible && in intel_sanitize_crtc()
18292 plane->base.type != DRM_PLANE_TYPE_PRIMARY) in intel_sanitize_crtc()
18301 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe), in intel_sanitize_crtc()
18307 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc)) in intel_sanitize_crtc()
18310 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) { in intel_sanitize_crtc()
18321 * No protection against concurrent access is required - at in intel_sanitize_crtc()
18324 crtc->cpu_fifo_underrun_disabled = true; in intel_sanitize_crtc()
18329 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, in intel_sanitize_crtc()
18330 * and marking underrun reporting as disabled for the non-existing in intel_sanitize_crtc()
18334 if (has_pch_trancoder(dev_priv, crtc->pipe)) in intel_sanitize_crtc()
18335 crtc->pch_fifo_underrun_disabled = true; in intel_sanitize_crtc()
18341 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in has_bogus_dpll_config()
18354 crtc_state->hw.active && in has_bogus_dpll_config()
18355 crtc_state->shared_dpll && in has_bogus_dpll_config()
18356 crtc_state->port_clock == 0; in has_bogus_dpll_config()
18361 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_sanitize_encoder()
18363 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_sanitize_encoder()
18365 to_intel_crtc_state(crtc->base.state) : NULL; in intel_sanitize_encoder()
18371 crtc_state->hw.active; in intel_sanitize_encoder()
18374 drm_dbg_kms(&dev_priv->drm, in intel_sanitize_encoder()
18376 pipe_name(crtc->pipe)); in intel_sanitize_encoder()
18382 drm_dbg_kms(&dev_priv->drm, in intel_sanitize_encoder()
18384 encoder->base.base.id, in intel_sanitize_encoder()
18385 encoder->base.name); in intel_sanitize_encoder()
18393 drm_dbg_kms(&dev_priv->drm, in intel_sanitize_encoder()
18395 encoder->base.base.id, in intel_sanitize_encoder()
18396 encoder->base.name); in intel_sanitize_encoder()
18399 best_encoder = connector->base.state->best_encoder; in intel_sanitize_encoder()
18400 connector->base.state->best_encoder = &encoder->base; in intel_sanitize_encoder()
18403 if (encoder->disable) in intel_sanitize_encoder()
18404 encoder->disable(NULL, encoder, crtc_state, in intel_sanitize_encoder()
18405 connector->base.state); in intel_sanitize_encoder()
18406 if (encoder->post_disable) in intel_sanitize_encoder()
18407 encoder->post_disable(NULL, encoder, crtc_state, in intel_sanitize_encoder()
18408 connector->base.state); in intel_sanitize_encoder()
18410 connector->base.state->best_encoder = best_encoder; in intel_sanitize_encoder()
18412 encoder->base.crtc = NULL; in intel_sanitize_encoder()
18419 connector->base.dpms = DRM_MODE_DPMS_OFF; in intel_sanitize_encoder()
18420 connector->base.encoder = NULL; in intel_sanitize_encoder()
18436 for_each_intel_plane(&dev_priv->drm, plane) { in readout_plane_state()
18438 to_intel_plane_state(plane->base.state); in readout_plane_state()
18443 visible = plane->get_hw_state(plane, &pipe); in readout_plane_state()
18446 crtc_state = to_intel_crtc_state(crtc->base.state); in readout_plane_state()
18450 drm_dbg_kms(&dev_priv->drm, in readout_plane_state()
18452 plane->base.base.id, plane->base.name, in readout_plane_state()
18456 for_each_intel_crtc(&dev_priv->drm, crtc) { in readout_plane_state()
18458 to_intel_crtc_state(crtc->base.state); in readout_plane_state()
18468 to_intel_cdclk_state(dev_priv->cdclk.obj.state); in intel_modeset_readout_hw_state()
18470 to_intel_dbuf_state(dev_priv->dbuf.obj.state); in intel_modeset_readout_hw_state()
18480 to_intel_crtc_state(crtc->base.state); in intel_modeset_readout_hw_state()
18482 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); in intel_modeset_readout_hw_state()
18486 crtc_state->hw.active = crtc_state->hw.enable = in intel_modeset_readout_hw_state()
18487 dev_priv->display.get_pipe_config(crtc, crtc_state); in intel_modeset_readout_hw_state()
18489 crtc->base.enabled = crtc_state->hw.enable; in intel_modeset_readout_hw_state()
18490 crtc->active = crtc_state->hw.active; in intel_modeset_readout_hw_state()
18492 if (crtc_state->hw.active) in intel_modeset_readout_hw_state()
18493 active_pipes |= BIT(crtc->pipe); in intel_modeset_readout_hw_state()
18495 drm_dbg_kms(&dev_priv->drm, in intel_modeset_readout_hw_state()
18497 crtc->base.base.id, crtc->base.name, in intel_modeset_readout_hw_state()
18498 enableddisabled(crtc_state->hw.active)); in intel_modeset_readout_hw_state()
18501 dev_priv->active_pipes = cdclk_state->active_pipes = in intel_modeset_readout_hw_state()
18502 dbuf_state->active_pipes = active_pipes; in intel_modeset_readout_hw_state()
18511 if (encoder->get_hw_state(encoder, &pipe)) { in intel_modeset_readout_hw_state()
18515 crtc_state = to_intel_crtc_state(crtc->base.state); in intel_modeset_readout_hw_state()
18517 encoder->base.crtc = &crtc->base; in intel_modeset_readout_hw_state()
18518 encoder->get_config(encoder, crtc_state); in intel_modeset_readout_hw_state()
18520 encoder->base.crtc = NULL; in intel_modeset_readout_hw_state()
18523 drm_dbg_kms(&dev_priv->drm, in intel_modeset_readout_hw_state()
18525 encoder->base.base.id, encoder->base.name, in intel_modeset_readout_hw_state()
18526 enableddisabled(encoder->base.crtc), in intel_modeset_readout_hw_state()
18532 if (connector->get_hw_state(connector)) { in intel_modeset_readout_hw_state()
18536 connector->base.dpms = DRM_MODE_DPMS_ON; in intel_modeset_readout_hw_state()
18539 connector->base.encoder = &encoder->base; in intel_modeset_readout_hw_state()
18541 crtc = to_intel_crtc(encoder->base.crtc); in intel_modeset_readout_hw_state()
18542 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; in intel_modeset_readout_hw_state()
18544 if (crtc_state && crtc_state->hw.active) { in intel_modeset_readout_hw_state()
18550 crtc_state->uapi.connector_mask |= in intel_modeset_readout_hw_state()
18551 drm_connector_mask(&connector->base); in intel_modeset_readout_hw_state()
18552 crtc_state->uapi.encoder_mask |= in intel_modeset_readout_hw_state()
18553 drm_encoder_mask(&encoder->base); in intel_modeset_readout_hw_state()
18556 connector->base.dpms = DRM_MODE_DPMS_OFF; in intel_modeset_readout_hw_state()
18557 connector->base.encoder = NULL; in intel_modeset_readout_hw_state()
18559 drm_dbg_kms(&dev_priv->drm, in intel_modeset_readout_hw_state()
18561 connector->base.base.id, connector->base.name, in intel_modeset_readout_hw_state()
18562 enableddisabled(connector->base.encoder)); in intel_modeset_readout_hw_state()
18568 to_intel_bw_state(dev_priv->bw_obj.state); in intel_modeset_readout_hw_state()
18570 to_intel_crtc_state(crtc->base.state); in intel_modeset_readout_hw_state()
18574 if (crtc_state->hw.active) { in intel_modeset_readout_hw_state()
18575 struct drm_display_mode *mode = &crtc_state->hw.mode; in intel_modeset_readout_hw_state()
18577 intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode, in intel_modeset_readout_hw_state()
18580 *mode = crtc_state->hw.adjusted_mode; in intel_modeset_readout_hw_state()
18581 mode->hdisplay = crtc_state->pipe_src_w; in intel_modeset_readout_hw_state()
18582 mode->vdisplay = crtc_state->pipe_src_h; in intel_modeset_readout_hw_state()
18593 crtc_state->inherited = true; in intel_modeset_readout_hw_state()
18602 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { in intel_modeset_readout_hw_state()
18604 to_intel_plane_state(plane->base.state); in intel_modeset_readout_hw_state()
18610 if (plane_state->uapi.visible) in intel_modeset_readout_hw_state()
18611 crtc_state->data_rate[plane->id] = in intel_modeset_readout_hw_state()
18612 4 * crtc_state->pixel_rate; in intel_modeset_readout_hw_state()
18615 * use plane->min_cdclk() :( in intel_modeset_readout_hw_state()
18617 if (plane_state->uapi.visible && plane->min_cdclk) { in intel_modeset_readout_hw_state()
18618 if (crtc_state->double_wide || in intel_modeset_readout_hw_state()
18620 crtc_state->min_cdclk[plane->id] = in intel_modeset_readout_hw_state()
18621 DIV_ROUND_UP(crtc_state->pixel_rate, 2); in intel_modeset_readout_hw_state()
18623 crtc_state->min_cdclk[plane->id] = in intel_modeset_readout_hw_state()
18624 crtc_state->pixel_rate; in intel_modeset_readout_hw_state()
18626 drm_dbg_kms(&dev_priv->drm, in intel_modeset_readout_hw_state()
18628 plane->base.base.id, plane->base.name, in intel_modeset_readout_hw_state()
18629 crtc_state->min_cdclk[plane->id]); in intel_modeset_readout_hw_state()
18632 if (crtc_state->hw.active) { in intel_modeset_readout_hw_state()
18638 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_modeset_readout_hw_state()
18639 cdclk_state->min_voltage_level[crtc->pipe] = in intel_modeset_readout_hw_state()
18640 crtc_state->min_voltage_level; in intel_modeset_readout_hw_state()
18653 for_each_intel_encoder(&dev_priv->drm, encoder) { in get_encoder_power_domains()
18656 if (!encoder->get_power_domains) in get_encoder_power_domains()
18660 * MST-primary and inactive encoders don't have a crtc state in get_encoder_power_domains()
18663 if (!encoder->base.crtc) in get_encoder_power_domains()
18666 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); in get_encoder_power_domains()
18667 encoder->get_power_domains(encoder, crtc_state); in get_encoder_power_domains()
18700 drm_dbg_kms(&dev_priv->drm, in ibx_sanitize_pch_hdmi_port()
18719 drm_dbg_kms(&dev_priv->drm, in ibx_sanitize_pch_dp_port()
18773 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in intel_modeset_setup_hw_state()
18776 if (encoder->type != INTEL_OUTPUT_DP_MST && in intel_modeset_setup_hw_state()
18790 for_each_intel_crtc(&dev_priv->drm, crtc) { in intel_modeset_setup_hw_state()
18792 to_intel_crtc_state(crtc->base.state); in intel_modeset_setup_hw_state()
18794 drm_crtc_vblank_reset(&crtc->base); in intel_modeset_setup_hw_state()
18796 if (crtc_state->hw.active) in intel_modeset_setup_hw_state()
18805 for_each_intel_crtc(&dev_priv->drm, crtc) { in intel_modeset_setup_hw_state()
18807 to_intel_crtc_state(crtc->base.state); in intel_modeset_setup_hw_state()
18831 to_intel_crtc_state(crtc->base.state); in intel_modeset_setup_hw_state()
18845 struct drm_atomic_state *state = dev_priv->modeset_restore_state; in intel_display_resume()
18849 dev_priv->modeset_restore_state = NULL; in intel_display_resume()
18851 state->acquire_ctx = &ctx; in intel_display_resume()
18857 if (ret != -EDEADLK) in intel_display_resume()
18871 drm_err(&dev_priv->drm, in intel_display_resume()
18883 drm_connector_list_iter_begin(&i915->drm, &conn_iter); in intel_hpd_poll_fini()
18885 if (connector->modeset_retry_work.func) in intel_hpd_poll_fini()
18886 cancel_work_sync(&connector->modeset_retry_work); in intel_hpd_poll_fini()
18887 if (connector->hdcp.shim) { in intel_hpd_poll_fini()
18888 cancel_delayed_work_sync(&connector->hdcp.check_work); in intel_hpd_poll_fini()
18889 cancel_work_sync(&connector->hdcp.prop_work); in intel_hpd_poll_fini()
18898 flush_workqueue(i915->flip_wq); in intel_modeset_driver_remove()
18899 flush_workqueue(i915->modeset_wq); in intel_modeset_driver_remove()
18901 flush_work(&i915->atomic_helper.free_work); in intel_modeset_driver_remove()
18902 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); in intel_modeset_driver_remove()
18909 * Due to the hpd irq storm handling the hotplug work can re-arm the in intel_modeset_driver_remove_noirq()
18939 destroy_workqueue(i915->flip_wq); in intel_modeset_driver_remove_noirq()
18940 destroy_workqueue(i915->modeset_wq); in intel_modeset_driver_remove_noirq()
19015 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder)); in intel_display_capture_error_state()
19025 error->power_well_driver = intel_de_read(dev_priv, in intel_display_capture_error_state()
19029 error->pipe[i].power_domain_on = in intel_display_capture_error_state()
19032 if (!error->pipe[i].power_domain_on) in intel_display_capture_error_state()
19035 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i)); in intel_display_capture_error_state()
19036 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i)); in intel_display_capture_error_state()
19037 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i)); in intel_display_capture_error_state()
19039 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i)); in intel_display_capture_error_state()
19040 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i)); in intel_display_capture_error_state()
19042 error->plane[i].size = intel_de_read(dev_priv, in intel_display_capture_error_state()
19044 error->plane[i].pos = intel_de_read(dev_priv, in intel_display_capture_error_state()
19048 error->plane[i].addr = intel_de_read(dev_priv, in intel_display_capture_error_state()
19051 error->plane[i].surface = intel_de_read(dev_priv, in intel_display_capture_error_state()
19053 error->plane[i].tile_offset = intel_de_read(dev_priv, in intel_display_capture_error_state()
19057 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i)); in intel_display_capture_error_state()
19060 error->pipe[i].stat = intel_de_read(dev_priv, in intel_display_capture_error_state()
19064 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) { in intel_display_capture_error_state()
19070 error->transcoder[i].available = true; in intel_display_capture_error_state()
19071 error->transcoder[i].power_domain_on = in intel_display_capture_error_state()
19074 if (!error->transcoder[i].power_domain_on) in intel_display_capture_error_state()
19077 error->transcoder[i].cpu_transcoder = cpu_transcoder; in intel_display_capture_error_state()
19079 error->transcoder[i].conf = intel_de_read(dev_priv, in intel_display_capture_error_state()
19081 error->transcoder[i].htotal = intel_de_read(dev_priv, in intel_display_capture_error_state()
19083 error->transcoder[i].hblank = intel_de_read(dev_priv, in intel_display_capture_error_state()
19085 error->transcoder[i].hsync = intel_de_read(dev_priv, in intel_display_capture_error_state()
19087 error->transcoder[i].vtotal = intel_de_read(dev_priv, in intel_display_capture_error_state()
19089 error->transcoder[i].vblank = intel_de_read(dev_priv, in intel_display_capture_error_state()
19091 error->transcoder[i].vsync = intel_de_read(dev_priv, in intel_display_capture_error_state()
19104 struct drm_i915_private *dev_priv = m->i915; in intel_display_print_error_state()
19113 error->power_well_driver); in intel_display_print_error_state()
19117 onoff(error->pipe[i].power_domain_on)); in intel_display_print_error_state()
19118 err_printf(m, " SRC: %08x\n", error->pipe[i].source); in intel_display_print_error_state()
19119 err_printf(m, " STAT: %08x\n", error->pipe[i].stat); in intel_display_print_error_state()
19122 err_printf(m, " CNTR: %08x\n", error->plane[i].control); in intel_display_print_error_state()
19123 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); in intel_display_print_error_state()
19125 err_printf(m, " SIZE: %08x\n", error->plane[i].size); in intel_display_print_error_state()
19126 err_printf(m, " POS: %08x\n", error->plane[i].pos); in intel_display_print_error_state()
19129 err_printf(m, " ADDR: %08x\n", error->plane[i].addr); in intel_display_print_error_state()
19131 err_printf(m, " SURF: %08x\n", error->plane[i].surface); in intel_display_print_error_state()
19132 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); in intel_display_print_error_state()
19136 err_printf(m, " CNTR: %08x\n", error->cursor[i].control); in intel_display_print_error_state()
19137 err_printf(m, " POS: %08x\n", error->cursor[i].position); in intel_display_print_error_state()
19138 err_printf(m, " BASE: %08x\n", error->cursor[i].base); in intel_display_print_error_state()
19141 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) { in intel_display_print_error_state()
19142 if (!error->transcoder[i].available) in intel_display_print_error_state()
19146 transcoder_name(error->transcoder[i].cpu_transcoder)); in intel_display_print_error_state()
19148 onoff(error->transcoder[i].power_domain_on)); in intel_display_print_error_state()
19149 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); in intel_display_print_error_state()
19150 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); in intel_display_print_error_state()
19151 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); in intel_display_print_error_state()
19152 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); in intel_display_print_error_state()
19153 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); in intel_display_print_error_state()
19154 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); in intel_display_print_error_state()
19155 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); in intel_display_print_error_state()