| /Linux-v5.10/drivers/clk/tegra/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
24 #define PLL_BASE_DIVM_SHIFT 0
26 #define PLLU_POST_DIVP_MASK 0x1
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
35 #define PLL_MISC_VCOCON_SHIFT 0
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
41 #define PMC_PLLP_WB0_OVERRIDE 0xf8
50 #define PLLE_BASE_DIVCML_MASK 0xf
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| /Linux-v5.10/drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
12 #include "clk-alpha-pll.h"
15 #define PLL_MODE(p) ((p)->offset + 0x0)
16 # define PLL_OUTCTRL BIT(0)
21 # define PLL_LOCK_COUNT_MASK 0x3f
23 # define PLL_BIAS_COUNT_MASK 0x3f
34 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
35 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
36 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
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| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
20 #define PLL_OUTCTRL BIT(0)
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
37 return 0; in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
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| /Linux-v5.10/drivers/clk/mediatek/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "clk-mtk.h"
16 #define REG_CON0 0
19 #define CON0_BASE_EN BIT(0)
20 #define CON0_PWR_ON BIT(0)
26 #define POSTDIV_MASK 0x7
33 * a divider in the PLL feedback loop which consists of 7 bits for the integer
35 * have a 3 bit power-of-two post divider.
57 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
59 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; in mtk_pll_is_prepared()
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| /Linux-v5.10/drivers/clk/sprd/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
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| /Linux-v5.10/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 16 #include <linux/clk-provider.h>
23 #include "clk-iproc.h"
29 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
30 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
34 /* number of delay loops waiting for PLL to lock */
42 KP_BAND_MID = 0,
85 struct iproc_pll *pll; member
100 return -EINVAL; in pll_calc_param()
102 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
112 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
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| D | clk-iproc-armpll.c | 17 #include <linux/clk-provider.h>
23 #include "clk-iproc.h"
25 #define IPROC_CLK_MAX_FREQ_POLICY 0x3
26 #define IPROC_CLK_POLICY_FREQ_OFFSET 0x008
28 #define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK 0x7
30 #define IPROC_CLK_PLLARMA_OFFSET 0xc00
33 #define IPROC_CLK_PLLARMA_PDIV_MASK 0xf
35 #define IPROC_CLK_PLLARMA_NDIV_INT_MASK 0x3ff
37 #define IPROC_CLK_PLLARMB_OFFSET 0xc04
38 #define IPROC_CLK_PLLARMB_NDIV_FRAC_MASK 0xfffff
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| /Linux-v5.10/drivers/clk/imx/ |
| D | clk-pllv3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
16 #define PLL_NUM_OFFSET 0x10
17 #define PLL_DENOM_OFFSET 0x20
18 #define PLL_IMX7_NUM_OFFSET 0x20
19 #define PLL_IMX7_DENOM_OFFSET 0x30
21 #define PLL_VF610_NUM_OFFSET 0x20
22 #define PLL_VF610_DENOM_OFFSET 0x30
24 #define BM_PLL_POWER (0x1 << 12)
25 #define BM_PLL_LOCK (0x1 << 31)
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| D | clk-pll14xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2017-2018 NXP.
7 #include <linux/clk-provider.h>
17 #define GNRL_CTL 0x0
18 #define DIV_CTL 0x4
28 #define SDIV_SHIFT 0
29 #define SDIV_MASK GENMASK(2, 0)
30 #define KDIV_SHIFT 0
31 #define KDIV_MASK GENMASK(15, 0)
46 PLL_1416X_RATE(1800000000U, 225, 3, 0),
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| /Linux-v5.10/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 1 // SPDX-License-Identifier: GPL-2.0
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
53 * CLK = ----------------------
70 * XCLK The clock rate of the on-chip memory
77 * SCLK Multi-purpose clock
79 * - MCLK and XCLK use the same FB_DIV
80 * - VCLK0 .. VCLK3 use the same FB_DIV
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| /Linux-v5.10/drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
8 static int dsi_pll_enable(struct msm_dsi_pll *pll) in dsi_pll_enable() argument
10 int i, ret = 0; in dsi_pll_enable()
16 if (unlikely(pll->pll_on)) in dsi_pll_enable()
17 return 0; in dsi_pll_enable()
20 for (i = 0; i < pll->en_seq_cnt; i++) { in dsi_pll_enable()
21 ret = pll->enable_seqs[i](pll); in dsi_pll_enable()
22 DBG("DSI PLL %s after sequence #%d", in dsi_pll_enable()
29 DRM_ERROR("DSI PLL failed to lock\n"); in dsi_pll_enable()
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| D | dsi_pll_7nm.c | 2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
14 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
19 * +---------+ | +----------+ | +----+
20 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
21 * +---------+ | +----------+ | +----+
25 * | | +----+ | |\ dsi0_pclk_mux
26 * | |--| /2 |--o--| \ |
27 * | | +----+ | \ | +---------+
28 …* | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_…
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| D | dsi_pll_14nm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 * DSI PLL 14nm - clock diagram (eg: DSI0):
18 * +----+ | +----+
19 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
20 * +----+ | +----+
22 * | +----+ |
23 * o---| /2 |--o--|\
24 * | +----+ | \ +----+
25 * | | |--| n2 |-- dsi0pll
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| D | dsi_pll_10nm.c | 2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
14 * DSI PLL 10nm - clock diagram (eg: DSI0):
19 * +---------+ | +----------+ | +----+
20 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
21 * +---------+ | +----------+ | +----+
25 * | | +----+ | |\ dsi0_pclk_mux
26 * | |--| /2 |--o--| \ |
27 * | | +----+ | \ | +---------+
28 …* | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_…
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| /Linux-v5.10/drivers/clk/rockchip/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
20 #define PLL_MODE_MASK 0x3
21 #define PLL_MODE_SLOW 0x0
22 #define PLL_MODE_NORM 0x1
23 #define PLL_MODE_DEEP 0x2
24 #define PLL_RK3328_MODE_MASK 0x1
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
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| /Linux-v5.10/drivers/clk/meson/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
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| /Linux-v5.10/drivers/clk/samsung/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file contains the utility functions to register the pll clocks.
13 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
24 /* PLL enable control bit offset in @con_reg register */
26 /* PLL lock status bit offset in @con_reg register */
36 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
38 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
41 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
52 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
[all …]
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| /Linux-v5.10/drivers/clk/pistachio/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
16 #define PLL_STATUS 0x0
17 #define PLL_STATUS_LOCK BIT(0)
19 #define PLL_CTRL1 0x4
20 #define PLL_CTRL1_REFDIV_SHIFT 0
21 #define PLL_CTRL1_REFDIV_MASK 0x3f
23 #define PLL_CTRL1_FBDIV_MASK 0xfff
25 #define PLL_INT_CTRL1_POSTDIV1_MASK 0x7
27 #define PLL_INT_CTRL1_POSTDIV2_MASK 0x7
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| /Linux-v5.10/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_phy_8996.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
33 /* pll mmio base */
81 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll) in pll_get_phy() argument
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
86 static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset, in hdmi_pll_write() argument
89 msm_writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
92 static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset) in hdmi_pll_read() argument
94 return msm_readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
97 static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel, in hdmi_tx_chan_write() argument
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| /Linux-v5.10/drivers/clk/st/ |
| D | clkgen-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/clk-provider.h>
24 * PLL configuration register bits for PLL3200 C32
26 #define C32_NDIV_MASK (0xff)
27 #define C32_IDF_MASK (0x7)
28 #define C32_ODF_MASK (0x3f)
29 #define C32_LDF_MASK (0x7f)
30 #define C32_CP_MASK (0x1f)
35 * PLL configuration register bits for PLL4600 C28
37 #define C28_NDIV_MASK (0xff)
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| /Linux-v5.10/drivers/clk/x86/ |
| D | clk-cgu-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
14 #include "clk-cgu.h"
17 #define PLL_REF_DIV(x) ((x) + 0x08)
41 struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); in lgm_pll_recalc_rate() local
45 spin_lock_irqsave(&pll->lock, flags); in lgm_pll_recalc_rate()
46 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
47 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); in lgm_pll_recalc_rate()
48 frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); in lgm_pll_recalc_rate()
49 spin_unlock_irqrestore(&pll->lock, flags); in lgm_pll_recalc_rate()
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| /Linux-v5.10/drivers/clk/baikal-t1/ |
| D | ccu-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL interface driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
20 #include <linux/clk-provider.h>
29 #include "ccu-pll.h"
31 #define CCU_PLL_CTL 0x000
32 #define CCU_PLL_CTL_EN BIT(0)
42 #define CCU_PLL_CTL1 0x004
88 static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk, in ccu_pll_reset() argument
97 regmap_update_bits(pll->sys_regs, pll->reg_ctl, in ccu_pll_reset()
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| /Linux-v5.10/drivers/clk/mmp/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MMP PLL clock rate calculation
8 #include <linux/clk-provider.h>
31 struct mmp_clk_pll *pll = to_clk_mmp_pll(hw); in mmp_clk_pll_is_enabled() local
34 val = readl_relaxed(pll->enable_reg); in mmp_clk_pll_is_enabled()
35 if ((val & pll->enable) == pll->enable) in mmp_clk_pll_is_enabled()
39 if (pll->default_rate > 0) in mmp_clk_pll_is_enabled()
42 return 0; in mmp_clk_pll_is_enabled()
48 struct mmp_clk_pll *pll = to_clk_mmp_pll(hw); in mmp_clk_pll_recalc_rate() local
53 val = readl_relaxed(pll->enable_reg); in mmp_clk_pll_recalc_rate()
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| /Linux-v5.10/drivers/clk/at91/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
17 #define PLL_DIV_MASK 0xff
20 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
21 (layout)->mul_mask)
23 #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
26 #define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
27 #define PLL_MAX_COUNT 0x3f
51 return status & PLL_STATUS_MASK(id) ? 1 : 0; in clk_pll_ready()
56 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
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| /Linux-v5.10/drivers/video/fbdev/omap2/omapfb/dss/ |
| D | hdmi_pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * HDMI PLL
23 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) in hdmi_pll_dump() argument
25 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ in hdmi_pll_dump()
26 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
39 void hdmi_pll_compute(struct hdmi_pll_data *pll, in hdmi_pll_compute() argument
47 const struct dss_pll_hw *hw = pll->pll.hw; in hdmi_pll_compute()
49 clkin = clk_get_rate(pll->pll.clkin); in hdmi_pll_compute()
56 n = DIV_ROUND_UP(clkin, hw->fint_max); in hdmi_pll_compute()
60 min_dco = roundup(hw->clkdco_min, fint); in hdmi_pll_compute()
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