1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright 2017-2018 NXP.
7 #include <linux/clk-provider.h>
17 #define GNRL_CTL	0x0
18 #define DIV_CTL		0x4
28 #define SDIV_SHIFT	0
29 #define SDIV_MASK	GENMASK(2, 0)
30 #define KDIV_SHIFT	0
31 #define KDIV_MASK	GENMASK(15, 0)
46 	PLL_1416X_RATE(1800000000U, 225, 3, 0),
47 	PLL_1416X_RATE(1600000000U, 200, 3, 0),
60 	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
61 	PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
90 		struct clk_pll14xx *pll, unsigned long rate)  in imx_get_pll_settings()  argument
92 	const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;  in imx_get_pll_settings()
95 	for (i = 0; i < pll->rate_count; i++)  in imx_get_pll_settings()
105 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll14xx_round_rate()  local
106 	const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;  in clk_pll14xx_round_rate()
110 	for (i = 0; i < pll->rate_count; i++)  in clk_pll14xx_round_rate()
115 	return rate_table[i - 1].rate;  in clk_pll14xx_round_rate()
121 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll1416x_recalc_rate()  local
125 	pll_div = readl_relaxed(pll->base + 4);  in clk_pll1416x_recalc_rate()
139 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll1443x_recalc_rate()  local
144 	pll_div_ctl0 = readl_relaxed(pll->base + 4);  in clk_pll1443x_recalc_rate()
145 	pll_div_ctl1 = readl_relaxed(pll->base + 8);  in clk_pll1443x_recalc_rate()
168 	return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;  in clk_pll14xx_mp_change()
171 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)  in clk_pll14xx_wait_lock()  argument
175 	return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0,  in clk_pll14xx_wait_lock()
182 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll1416x_set_rate()  local
187 	rate = imx_get_pll_settings(pll, drate);  in clk_pll1416x_set_rate()
189 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in clk_pll1416x_set_rate()
191 		return -EINVAL;  in clk_pll1416x_set_rate()
194 	tmp = readl_relaxed(pll->base + 4);  in clk_pll1416x_set_rate()
198 		tmp |= rate->sdiv << SDIV_SHIFT;  in clk_pll1416x_set_rate()
199 		writel_relaxed(tmp, pll->base + 4);  in clk_pll1416x_set_rate()
201 		return 0;  in clk_pll1416x_set_rate()
204 	/* Bypass clock and set lock to pll output lock */  in clk_pll1416x_set_rate()
205 	tmp = readl_relaxed(pll->base);  in clk_pll1416x_set_rate()
207 	writel_relaxed(tmp, pll->base);  in clk_pll1416x_set_rate()
211 	writel_relaxed(tmp, pll->base);  in clk_pll1416x_set_rate()
215 	writel(tmp, pll->base);  in clk_pll1416x_set_rate()
217 	div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |  in clk_pll1416x_set_rate()
218 		(rate->sdiv << SDIV_SHIFT);  in clk_pll1416x_set_rate()
219 	writel_relaxed(div_val, pll->base + 0x4);  in clk_pll1416x_set_rate()
222 	 * According to SPEC, t3 - t2 need to be greater than  in clk_pll1416x_set_rate()
231 	writel_relaxed(tmp, pll->base);  in clk_pll1416x_set_rate()
234 	ret = clk_pll14xx_wait_lock(pll);  in clk_pll1416x_set_rate()
240 	writel_relaxed(tmp, pll->base);  in clk_pll1416x_set_rate()
242 	return 0;  in clk_pll1416x_set_rate()
248 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll1443x_set_rate()  local
253 	rate = imx_get_pll_settings(pll, drate);  in clk_pll1443x_set_rate()
255 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in clk_pll1443x_set_rate()
257 		return -EINVAL;  in clk_pll1443x_set_rate()
260 	tmp = readl_relaxed(pll->base + 4);  in clk_pll1443x_set_rate()
264 		tmp |= rate->sdiv << SDIV_SHIFT;  in clk_pll1443x_set_rate()
265 		writel_relaxed(tmp, pll->base + 4);  in clk_pll1443x_set_rate()
267 		tmp = rate->kdiv << KDIV_SHIFT;  in clk_pll1443x_set_rate()
268 		writel_relaxed(tmp, pll->base + 8);  in clk_pll1443x_set_rate()
270 		return 0;  in clk_pll1443x_set_rate()
274 	tmp = readl_relaxed(pll->base);  in clk_pll1443x_set_rate()
276 	writel_relaxed(tmp, pll->base);  in clk_pll1443x_set_rate()
280 	writel_relaxed(tmp, pll->base);  in clk_pll1443x_set_rate()
282 	div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |  in clk_pll1443x_set_rate()
283 		(rate->sdiv << SDIV_SHIFT);  in clk_pll1443x_set_rate()
284 	writel_relaxed(div_val, pll->base + 0x4);  in clk_pll1443x_set_rate()
285 	writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);  in clk_pll1443x_set_rate()
288 	 * According to SPEC, t3 - t2 need to be greater than  in clk_pll1443x_set_rate()
297 	writel_relaxed(tmp, pll->base);  in clk_pll1443x_set_rate()
300 	ret = clk_pll14xx_wait_lock(pll);  in clk_pll1443x_set_rate()
306 	writel_relaxed(tmp, pll->base);  in clk_pll1443x_set_rate()
308 	return 0;  in clk_pll1443x_set_rate()
313 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll14xx_prepare()  local
318 	 * RESETB = 1 from 0, PLL starts its normal  in clk_pll14xx_prepare()
321 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
323 		return 0;  in clk_pll14xx_prepare()
325 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
327 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
329 	ret = clk_pll14xx_wait_lock(pll);  in clk_pll14xx_prepare()
334 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
336 	return 0;  in clk_pll14xx_prepare()
341 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll14xx_is_prepared()  local
344 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_is_prepared()
346 	return (val & RST_MASK) ? 1 : 0;  in clk_pll14xx_is_prepared()
351 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll14xx_unprepare()  local
355 	 * Set RST to 0, power down mode is enabled and  in clk_pll14xx_unprepare()
358 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_unprepare()
360 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_unprepare()
389 	struct clk_pll14xx *pll;  in imx_dev_clk_hw_pll14xx()  local
395 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in imx_dev_clk_hw_pll14xx()
396 	if (!pll)  in imx_dev_clk_hw_pll14xx()
397 		return ERR_PTR(-ENOMEM);  in imx_dev_clk_hw_pll14xx()
400 	init.flags = pll_clk->flags;  in imx_dev_clk_hw_pll14xx()
404 	switch (pll_clk->type) {  in imx_dev_clk_hw_pll14xx()
406 		if (!pll_clk->rate_table)  in imx_dev_clk_hw_pll14xx()
415 		pr_err("%s: Unknown pll type for pll clk %s\n",  in imx_dev_clk_hw_pll14xx()
417 		kfree(pll);  in imx_dev_clk_hw_pll14xx()
418 		return ERR_PTR(-EINVAL);  in imx_dev_clk_hw_pll14xx()
421 	pll->base = base;  in imx_dev_clk_hw_pll14xx()
422 	pll->hw.init = &init;  in imx_dev_clk_hw_pll14xx()
423 	pll->type = pll_clk->type;  in imx_dev_clk_hw_pll14xx()
424 	pll->rate_table = pll_clk->rate_table;  in imx_dev_clk_hw_pll14xx()
425 	pll->rate_count = pll_clk->rate_count;  in imx_dev_clk_hw_pll14xx()
427 	val = readl_relaxed(pll->base + GNRL_CTL);  in imx_dev_clk_hw_pll14xx()
429 	writel_relaxed(val, pll->base + GNRL_CTL);  in imx_dev_clk_hw_pll14xx()
431 	hw = &pll->hw;  in imx_dev_clk_hw_pll14xx()
435 		pr_err("%s: failed to register pll %s %d\n",  in imx_dev_clk_hw_pll14xx()
437 		kfree(pll);  in imx_dev_clk_hw_pll14xx()