Lines Matching +full:pll +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file contains the utility functions to register the pll clocks.
13 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
24 /* PLL enable control bit offset in @con_reg register */
26 /* PLL lock status bit offset in @con_reg register */
36 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
38 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
41 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
52 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
53 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_round_rate()
57 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_round_rate()
63 return rate_table[i - 1].rate; in samsung_pll_round_rate()
68 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_enable() local
71 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_enable()
72 tmp |= BIT(pll->enable_offs); in samsung_pll3xxx_enable()
73 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_enable()
78 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_enable()
79 } while (!(tmp & BIT(pll->lock_offs))); in samsung_pll3xxx_enable()
81 return 0; in samsung_pll3xxx_enable()
86 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_disable() local
89 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_disable()
90 tmp &= ~BIT(pll->enable_offs); in samsung_pll3xxx_disable()
91 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_disable()
98 #define PLL2126_MDIV_MASK (0xff)
99 #define PLL2126_PDIV_MASK (0x3f)
100 #define PLL2126_SDIV_MASK (0x3)
103 #define PLL2126_SDIV_SHIFT (0)
108 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2126_recalc_rate() local
112 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2126_recalc_rate()
131 #define PLL3000_MDIV_MASK (0xff)
132 #define PLL3000_PDIV_MASK (0x3)
133 #define PLL3000_SDIV_MASK (0x3)
136 #define PLL3000_SDIV_SHIFT (0)
141 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3000_recalc_rate() local
145 pll_con = readl_relaxed(pll->con_reg); in samsung_pll3000_recalc_rate()
166 #define PLL35XX_MDIV_MASK (0x3FF)
167 #define PLL35XX_PDIV_MASK (0x3F)
168 #define PLL35XX_SDIV_MASK (0x7)
171 #define PLL35XX_SDIV_SHIFT (0)
178 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_recalc_rate() local
182 pll_con = readl_relaxed(pll->con_reg); in samsung_pll35xx_recalc_rate()
201 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
207 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_set_rate() local
212 rate = samsung_get_pll_settings(pll, drate); in samsung_pll35xx_set_rate()
214 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll35xx_set_rate()
216 return -EINVAL; in samsung_pll35xx_set_rate()
219 tmp = readl_relaxed(pll->con_reg); in samsung_pll35xx_set_rate()
224 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; in samsung_pll35xx_set_rate()
225 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
227 return 0; in samsung_pll35xx_set_rate()
230 /* Set PLL lock time. */ in samsung_pll35xx_set_rate()
231 writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, in samsung_pll35xx_set_rate()
232 pll->lock_reg); in samsung_pll35xx_set_rate()
234 /* Change PLL PMS values */ in samsung_pll35xx_set_rate()
238 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | in samsung_pll35xx_set_rate()
239 (rate->pdiv << PLL35XX_PDIV_SHIFT) | in samsung_pll35xx_set_rate()
240 (rate->sdiv << PLL35XX_SDIV_SHIFT); in samsung_pll35xx_set_rate()
241 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
243 /* Wait until the PLL is locked if it is enabled. */ in samsung_pll35xx_set_rate()
244 if (tmp & BIT(pll->enable_offs)) { in samsung_pll35xx_set_rate()
247 tmp = readl_relaxed(pll->con_reg); in samsung_pll35xx_set_rate()
248 } while (!(tmp & BIT(pll->lock_offs))); in samsung_pll35xx_set_rate()
250 return 0; in samsung_pll35xx_set_rate()
271 #define PLL36XX_KDIV_MASK (0xFFFF)
272 #define PLL36XX_MDIV_MASK (0x1FF)
273 #define PLL36XX_PDIV_MASK (0x3F)
274 #define PLL36XX_SDIV_MASK (0x7)
277 #define PLL36XX_SDIV_SHIFT (0)
278 #define PLL36XX_KDIV_SHIFT (0)
285 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_recalc_rate() local
290 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_recalc_rate()
291 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_recalc_rate()
313 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || in samsung_pll36xx_mpk_change()
314 rate->kdiv != old_kdiv); in samsung_pll36xx_mpk_change()
320 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_set_rate() local
324 rate = samsung_get_pll_settings(pll, drate); in samsung_pll36xx_set_rate()
326 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll36xx_set_rate()
328 return -EINVAL; in samsung_pll36xx_set_rate()
331 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_set_rate()
332 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_set_rate()
337 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); in samsung_pll36xx_set_rate()
338 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
340 return 0; in samsung_pll36xx_set_rate()
343 /* Set PLL lock time. */ in samsung_pll36xx_set_rate()
344 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll36xx_set_rate()
346 /* Change PLL PMS values */ in samsung_pll36xx_set_rate()
350 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | in samsung_pll36xx_set_rate()
351 (rate->pdiv << PLL36XX_PDIV_SHIFT) | in samsung_pll36xx_set_rate()
352 (rate->sdiv << PLL36XX_SDIV_SHIFT); in samsung_pll36xx_set_rate()
353 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
356 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; in samsung_pll36xx_set_rate()
357 writel_relaxed(pll_con1, pll->con_reg + 4); in samsung_pll36xx_set_rate()
360 if (pll_con0 & BIT(pll->enable_offs)) { in samsung_pll36xx_set_rate()
363 tmp = readl_relaxed(pll->con_reg); in samsung_pll36xx_set_rate()
364 } while (!(tmp & BIT(pll->lock_offs))); in samsung_pll36xx_set_rate()
367 return 0; in samsung_pll36xx_set_rate()
388 #define PLL45XX_MDIV_MASK (0x3FF)
389 #define PLL45XX_PDIV_MASK (0x3F)
390 #define PLL45XX_SDIV_MASK (0x7)
391 #define PLL45XX_AFC_MASK (0x1F)
394 #define PLL45XX_SDIV_SHIFT (0)
395 #define PLL45XX_AFC_SHIFT (0)
403 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_recalc_rate() local
407 pll_con = readl_relaxed(pll->con_reg); in samsung_pll45xx_recalc_rate()
412 if (pll->type == pll_4508) in samsung_pll45xx_recalc_rate()
413 sdiv = sdiv - 1; in samsung_pll45xx_recalc_rate()
430 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll45xx_mp_change()
431 || old_afc != rate->afc); in samsung_pll45xx_mp_change()
437 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_set_rate() local
443 rate = samsung_get_pll_settings(pll, drate); in samsung_pll45xx_set_rate()
445 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll45xx_set_rate()
447 return -EINVAL; in samsung_pll45xx_set_rate()
450 con0 = readl_relaxed(pll->con_reg); in samsung_pll45xx_set_rate()
451 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
456 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; in samsung_pll45xx_set_rate()
457 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
459 return 0; in samsung_pll45xx_set_rate()
462 /* Set PLL PMS values. */ in samsung_pll45xx_set_rate()
466 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
467 (rate->pdiv << PLL45XX_PDIV_SHIFT) | in samsung_pll45xx_set_rate()
468 (rate->sdiv << PLL45XX_SDIV_SHIFT); in samsung_pll45xx_set_rate()
470 /* Set PLL AFC value. */ in samsung_pll45xx_set_rate()
471 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
473 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
475 /* Set PLL lock time. */ in samsung_pll45xx_set_rate()
476 switch (pll->type) { in samsung_pll45xx_set_rate()
478 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
481 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
488 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
489 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
493 while (!(readl_relaxed(pll->con_reg) & PLL45XX_LOCKED)) { in samsung_pll45xx_set_rate()
497 pr_err("%s: could not lock PLL %s\n", in samsung_pll45xx_set_rate()
499 return -EFAULT; in samsung_pll45xx_set_rate()
505 return 0; in samsung_pll45xx_set_rate()
524 #define PLL46XX_MDIV_MASK (0x1FF)
525 #define PLL1460X_MDIV_MASK (0x3FF)
527 #define PLL46XX_PDIV_MASK (0x3F)
528 #define PLL46XX_SDIV_MASK (0x7)
532 #define PLL46XX_SDIV_SHIFT (0)
534 #define PLL46XX_KDIV_MASK (0xFFFF)
535 #define PLL4650C_KDIV_MASK (0xFFF)
536 #define PLL46XX_KDIV_SHIFT (0)
537 #define PLL46XX_MFR_MASK (0x3F)
538 #define PLL46XX_MRR_MASK (0x1F)
539 #define PLL46XX_KDIV_SHIFT (0)
550 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_recalc_rate() local
554 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_recalc_rate()
555 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll46xx_recalc_rate()
556 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? in samsung_pll46xx_recalc_rate()
560 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : in samsung_pll46xx_recalc_rate()
563 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; in samsung_pll46xx_recalc_rate()
581 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll46xx_mpk_change()
582 || old_kdiv != rate->kdiv); in samsung_pll46xx_mpk_change()
588 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_set_rate() local
594 rate = samsung_get_pll_settings(pll, drate); in samsung_pll46xx_set_rate()
596 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll46xx_set_rate()
598 return -EINVAL; in samsung_pll46xx_set_rate()
601 con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_set_rate()
602 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
607 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; in samsung_pll46xx_set_rate()
608 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
610 return 0; in samsung_pll46xx_set_rate()
613 /* Set PLL lock time. */ in samsung_pll46xx_set_rate()
614 lock = rate->pdiv * PLL46XX_LOCK_FACTOR; in samsung_pll46xx_set_rate()
615 if (lock > 0xffff) in samsung_pll46xx_set_rate()
616 /* Maximum lock time bitfield is 16-bit. */ in samsung_pll46xx_set_rate()
617 lock = 0xffff; in samsung_pll46xx_set_rate()
619 /* Set PLL PMS and VSEL values. */ in samsung_pll46xx_set_rate()
620 if (pll->type == pll_1460x) { in samsung_pll46xx_set_rate()
629 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; in samsung_pll46xx_set_rate()
632 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | in samsung_pll46xx_set_rate()
633 (rate->pdiv << PLL46XX_PDIV_SHIFT) | in samsung_pll46xx_set_rate()
634 (rate->sdiv << PLL46XX_SDIV_SHIFT); in samsung_pll46xx_set_rate()
636 /* Set PLL K, MFR and MRR values. */ in samsung_pll46xx_set_rate()
637 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
641 con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) | in samsung_pll46xx_set_rate()
642 (rate->mfr << PLL46XX_MFR_SHIFT) | in samsung_pll46xx_set_rate()
643 (rate->mrr << PLL46XX_MRR_SHIFT); in samsung_pll46xx_set_rate()
645 /* Write configuration to PLL */ in samsung_pll46xx_set_rate()
646 writel_relaxed(lock, pll->lock_reg); in samsung_pll46xx_set_rate()
647 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
648 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
652 while (!(readl_relaxed(pll->con_reg) & PLL46XX_LOCKED)) { in samsung_pll46xx_set_rate()
656 pr_err("%s: could not lock PLL %s\n", in samsung_pll46xx_set_rate()
658 return -EFAULT; in samsung_pll46xx_set_rate()
664 return 0; in samsung_pll46xx_set_rate()
681 #define PLL6552_MDIV_MASK 0x3ff
682 #define PLL6552_PDIV_MASK 0x3f
683 #define PLL6552_SDIV_MASK 0x7
688 #define PLL6552_SDIV_SHIFT 0
693 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6552_recalc_rate() local
697 pll_con = readl_relaxed(pll->con_reg); in samsung_pll6552_recalc_rate()
698 if (pll->type == pll_6552_s3c2416) { in samsung_pll6552_recalc_rate()
721 #define PLL6553_MDIV_MASK 0xff
722 #define PLL6553_PDIV_MASK 0x3f
723 #define PLL6553_SDIV_MASK 0x7
724 #define PLL6553_KDIV_MASK 0xffff
727 #define PLL6553_SDIV_SHIFT 0
728 #define PLL6553_KDIV_SHIFT 0
733 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6553_recalc_rate() local
737 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll6553_recalc_rate()
738 pll_con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll6553_recalc_rate()
756 * PLL Clock Type of S3C24XX before S3C2443
759 #define PLLS3C2410_MDIV_MASK (0xff)
760 #define PLLS3C2410_PDIV_MASK (0x1f)
761 #define PLLS3C2410_SDIV_MASK (0x3)
764 #define PLLS3C2410_SDIV_SHIFT (0)
766 #define PLLS3C2410_ENABLE_REG_OFFSET 0x10
771 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2410_pll_recalc_rate() local
775 pll_con = readl_relaxed(pll->con_reg); in samsung_s3c2410_pll_recalc_rate()
789 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2440_mpll_recalc_rate() local
793 pll_con = readl_relaxed(pll->con_reg); in samsung_s3c2440_mpll_recalc_rate()
807 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2410_pll_set_rate() local
812 rate = samsung_get_pll_settings(pll, drate); in samsung_s3c2410_pll_set_rate()
814 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_s3c2410_pll_set_rate()
816 return -EINVAL; in samsung_s3c2410_pll_set_rate()
819 tmp = readl_relaxed(pll->con_reg); in samsung_s3c2410_pll_set_rate()
821 /* Change PLL PMS values */ in samsung_s3c2410_pll_set_rate()
825 tmp |= (rate->mdiv << PLLS3C2410_MDIV_SHIFT) | in samsung_s3c2410_pll_set_rate()
826 (rate->pdiv << PLLS3C2410_PDIV_SHIFT) | in samsung_s3c2410_pll_set_rate()
827 (rate->sdiv << PLLS3C2410_SDIV_SHIFT); in samsung_s3c2410_pll_set_rate()
828 writel_relaxed(tmp, pll->con_reg); in samsung_s3c2410_pll_set_rate()
833 return 0; in samsung_s3c2410_pll_set_rate()
838 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2410_pll_enable() local
839 u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); in samsung_s3c2410_pll_enable()
847 writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); in samsung_s3c2410_pll_enable()
853 return 0; in samsung_s3c2410_pll_enable()
922 #define PLL2550X_R_MASK (0x1)
923 #define PLL2550X_P_MASK (0x3F)
924 #define PLL2550X_M_MASK (0x3FF)
925 #define PLL2550X_S_MASK (0x7)
929 #define PLL2550X_S_SHIFT (0)
934 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550x_recalc_rate() local
938 pll_stat = readl_relaxed(pll->con_reg); in samsung_pll2550x_recalc_rate()
941 return 0; in samsung_pll2550x_recalc_rate()
963 #define PLL2550XX_M_MASK 0x3FF
964 #define PLL2550XX_P_MASK 0x3F
965 #define PLL2550XX_S_MASK 0x7
966 #define PLL2550XX_LOCK_STAT_MASK 0x1
969 #define PLL2550XX_S_SHIFT 0
975 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_recalc_rate() local
979 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2550xx_recalc_rate()
1003 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_set_rate() local
1008 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2550xx_set_rate()
1010 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2550xx_set_rate()
1012 return -EINVAL; in samsung_pll2550xx_set_rate()
1015 tmp = readl_relaxed(pll->con_reg); in samsung_pll2550xx_set_rate()
1017 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { in samsung_pll2550xx_set_rate()
1020 tmp |= rate->sdiv << PLL2550XX_S_SHIFT; in samsung_pll2550xx_set_rate()
1021 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1023 return 0; in samsung_pll2550xx_set_rate()
1026 /* Set PLL lock time. */ in samsung_pll2550xx_set_rate()
1027 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll2550xx_set_rate()
1029 /* Change PLL PMS values */ in samsung_pll2550xx_set_rate()
1033 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | in samsung_pll2550xx_set_rate()
1034 (rate->pdiv << PLL2550XX_P_SHIFT) | in samsung_pll2550xx_set_rate()
1035 (rate->sdiv << PLL2550XX_S_SHIFT); in samsung_pll2550xx_set_rate()
1036 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1041 tmp = readl_relaxed(pll->con_reg); in samsung_pll2550xx_set_rate()
1045 return 0; in samsung_pll2550xx_set_rate()
1065 #define PLL2650X_M_MASK 0x1ff
1066 #define PLL2650X_P_MASK 0x3f
1067 #define PLL2650X_S_MASK 0x7
1068 #define PLL2650X_K_MASK 0xffff
1069 #define PLL2650X_LOCK_STAT_MASK 0x1
1072 #define PLL2650X_S_SHIFT 0
1073 #define PLL2650X_K_SHIFT 0
1080 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_recalc_rate() local
1085 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_recalc_rate()
1090 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_recalc_rate()
1103 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_set_rate() local
1108 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2650x_set_rate()
1110 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2650x_set_rate()
1112 return -EINVAL; in samsung_pll2650x_set_rate()
1115 con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_set_rate()
1116 con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_set_rate()
1118 /* Set PLL lock time. */ in samsung_pll2650x_set_rate()
1119 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg); in samsung_pll2650x_set_rate()
1121 /* Change PLL PMS values */ in samsung_pll2650x_set_rate()
1125 con0 |= (rate->mdiv << PLL2650X_M_SHIFT) | in samsung_pll2650x_set_rate()
1126 (rate->pdiv << PLL2650X_P_SHIFT) | in samsung_pll2650x_set_rate()
1127 (rate->sdiv << PLL2650X_S_SHIFT); in samsung_pll2650x_set_rate()
1129 writel_relaxed(con0, pll->con_reg); in samsung_pll2650x_set_rate()
1132 con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT); in samsung_pll2650x_set_rate()
1133 writel_relaxed(con1, pll->con_reg + 4); in samsung_pll2650x_set_rate()
1137 con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_set_rate()
1141 return 0; in samsung_pll2650x_set_rate()
1163 #define PLL2650XX_SDIV_SHIFT 0
1164 #define PLL2650XX_KDIV_SHIFT 0
1165 #define PLL2650XX_MDIV_MASK 0x1ff
1166 #define PLL2650XX_PDIV_MASK 0x3f
1167 #define PLL2650XX_SDIV_MASK 0x7
1168 #define PLL2650XX_KDIV_MASK 0xffff
1176 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_recalc_rate() local
1181 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_recalc_rate()
1182 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_recalc_rate()
1198 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_set_rate() local
1202 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2650xx_set_rate()
1204 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2650xx_set_rate()
1206 return -EINVAL; in samsung_pll2650xx_set_rate()
1209 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_set_rate()
1210 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1212 /* Change PLL PMS values */ in samsung_pll2650xx_set_rate()
1216 pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; in samsung_pll2650xx_set_rate()
1217 pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; in samsung_pll2650xx_set_rate()
1218 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; in samsung_pll2650xx_set_rate()
1223 pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) in samsung_pll2650xx_set_rate()
1226 /* Set PLL lock time. */ in samsung_pll2650xx_set_rate()
1227 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); in samsung_pll2650xx_set_rate()
1229 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll2650xx_set_rate()
1230 writel_relaxed(pll_con2, pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1233 tmp = readl_relaxed(pll->con_reg); in samsung_pll2650xx_set_rate()
1234 } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT))); in samsung_pll2650xx_set_rate()
1236 return 0; in samsung_pll2650xx_set_rate()
1253 struct samsung_clk_pll *pll; in _samsung_clk_register_pll() local
1257 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in _samsung_clk_register_pll()
1258 if (!pll) { in _samsung_clk_register_pll()
1259 pr_err("%s: could not allocate pll clk %s\n", in _samsung_clk_register_pll()
1260 __func__, pll_clk->name); in _samsung_clk_register_pll()
1264 init.name = pll_clk->name; in _samsung_clk_register_pll()
1265 init.flags = pll_clk->flags; in _samsung_clk_register_pll()
1266 init.parent_names = &pll_clk->parent_name; in _samsung_clk_register_pll()
1269 if (pll_clk->rate_table) { in _samsung_clk_register_pll()
1271 for (len = 0; pll_clk->rate_table[len].rate != 0; ) in _samsung_clk_register_pll()
1274 pll->rate_count = len; in _samsung_clk_register_pll()
1275 pll->rate_table = kmemdup(pll_clk->rate_table, in _samsung_clk_register_pll()
1276 pll->rate_count * in _samsung_clk_register_pll()
1279 WARN(!pll->rate_table, in _samsung_clk_register_pll()
1281 __func__, pll_clk->name); in _samsung_clk_register_pll()
1284 switch (pll_clk->type) { in _samsung_clk_register_pll()
1297 pll->enable_offs = PLL35XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1298 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1299 if (!pll->rate_table) in _samsung_clk_register_pll()
1309 if (!pll->rate_table) in _samsung_clk_register_pll()
1317 pll->enable_offs = PLL36XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1318 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1319 if (!pll->rate_table) in _samsung_clk_register_pll()
1335 if (!pll->rate_table) in _samsung_clk_register_pll()
1341 if (!pll->rate_table) in _samsung_clk_register_pll()
1347 if (!pll->rate_table) in _samsung_clk_register_pll()
1353 if (!pll->rate_table) in _samsung_clk_register_pll()
1362 if (!pll->rate_table) in _samsung_clk_register_pll()
1368 if (!pll->rate_table) in _samsung_clk_register_pll()
1374 if (!pll->rate_table) in _samsung_clk_register_pll()
1380 pr_warn("%s: Unknown pll type for pll clk %s\n", in _samsung_clk_register_pll()
1381 __func__, pll_clk->name); in _samsung_clk_register_pll()
1384 pll->hw.init = &init; in _samsung_clk_register_pll()
1385 pll->type = pll_clk->type; in _samsung_clk_register_pll()
1386 pll->lock_reg = base + pll_clk->lock_offset; in _samsung_clk_register_pll()
1387 pll->con_reg = base + pll_clk->con_offset; in _samsung_clk_register_pll()
1389 ret = clk_hw_register(ctx->dev, &pll->hw); in _samsung_clk_register_pll()
1391 pr_err("%s: failed to register pll clock %s : %d\n", in _samsung_clk_register_pll()
1392 __func__, pll_clk->name, ret); in _samsung_clk_register_pll()
1393 kfree(pll); in _samsung_clk_register_pll()
1397 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); in _samsung_clk_register_pll()
1406 for (cnt = 0; cnt < nr_pll; cnt++) in samsung_clk_register_pll()