| /Linux-v5.4/Documentation/networking/dsa/ |
| D | bcm_sf2.rst | 5 Broadcom's Starfighter 2 Ethernet switch hardware block is commonly found and
8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
12 The switch is typically deployed in a configuration involving between 5 to 13
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
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| /Linux-v5.4/Documentation/devicetree/bindings/net/dsa/ |
| D | b53.txt | 6 - compatible: For external switch chips, compatible string must be exactly one
18 "brcm,bcm11360-srab" and the mandatory "brcm,cygnus-srab" string
20 For the BCM5310x SoCs with an integrated switch, must be one of:
21 "brcm,bcm53010-srab"
22 "brcm,bcm53011-srab"
23 "brcm,bcm53012-srab"
24 "brcm,bcm53018-srab"
25 "brcm,bcm53019-srab" and the mandatory "brcm,bcm5301x-srab" string
27 For the BCM5831X/BCM1140x SoCs with an integrated switch, must be one of:
28 "brcm,bcm11404-srab"
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| D | vitesse,vsc73xx.txt | 9 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
10 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
11 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
12 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
16 If SPI interface is used, the device tree node is an SPI device so it must
17 reside inside a SPI bus device tree node, see spi/spi-bus.txt
19 When the chip is connected to a parallel memory bus and work in memory-mapped
20 I/O mode, a platform device is used to represent the vsc73xx. In this case it
25 - compatible: must be exactly one of:
30 - gpio-controller: indicates that this switch is also a GPIO controller,
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| D | mt7530.txt | 6 - compatible: may be compatible = "mediatek,mt7530"
8 - #address-cells: Must be 1.
9 - #size-cells: Must be 0.
10 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
11 on multi-chip module belong to MT7623A has or the remotely standalone
14 If compatible mediatek,mt7530 is set then the following properties are required
16 - core-supply: Phandle to the regulator node necessary for the core power.
17 - io-supply: Phandle to the regulator node necessary for the I/O power.
18 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
21 If the property mediatek,mcm isn't defined, following property is required
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| D | qca8k.txt | 5 - compatible: should be one of:
9 - #size-cells: must be 0
10 - #address-cells: must be 1
14 - reset-gpios: GPIO to be used to reset the whole device
18 The integrated switch subnode should be specified according to the binding
19 described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
20 mdio-bus each subnode describing a port needs to have a valid phandle
21 referencing the internal PHY it is connected to. This is because there's no
22 N:N mapping of port and PHY id.
24 Don't use mixed external and internal mdio-bus configurations, as this is
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| D | lan9303.txt | 2 -------------------------------------------------
6 - compatible: should be
7 - "smsc,lan9303-i2c" for I2C managed mode
9 - "smsc,lan9303-mdio" for mdio managed mode
13 - reset-gpios: GPIO to be used to reset the whole device
14 - reset-duration: reset duration in milliseconds, defaults to 200 ms
18 The integrated switch subnode should be specified according to the binding
19 described in dsa/dsa.txt. The CPU port of this switch is always port 0.
21 Note: always use 'reg = <0/1/2>;' for the three DSA ports, even if the device is
23 auto-detected and mapped accordingly.
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| /Linux-v5.4/Documentation/devicetree/bindings/net/ |
| D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Generic Binding
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
16 # case, the node name is the one we want to match on, while the
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| D | snps,dwc-qos-ethernet.txt | 3 This binding is deprecated, but it continues to be supported, but new
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
17 Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
18 - "snps,dwc-qos-ethernet-4.10"
19 This combination is deprecated. It should be treated as equivalent to
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
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| D | allwinner,sun8i-a83t-emac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <maxime.ripard@bootlin.com>
16 - const: allwinner,sun8i-a83t-emac
17 - const: allwinner,sun8i-h3-emac
18 - const: allwinner,sun8i-r40-emac
19 - const: allwinner,sun8i-v3s-emac
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| D | brcm,unimac-mdio.txt | 4 - compatible: should one from "brcm,genet-mdio-v1", "brcm,genet-mdio-v2",
5 "brcm,genet-mdio-v3", "brcm,genet-mdio-v4", "brcm,genet-mdio-v5" or
6 "brcm,unimac-mdio"
7 - reg: address and length of the register set for the device, first one is the
8 base register, and the second one is optional and for indirect accesses to
9 larger than 16-bits MDIO transactions
10 - reg-names: name(s) of the register must be "mdio" and optional "mdio_indir_rw"
11 - #size-cells: must be 1
12 - #address-cells: must be 0
15 - interrupts: must be one if the interrupt is shared with the Ethernet MAC or
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| D | cortina,gemini-ethernet.txt | 4 This ethernet controller is found in the Gemini SoC family:
9 - compatible: must be "cortina,gemini-ethernet"
10 - reg: must contain the global registers and the V-bit and A-bit
12 - syscon: a phandle to the system controller
13 - #address-cells: must be specified, must be <1>
14 - #size-cells: must be specified, must be <1>
15 - ranges: should be state like this giving a 1:1 address translation
23 - port0: contains the resources for ethernet port 0
24 - port1: contains the resources for ethernet port 1
27 - compatible: must be "cortina,gemini-ethernet-port"
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| /Linux-v5.4/drivers/net/ethernet/wiznet/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
10 ---help---
23 ---help---
26 W5100 is a single chip with integrated 10/100 Ethernet MAC,
27 PHY and hardware TCP/IP stack, but this driver is limited to
28 the MAC and PHY functions only, onchip TCP/IP is unused.
36 ---help---
39 W5300 is a single chip with integrated 10/100 Ethernet MAC,
40 PHY and hardware TCP/IP stack, but this driver is limited to
41 the MAC and PHY functions only, onchip TCP/IP is unused.
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| /Linux-v5.4/arch/arm/boot/dts/ |
| D | rk3228-evb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
9 compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
16 vcc_phy: vcc-phy-regulator {
17 compatible = "regulator-fixed";
18 enable-active-high;
19 regulator-name = "vcc_phy";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
22 regulator-always-on;
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| D | rk3229-xms6.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/input/input.h>
17 dc_12v: dc-12v-regulator {
18 compatible = "regulator-fixed";
19 regulator-name = "dc_12v";
20 regulator-always-on;
21 regulator-boot-on;
22 regulator-min-microvolt = <12000000>;
23 regulator-max-microvolt = <12000000>;
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| /Linux-v5.4/drivers/net/phy/ |
| D | intel-xway.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/phy.h>
15 #define XWAY_MDIO_INIT_WOL BIT(15) /* Wake-On-LAN */
19 #define XWAY_MDIO_INIT_ANE BIT(11) /* Auto-Neg error */
20 #define XWAY_MDIO_INIT_ANC BIT(10) /* Auto-Neg complete */
21 #define XWAY_MDIO_INIT_ADSC BIT(5) /* Link auto-downspeed detect */
30 #define ADVERTISED_MPD BIT(10) /* Multi-port device */
171 * In most cases only one LED is connected to this phy, so in xway_gphy_config_init()
172 * configure them all to constant on and pulse mode. LED3 is in xway_gphy_config_init()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY Layer Configuration
18 This internal symbol is used for link time dependencies and it
19 reflects whether the mdio_bus/mdio_device code is built as a
20 loadable module or built-in.
30 controllers found in the ASPEED AST2600 SoC. This is a driver for the
31 third revision of the ASPEED MDIO register interface - the first two
35 AST2500 SoCs, so say N if AST2600 support is not required.
69 to a parent bus. Switching between child busses is done by
91 selection is under the control of GPIO lines.
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| D | bcm63xx.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Broadcom 63xx SOCs integrated PHYs
5 #include "bcm-phy-lib.h"
7 #include <linux/phy.h>
16 MODULE_DESCRIPTION("Broadcom 63xx internal PHY driver");
28 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in bcm63xx_config_intr()
41 /* ASYM_PAUSE bit is marked RO in datasheet, so don't cheat */ in bcm63xx_config_init()
42 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported); in bcm63xx_config_init()
73 /* same phy as above, with just a different OUI */
|
| D | mdio-bcm-unimac.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2014-2017 Broadcom
9 #include <linux/phy.h>
21 #include <linux/platform_data/mdio-bcm-unimac.h>
52 * peripheral registers for CPU-native byte order. in unimac_mdio_readl()
55 return __raw_readl(priv->base + offset); in unimac_mdio_readl()
57 return readl_relaxed(priv->base + offset); in unimac_mdio_readl()
64 __raw_writel(val, priv->base + offset); in unimac_mdio_writel()
66 writel_relaxed(val, priv->base + offset); in unimac_mdio_writel()
93 } while (--timeout); in unimac_mdio_poll()
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| /Linux-v5.4/drivers/scsi/mpt3sas/ |
| D | mpt3sas_base.h | 2 * This is the Fusion MPT base driver providing common API layer interface
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.h
6 * Copyright (C) 2012-2014 LSI Corporation
7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
10 * This program is free software; you can redistribute it and/or
15 * This program is distributed in the hope that it will be useful,
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
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| /Linux-v5.4/Documentation/devicetree/bindings/usb/ |
| D | iproc-udc.txt | 3 The device node is used for UDCs integrated into Broadcom's
4 iProc family (Northstar2, Cygnus) of SoCs'. The UDC is based
9 - compatible: Add the compatibility strings for supported platforms.
10 For Broadcom NS2 platform, add "brcm,ns2-udc","brcm,iproc-udc".
11 For Broadcom Cygnus platform, add "brcm,cygnus-udc", "brcm,iproc-udc".
12 - reg: Offset and length of UDC register set
13 - interrupts: description of interrupt line
14 - phys: phandle to phy node.
18 compatible = "brcm,ns2-udc", "brcm,iproc-udc";
|
| /Linux-v5.4/Documentation/devicetree/bindings/pci/ |
| D | brcm,iproc-pcie.txt | 4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
14 root complex is connected to emulated endpoint devices internal to the ASIC
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
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| /Linux-v5.4/arch/arc/boot/dts/ |
| D | vdk_axs10x_mb.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
10 compatible = "simple-bus";
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&mb_intc>;
18 compatible = "fixed-clock";
19 clock-frequency = <50000000>;
20 #clock-cells = <0>;
24 compatible = "fixed-clock";
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| /Linux-v5.4/Documentation/devicetree/bindings/mfd/ |
| D | mfd.txt | 1 Multi-Function Devices (MFD)
4 more than one non-unique yet varying hardware functionality.
8 - A mixed signal ASIC on an external bus, sometimes a PMIC (Power Management
9 Integrated Circuit) that is manufactured in a lower technology node (rough
11 drivers, level shifters, PHY (physical interfaces to things like USB or
14 - A range of memory registers containing "miscellaneous system registers" also
20 - compatible : "simple-mfd" - this signifies that the operating system should
22 "simple-bus" indicates when to see subnodes as children for a simple
23 memory-mapped bus. For more complex devices, when the nexus driver has to
28 - ranges: Describes the address mapping relationship to the parent. Should set
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| /Linux-v5.4/drivers/ata/ |
| D | sata_sis.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sata_sis.c - Silicon Integrated Systems SATA
6 * Please ALWAYS copy linux-ide@vger.kernel.org
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
37 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
38 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
39 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
94 MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller");
101 struct ata_port *ap = link->ap; in get_scr_cfg_addr()
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| /Linux-v5.4/drivers/net/dsa/ |
| D | vitesse-vsc73xx-core.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
8 * These switches have a built-in 8051 CPU and can download and execute a
10 * handling the switch in a memory-mapped manner by connecting to that external
31 #include "vitesse-vsc73xx.h"
33 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */
266 #define IS_7385(a) ((a)->chipid == VSC73XX_CHIPID_ID_7385)
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