Lines Matching +full:phy +full:- +full:is +full:- +full:integrated
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Generic Binding
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
16 # case, the node name is the one we want to match on, while the
17 # compatible is optional.
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
28 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
32 - const: ethernet-phy-ieee802.3-c22
34 - const: ethernet-phy-ieee802.3-c45
36 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
38 If the PHY reports an incorrect ID (or none at all) then the
39 compatible list may contain an entry with the correct PHY ID
41 The first group of digits is the 16 bit Phy Identifier 1
42 register, this is the chip vendor OUI bits 3:18. The
43 second group of digits is the Phy Identifier 2 register,
44 this is the chip vendor OUI bits 19:24, followed by 10
46 - items:
47 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
48 - const: ethernet-phy-ieee802.3-c45
54 The ID number for the PHY.
59 max-speed:
61 - 10
62 - 100
63 - 1000
64 - 2500
65 - 5000
66 - 10000
67 - 20000
68 - 25000
69 - 40000
70 - 50000
71 - 56000
72 - 100000
73 - 200000
75 Maximum PHY supported speed in Mbits / seconds.
77 broken-turn-around:
80 If set, indicates the PHY device does not correctly release
83 enet-phy-lane-swap:
86 If set, indicates the PHY will swap the TX/RX lanes to
90 eee-broken-100tx:
96 eee-broken-1000t:
102 eee-broken-10gt:
108 eee-broken-1000kx:
114 eee-broken-10gkx4:
120 eee-broken-10gkr:
126 phy-is-integrated:
129 If set, indicates that the PHY is integrated into the same
131 should be configured to ensure the integrated PHY is
133 should be configured so that the external PHY is used.
138 reset-names:
139 const: phy
141 reset-gpios:
144 The GPIO phandle and specifier for the PHY reset signal.
146 reset-assert-us:
149 property is missing the delay will be skipped.
151 reset-deassert-us:
154 this property is missing the delay will be skipped.
157 - reg
160 - |
162 #address-cells = <1>;
163 #size-cells = <0>;
165 ethernet-phy@0 {
166 compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45";
167 interrupt-parent = <&PIC>;
172 reset-names = "phy";
173 reset-gpios = <&gpio1 4 1>;
174 reset-assert-us = <1000>;
175 reset-deassert-us = <2000>;