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/Linux-v5.4/Documentation/devicetree/bindings/mtd/
Dgpmi-nand.txt1 * Freescale General-Purpose Media Interface (GPMI)
3 The GPMI nand controller provides an interface to control the
4 NAND flash chips.
7 - compatible : should be "fsl,<chip>-gpmi-nand", chip can be:
13 - reg : should contain registers location and length for gpmi and bch.
14 - reg-names: Should contain the reg names "gpmi-nand" and "bch"
15 - interrupts : BCH interrupt number.
16 - interrupt-names : Should be "bch".
17 - dmas: DMA specifier, consisting of a phandle to DMA controller node
19 Refer to dma.txt and fsl-mxs-dma.txt for details.
[all …]
Dbrcm,brcmnand.txt1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
5 registers and for its data input/output buffer. On some SoCs, this controller is
6 paired with a custom DMA engine (inventively named "Flash DMA") which supports
10 available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
17 added on top of the base core controller.
19 the core NAND controller, of the following form:
[all …]
Ddavinci-nand.txt1 Device tree bindings for Texas instruments Davinci/Keystone NAND controller
4 NAND interface contains.
7 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
8 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
12 - compatible: "ti,davinci-nand"
13 "ti,keystone-nand"
15 - reg: Contains 2 offset/length values:
16 - offset and length for the access window.
17 - offset and length for accessing the AEMIF
20 - ti,davinci-chipselect: number of chipselect. Indicates on the
[all …]
Dingenic,jz4780-nand.txt1 * Ingenic JZ4780 NAND/ECC
3 This file documents the device tree bindings for NAND flash devices on the
4 JZ4780. NAND devices are connected to the NEMC controller (described in
5 memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
8 Required NAND controller device properties:
9 - compatible: Should be one of:
10 * ingenic,jz4740-nand
11 * ingenic,jz4725b-nand
12 * ingenic,jz4780-nand
13 - reg: For each bank with a NAND chip attached, should specify a bank number,
[all …]
Dsamsung-s3c2410.txt1 * Samsung S3C2410 and compatible NAND flash controller
4 - compatible : The possible values are:
5 "samsung,s3c2410-nand"
6 "samsung,s3c2412-nand"
7 "samsung,s3c2440-nand"
8 - reg : register's location and length.
9 - #address-cells, #size-cells : see nand-controller.yaml
10 - clocks : phandle to the nand controller clock
11 - clock-names : must contain "nand"
14 Child nodes representing the available nand chips.
[all …]
Dvf610-nfc.txt1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
[all …]
Dstm32-fmc2-nand.txt2 NAND Interface
5 - compatible: Should be one of:
6 * st,stm32mp15-fmc2
7 - reg: NAND flash controller memory areas.
12 - interrupts: The interrupt number
13 - pinctrl-0: Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)
14 - clocks: The clock needed by the NAND flash controller
17 - resets: Reference to a reset controller asserting the FMC controller
18 - dmas: DMA specifiers (see: dma/stm32-mdma.txt)
19 - dma-names: Must be "tx", "rx" and "ecc"
[all …]
Datmel-nand.txt1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
[all …]
Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
[all …]
Dlpc32xx-slc.txt1 NXP LPC32xx SoC NAND SLC controller
4 - compatible: "nxp,lpc3220-slc"
5 - reg: Address and size of the controller
6 - nand-on-flash-bbt: Use bad block table on flash
7 - gpios: GPIO specification for NAND write protect
11 - nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
12 - nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
15 - nxp,wwidth: Write pulse width (W_WIDTH)
16 - nxp,whold: Write hold time (W_HOLD)
17 - nxp,wsetup: Write setup time (W_SETUP)
[all …]
Dmtk-nand.txt1 MTK SoCs NAND FLASH controller (NFC) DT binding
3 This file documents the device tree bindings for MTK SoCs NAND controllers.
5 the nand controller interface driver and the ECC engine driver.
10 1) NFC NAND Controller Interface (NFI):
13 The first part of NFC is NAND Controller Interface (NFI) HW.
15 - compatible: Should be one of
16 "mediatek,mt2701-nfc",
17 "mediatek,mt2712-nfc",
18 "mediatek,mt7622-nfc".
19 - reg: Base physical address and size of NFI.
[all …]
Dmarvell-nand.txt1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
[all …]
Dnand-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
[all …]
Damlogic,meson-nand.txt1 Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
4 the MTD NAND bindings.
7 - compatible : contains one of:
8 - "amlogic,meson-gxl-nfc"
9 - "amlogic,meson-axg-nfc"
10 - clocks :
11 A list of phandle + clock-specifier pairs for the clocks listed
12 in clock-names.
14 - clock-names: Should contain the following:
15 "core" - NFC module gate clock
[all …]
Dmxc-nand.txt4 - compatible: "fsl,imxXX-nand"
5 - reg: address range of the nfc block
6 - interrupts: irq to be used
7 - nand-bus-width: see nand-controller.yaml
8 - nand-ecc-mode: see nand-controller.yaml
9 - nand-on-flash-bbt: see nand-controller.yaml
13 nand@d8000000 {
14 compatible = "fsl,imx27-nand";
17 nand-bus-width = <8>;
18 nand-ecc-mode = "hw";
/Linux-v5.4/drivers/mtd/nand/raw/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "NAND ECC Smart Media byte order"
7 depends on MTD_NAND_ECC_SW_HAMMING
14 tristate "Raw/Parallel NAND Device Support"
15 depends on MTD
20 NAND flash devices. For further information see
21 <http://www.linux-mtd.infradead.org/doc/nand.html>.
32 ECC codes. They are used with NAND devices requiring more than 1 bit
35 comment "Raw/parallel NAND flash controllers"
41 tristate "Denali NAND controller on Intel Moorestown"
[all …]
Dnand_bbt.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Bad block table support for the NAND driver
11 * depending on the options in the BBT descriptor(s). If no flash based BBT
13 * marked good / bad blocks. This information is used to create a memory BBT.
15 * on the device.
16 * If a flash based BBT is specified then the function first tries to find the
17 * BBT on flash. If a BBT is found then the contents are read and the memory
18 * based BBT is created. If a mirrored BBT is selected then the mirror is
20 * version number, then the mirror BBT is used to build the memory based BBT.
23 * If no BBT exists at all then the device is scanned for factory marked
[all …]
/Linux-v5.4/include/linux/mtd/
Dbbm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * NAND family Bad Block Management (BBM) header file
4 * - Bad Block Table (BBT) implementation
9 * Copyright © 2000-2005
15 /* The maximum number of NAND chips in an array */
19 * struct nand_bbt_descr - bad block table descriptor
21 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
22 * when bbt is searched, then we store the found bbts pages here.
25 * @veroffs: offset of the bbt version counter in the oob are of the page
26 * @version: version read from the bbt page during scan
[all …]
/Linux-v5.4/drivers/mtd/nand/
Dbbt.c1 // SPDX-License-Identifier: GPL-2.0
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
10 #define pr_fmt(fmt) "nand-bbt: " fmt
12 #include <linux/mtd/nand.h>
16 * nanddev_bbt_init() - Initialize the BBT (Bad Block Table)
17 * @nand: NAND device
19 * Initialize the in-memory BBT.
23 int nanddev_bbt_init(struct nand_device *nand) in nanddev_bbt_init() argument
26 unsigned int nblocks = nanddev_neraseblocks(nand); in nanddev_bbt_init()
30 nand->bbt.cache = kcalloc(nwords, sizeof(*nand->bbt.cache), in nanddev_bbt_init()
[all …]
/Linux-v5.4/arch/arm/boot/dts/
Dat91-kizboxmini.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board
7 /dts-v1/;
9 #include <dt-bindings/pwm/pwm.h>
17 stdout-path = &dbgu;
26 clock-frequency = <32768>;
30 clock-frequency = <12000000>;
35 nand0: nand@40000000 {
36 nand-bus-width = <8>;
37 nand-ecc-mode = "hw";
[all …]
Dbcm7445-bcm97445svmb.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
17 &nand {
23 nand-ecc-step-size = <512>;
24 nand-ecc-strength = <8>;
25 nand-on-flash-bbt;
27 #size-cells = <2>;
28 #address-cells = <2>;
Dsama5d3xcm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
14 stdout-path = "serial0:115200n8";
23 clock-frequency = <32768>;
27 clock-frequency = <12000000>;
34 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
39 compatible = "atmel,tcb-timer";
44 compatible = "atmel,tcb-timer";
51 pinctrl-0 = <&pinctrl_ebi_addr &pinctrl_ebi_cs0>;
52 pinctr-name = "default";
[all …]
/Linux-v5.4/Documentation/driver-api/
Dmtdnand.rst2 MTD NAND Driver Programming Interface
10 The generic NAND driver supports almost all NAND and AG-AND based chips
15 board drivers or filesystem drivers suitable for NAND devices.
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
45 These functions are exported and provide the interface to the NAND
48 - [GENERIC]
53 - [DEFAULT]
58 via pointers in the NAND chip description structure. The board driver
[all …]
/Linux-v5.4/arch/mips/boot/dts/brcm/
Dbcm97xxx-nand-cs1-bch24.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 &nand {
6 nand-on-flash-bbt;
8 nand-ecc-strength = <24>;
9 nand-ecc-step-size = <1024>;
10 brcm,nand-oob-sector-size = <27>;
13 compatible = "fixed-partitions";
14 #address-cells = <1>;
15 #size-cells = <1>;
Dbcm97xxx-nand-cs1-bch4.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 &nand {
6 nand-on-flash-bbt;
8 nand-ecc-strength = <4>;
9 nand-ecc-step-size = <512>;
10 brcm,nand-oob-sector-size = <16>;
13 compatible = "fixed-partitions";
14 #address-cells = <1>;
15 #size-cells = <1>;

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