Lines Matching +full:nand +full:- +full:on +full:- +full:flash +full:- +full:bbt
1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
20 - #size-cells: should be set to 1.
21 - atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
23 - atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
27 - ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
30 * NAND device/chip bindings:
33 - reg: describes the CS lines assigned to the NAND device. If the NAND device
34 exposes multiple CS lines (multi-dies chips), your reg property will
36 1st entry: the CS line this NAND chip is connected to
42 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
43 - cs-gpios: the GPIO(s) used to control the CS line.
44 - det-gpios: the GPIO used to detect if a Smartmedia Card is present.
45 - atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
46 on sama5 SoCs.
49 Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to the NAND
50 device node, and NAND partitions should be defined under the NAND node as
56 - compatible: should be one of the following
57 "atmel,at91sam9g45-pmecc"
58 "atmel,sama5d4-pmecc"
59 "atmel,sama5d2-pmecc"
60 - reg: should contain 2 register ranges. The first one is pointing to the PMECC
65 SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page
69 - compatible: should be "atmel,sama5d3-nfc-io", "syscon".
70 - reg: should contain the I/O range used to interact with the NFC logic.
74 nfc_io: nfc-io@70000000 {
75 compatible = "atmel,sama5d3-nfc-io", "syscon";
79 pmecc: ecc-engine@ffffc070 {
80 compatible = "atmel,at91sam9g45-pmecc";
86 compatible = "atmel,sama5d3-ebi";
87 #address-cells = <2>;
88 #size-cells = <1>;
98 nand_controller: nand-controller {
99 compatible = "atmel,sama5d3-nand-controller";
100 atmel,nfc-sram = <&nfc_sram>;
101 atmel,nfc-io = <&nfc_io>;
102 ecc-engine = <&pmecc>;
103 #address-cells = <2>;
104 #size-cells = <1>;
107 nand@3 {
112 * Put generic NAND/MTD properties and
119 -----------------------------------------------------------------------
124 - compatible: The possible values are:
125 "atmel,at91rm9200-nand"
126 "atmel,sama5d2-nand"
127 "atmel,sama5d4-nand"
128 - reg : should specify localbus address and size used for the chip,
134 - atmel,nand-addr-offset : offset for the address latch.
135 - atmel,nand-cmd-offset : offset for the command latch.
136 - #address-cells, #size-cells : Must be present if the device has sub-nodes
139 - gpios : specifies the gpio pins to control the NAND device. detect is an
143 - atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
144 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
147 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
148 capable of BCH encoding and decoding, on devices where it is present.
149 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
151 is "atmel,sama5d2-nand", 32 is also valid.
152 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
154 - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
157 - nand-bus-width : 8 or 16 bus width if not present 8
158 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
160 Nand Flash Controller(NFC) is an optional sub-node
162 - compatible : "atmel,sama5d3-nfc".
163 - reg : should specify the address and size used for NFC command registers,
166 - clocks: phandle to the peripheral clock
168 - atmel,write-by-sram: boolean to enable NFC write by SRAM.
171 nand0: nand@40000000,0 {
172 compatible = "atmel,at91rm9200-nand";
173 #address-cells = <1>;
174 #size-cells = <1>;
178 atmel,nand-addr-offset = <21>; /* ale */
179 atmel,nand-cmd-offset = <22>; /* cle */
180 nand-on-flash-bbt;
181 nand-ecc-mode = "soft";
192 nand0: nand@40000000 {
193 compatible = "atmel,at91rm9200-nand";
194 #address-cells = <1>;
195 #size-cells = <1>;
201 atmel,nand-addr-offset = <21>; /* ale */
202 atmel,nand-cmd-offset = <22>; /* cle */
203 nand-on-flash-bbt;
204 nand-ecc-mode = "hw";
205 atmel,has-pmecc; /* enable PMECC */
206 atmel,pmecc-cap = <2>;
207 atmel,pmecc-sector-size = <512>;
208 atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
219 nand0: nand@40000000 {
220 compatible = "atmel,at91rm9200-nand";
221 #address-cells = <1>;
222 #size-cells = <1>;
226 compatible = "atmel,sama5d3-nfc";
227 #address-cells = <1>;
228 #size-cells = <1>;