Lines Matching +full:nand +full:- +full:on +full:- +full:flash +full:- +full:bbt
1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
5 registers and for its data input/output buffer. On some SoCs, this controller is
6 paired with a custom DMA engine (inventively named "Flash DMA") which supports
10 available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
17 added on top of the base core controller.
19 the core NAND controller, of the following form:
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v4.0
24 brcm,brcmnand-v5.0
25 brcm,brcmnand-v6.0
26 brcm,brcmnand-v6.1
27 brcm,brcmnand-v6.2
28 brcm,brcmnand-v7.0
29 brcm,brcmnand-v7.1
30 brcm,brcmnand-v7.2
31 brcm,brcmnand-v7.3
33 - reg : the register start and length for NAND register region.
34 (optional) Flash DMA register range (if present)
35 (optional) NAND flash cache range (if at non-standard offset)
36 - reg-names : a list of the names corresponding to the previous register
37 ranges. Should contain "nand" and (optionally)
38 "flash-dma" and/or "nand-cache".
39 - interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available)
41 - interrupt-names : May be "nand_ctlrdy" or "flash_dma_done", if broken out as
43 May be "nand", if the SoC has the individual NAND
46 - #address-cells : <1> - subnodes give the chip-select number
47 - #size-cells : <0>
50 - clock : reference to the clock for the NAND controller
51 - clock-names : "nand" (required for the above clock)
52 - brcm,nand-has-wp : Some versions of this IP include a write-protect
53 (WP) control bit. It is always available on >=
57 -- Additional SoC-specific NAND controller properties --
59 The NAND controller is integrated differently on the variety of SoCs on which it
61 with which to control the 8 exposed NAND interrupts, as well as hardware for
62 configuring the endianness of the data bus. On some SoCs, these features are
64 normal IRQ chip), but on others, they are controlled in unique and interesting
65 ways, sometimes with registers that lump multiple NAND-related functions
68 we define additional 'compatible' properties and associated register resources within the NAND cont…
70 - compatible: Can be one of several SoC-specific strings. Each SoC may have
74 * "brcm,nand-bcm63138"
75 - reg: (required) the 'NAND_INT_BASE' register range, with separate status
77 - reg-names: (required) "nand-int-base"
79 * "brcm,nand-bcm6368"
80 - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
81 - reg: (required) the 'NAND_INTR_BASE' register range, with combined status
83 - reg-names: (required) "nand-int-base"
85 * "brcm,nand-iproc"
86 - reg: (required) the "IDM" register range, for interrupt enable and APB
89 - reg-names: (required) a list of the names corresponding to the previous
90 register ranges. Should contain "iproc-idm" and "iproc-ext".
93 * NAND chip-select
96 to represent enabled chip-selects which (may) contain NAND flash chips. Their
100 - compatible : should contain "brcm,nandcs"
101 - reg : a single integer representing the chip-select
103 - #address-cells : see partition.txt
104 - #size-cells : see partition.txt
107 - nand-ecc-strength : see nand-controller.yaml
108 - nand-ecc-step-size : must be 512 or 1024. See nand-controller.yaml
109 - nand-on-flash-bbt : boolean, to enable the on-flash BBT for this
110 chip-select. See nand-controller.yaml
111 - brcm,nand-oob-sector-size : integer, to denote the spare area sector size
113 addition to the strength and step-size,
115 out the parity bytes it stores on the flash.
117 the flash geometry (particularly the NAND page
119 from NAND, the boot controller has only a limited
123 Each nandcs device node may optionally contain sub-nodes describing the flash
129 nand@f0442800 {
130 compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
133 reg-names = "nand", "flash-dma";
134 interrupt-parent = <&hif_intr2_intc>;
137 #address-cells = <1>;
138 #size-cells = <0>;
143 nand-on-flash-bbt;
144 nand-ecc-strength = <12>;
145 nand-ecc-step-size = <512>;
148 #address-cells = <1>; // <2>, for 64-bit offset
149 #size-cells = <1>; // <2>, for 64-bit length
162 nand@10000200 {
163 compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
164 "brcm,brcmnand-v4.0", "brcm,brcmnand";
168 reg-names = "nand", "nand-cache", "nand-int-base";
169 interrupt-parent = <&periph_intc>;
172 clock-names = "nand";
174 #address-cells = <1>;
175 #size-cells = <0>;
180 nand-on-flash-bbt;
181 nand-ecc-strength = <1>;
182 nand-ecc-step-size = <512>;