Home
last modified time | relevance | path

Searched +full:nand +full:- +full:ecc +full:- +full:algo (Results 1 – 25 of 41) sorted by relevance

12

/Linux-v5.4/Documentation/devicetree/bindings/mtd/
Dnand-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
[all …]
Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
[all …]
Dallwinner,sun4i-a10-nand.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 NAND Controller Device Tree Bindings
10 - $ref: "nand-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <maxime.ripard@bootlin.com>
17 "#address-cells": true
18 "#size-cells": true
[all …]
Doxnas-nand.txt1 * Oxford Semiconductor OXNAS NAND Controller
3 Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.
6 - compatible: "oxsemi,ox820-nand"
7 - reg: Base address and length for NAND mapped memory.
10 - clocks: phandle to the NAND gate clock if needed.
11 - resets: phandle to the NAND reset control if needed.
15 nandc: nand-controller@41000000 {
16 compatible = "oxsemi,ox820-nand";
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
Dmarvell-nand.txt1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
[all …]
Dmxic-nand.txt1 Macronix Raw NAND Controller Device Tree Bindings
2 -------------------------------------------------
5 - compatible: should be "mxic,multi-itfc-v009-nand-controller"
6 - reg: should contain 1 entry for the registers
7 - #address-cells: should be set to 1
8 - #size-cells: should be set to 0
9 - interrupts: interrupt line connected to this raw NAND controller
10 - clock-names: should contain "ps", "send" and "send_dly"
11 - clocks: should contain 3 phandles for the "ps", "send" and
15 - children nodes represent the available NAND chips.
[all …]
/Linux-v5.4/drivers/mtd/nand/raw/
Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
31 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
37 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
38 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
153 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
182 struct mtd_oob_region ecc; member
204 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
208 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
[all …]
Ddavinci_nand.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
8 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
24 #include <linux/platform_data/mtd-davinci.h>
25 #include <linux/platform_data/mtd-davinci-aemif.h>
28 * This is a device driver for the NAND flash controller found on the
33 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
34 * available on chips like the DM355 and OMAP-L137 and needed with the
35 * more error-prone MLC NAND chips.
37 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
[all …]
Dsocrates_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
31 * socrates_nand_write_buf - write buffer to chip
32 * @this: NAND chip object
43 out_be32(host->io_base, FPGA_NAND_ENABLE | in socrates_nand_write_buf()
50 * socrates_nand_read_buf - read chip data into buffer
51 * @this: NAND chip object
64 out_be32(host->io_base, val); in socrates_nand_read_buf()
66 buf[i] = (in_be32(host->io_base) >> in socrates_nand_read_buf()
72 * socrates_nand_read_byte - read one byte from the chip
83 * Hardware specific access to control-lines
[all …]
Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
28 * +-------------------------------------------------------------+
29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
[all …]
Dplat_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic NAND driver
22 * Probe for the NAND device.
26 struct platform_nand_data *pdata = dev_get_platdata(&pdev->dev); in plat_nand_probe()
34 dev_err(&pdev->dev, "platform_nand_data is missing\n"); in plat_nand_probe()
35 return -EINVAL; in plat_nand_probe()
38 if (pdata->chip.nr_chips < 1) { in plat_nand_probe()
39 dev_err(&pdev->dev, "invalid number of chips specified\n"); in plat_nand_probe()
40 return -EINVAL; in plat_nand_probe()
44 data = devm_kzalloc(&pdev->dev, sizeof(struct plat_nand_data), in plat_nand_probe()
[all …]
Ds3c2410.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright © 2004-2008 Simtec Electronics
7 * Samsung S3C2410/S3C2440/S3C2412 NAND driver
10 #define pr_fmt(fmt) "nand-s3c2410: " fmt
36 #include <linux/platform_data/mtd-nand-s3c2410.h>
73 /* new oob placement block for use with hardware ecc generation
79 return -ERANGE; in s3c2410_ooblayout_ecc()
81 oobregion->offset = 0; in s3c2410_ooblayout_ecc()
82 oobregion->length = 3; in s3c2410_ooblayout_ecc()
91 return -ERANGE; in s3c2410_ooblayout_free()
[all …]
Dcmx270_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Derived from drivers/mtd/nand/h1910.c (removed in v3.10)
11 * This is a device driver for the NAND flash device found on the
12 * CM-X270 board.
23 #include <asm/mach-types.h>
25 #include <mach/pxa2xx-regs.h>
30 /* MTD structure for CM-X270 board */
41 .name = "cmx270-0",
50 return (readl(this->legacy.IO_ADDR_R) >> 16); in cmx270_read_byte()
59 writel((*buf++ << 16), this->legacy.IO_ADDR_W); in cmx270_write_buf()
[all …]
Dpasemi_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
8 * Driver for the PWRficient onchip NAND flash interface
32 static const char driver_name[] = "pasemi-nand";
37 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); in pasemi_read_buf()
39 len -= 0x800; in pasemi_read_buf()
41 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, len); in pasemi_read_buf()
48 memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); in pasemi_write_buf()
50 len -= 0x800; in pasemi_write_buf()
52 memcpy_toio(chip->legacy.IO_ADDR_R, buf, len); in pasemi_write_buf()
[all …]
Dxway_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
14 /* nand registers */
18 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */
19 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */
24 * nand commands
25 * The pins of the NAND chip are selected based on the address bits of the
41 /* we need to tel the ebu which addr we mapped the nand to */
45 /* we need to tell the EBU that we have nand attached and set it up properly */
75 return readb(data->nandaddr + op); in xway_readb()
[all …]
Dnand_base.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * This is the generic MTD driver for NAND flash devices. It should be
5 * capable of working with almost all NAND chips currently available.
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
22 * if we have HW ECC support.
53 struct nand_ecc_ctrl *ecc = &chip->ecc; in nand_ooblayout_ecc_sp() local
56 return -ERANGE; in nand_ooblayout_ecc_sp()
59 oobregion->offset = 0; in nand_ooblayout_ecc_sp()
[all …]
Dnand_micron.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
15 * corrected by on-die ECC and should be rewritten.
20 * On chips with 8-bit ECC and additional bit can be used to distinguish
24 * ----- ----- ----- -----------
27 * 0 1 0 4 - 6 errors corrected, recommend rewrite
29 * 1 0 0 1 - 3 errors corrected
31 * 1 1 0 7 - 8 errors corrected, recommend rewrite
66 struct micron_on_die_ecc ecc; member
77 * Configure chip properties from Micron vendor-specific ONFI table
[all …]
Dfsmc_nand.c1 // SPDX-License-Identifier: GPL-2.0
5 * Driver for NAND portions
11 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
19 #include <linux/dma-direction.h>
20 #include <linux/dma-mapping.h>
36 #include <mtd/mtd-abi.h>
60 /* fsmc controller registers for NAND flash */
111 * struct fsmc_nand_data - structure for FSMC NAND device state
115 * @nand: Chip related info for a NAND flash.
123 * @write_dma_chan: DMA channel for write access to NAND
[all …]
Dstm32_fmc2_nand.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
22 /* ECC step size */
31 /* Max requests done for a 8k nand page size */
37 /* Max ECC buffer length */
243 struct stm32_fmc2_nand nand; member
278 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); in stm32_fmc2_timings_init()
279 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); in stm32_fmc2_timings_init() local
280 struct stm32_fmc2_timings *timings = &nand->timings; in stm32_fmc2_timings_init()
281 u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR); in stm32_fmc2_timings_init()
[all …]
/Linux-v5.4/arch/arm/boot/dts/
Dbcm5301x-nand-cs0-bch8.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom BCM470X / BCM5301X Nand chip defaults.
5 * This should be included if the NAND controller is on chip select 0
6 * and uses 8 bit ECC.
8 * Copyright (C) 2015 Hauke Mehrtens <hauke@hauke-m.de>
11 #include "bcm5301x-nand-cs0.dtsi"
14 nand-ecc-algo = "bch";
15 nand-ecc-strength = <8>;
16 nand-ecc-step-size = <512>;
Dbcm5301x-nand-cs0-bch1.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom Northstar NAND.
8 #include "bcm5301x-nand-cs0.dtsi"
11 nand-ecc-algo = "bch";
12 nand-ecc-strength = <1>;
13 nand-ecc-step-size = <512>;
Dbcm5301x-nand-cs0-bch4.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include "bcm5301x-nand-cs0.dtsi"
9 nand-ecc-algo = "bch";
10 nand-ecc-strength = <4>;
11 nand-ecc-step-size = <512>;
Dox820-cloudengines-pogoplug-series-3.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3
8 /dts-v1/;
18 stdout-path = "serial0:115200n8";
33 compatible = "gpio-leds";
38 default-state = "keep";
44 default-state = "keep";
50 default-state = "keep";
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_uart0>;
[all …]
/Linux-v5.4/include/linux/mtd/
Drawnand.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8 * Contains standard defines and IDs for NAND flash devices
20 #include <linux/mtd/nand.h>
28 /* The maximum number of NAND chips in an array */
49 * Standard NAND flash commands
72 #define NAND_CMD_NONE -1
81 #define NAND_DATA_IFACE_CHECK_ONLY -1
103 * Constants for Hardware ECC
105 /* Reset Hardware ECC for read */
[all …]
/Linux-v5.4/drivers/mtd/nand/raw/brcmnand/
Dbrcmnand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
17 #include <linux/dma-mapping.h>
88 #define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */
93 /* 512B flash cache in the NAND controller HW */
179 /* List of NAND hosts (one for each chip-select) */
187 /* in-memory cache of the FLASH_CACHE, used only for some commands */
193 const u8 *cs_offsets; /* within each chip-select */
202 /* for low-power standby/resume only */
221 /* use for low-power standby/resume only */
[all …]

12