Lines Matching +full:nand +full:- +full:ecc +full:- +full:algo
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
17 #include <linux/dma-mapping.h>
88 #define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */
93 /* 512B flash cache in the NAND controller HW */
179 /* List of NAND hosts (one for each chip-select) */
187 /* in-memory cache of the FLASH_CACHE, used only for some commands */
193 const u8 *cs_offsets; /* within each chip-select */
202 /* for low-power standby/resume only */
221 /* use for low-power standby/resume only */
252 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
266 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
268 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
332 /* BRCMNAND v6.0 - v7.1 */
430 /* Per chip-select offsets for v7.1 */
439 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
448 /* Per chip-select offset for <= v5.0 on CS0 only */
458 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
470 /* Only for pre-v7.1 (with no CFG_EXT register) */
492 return brcmnand_readl(ctrl->nand_base + offs); in nand_readreg()
498 brcmnand_writel(val, ctrl->nand_base + offs); in nand_writereg()
507 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; in brcmnand_revision_init()
510 if (ctrl->nand_version < 0x0400) { in brcmnand_revision_init()
511 dev_err(ctrl->dev, "version %#x not supported\n", in brcmnand_revision_init()
512 ctrl->nand_version); in brcmnand_revision_init()
513 return -ENODEV; in brcmnand_revision_init()
517 if (ctrl->nand_version >= 0x0702) in brcmnand_revision_init()
518 ctrl->reg_offsets = brcmnand_regs_v72; in brcmnand_revision_init()
519 else if (ctrl->nand_version == 0x0701) in brcmnand_revision_init()
520 ctrl->reg_offsets = brcmnand_regs_v71; in brcmnand_revision_init()
521 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
522 ctrl->reg_offsets = brcmnand_regs_v60; in brcmnand_revision_init()
523 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
524 ctrl->reg_offsets = brcmnand_regs_v50; in brcmnand_revision_init()
525 else if (ctrl->nand_version >= 0x0400) in brcmnand_revision_init()
526 ctrl->reg_offsets = brcmnand_regs_v40; in brcmnand_revision_init()
528 /* Chip-select stride */ in brcmnand_revision_init()
529 if (ctrl->nand_version >= 0x0701) in brcmnand_revision_init()
530 ctrl->reg_spacing = 0x14; in brcmnand_revision_init()
532 ctrl->reg_spacing = 0x10; in brcmnand_revision_init()
534 /* Per chip-select registers */ in brcmnand_revision_init()
535 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
536 ctrl->cs_offsets = brcmnand_cs_offsets_v71; in brcmnand_revision_init()
538 ctrl->cs_offsets = brcmnand_cs_offsets; in brcmnand_revision_init()
541 if (ctrl->nand_version <= 0x0500) in brcmnand_revision_init()
542 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; in brcmnand_revision_init()
546 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
547 /* >= v7.1 use nice power-of-2 values! */ in brcmnand_revision_init()
548 ctrl->max_page_size = 16 * 1024; in brcmnand_revision_init()
549 ctrl->max_block_size = 2 * 1024 * 1024; in brcmnand_revision_init()
551 ctrl->page_sizes = page_sizes; in brcmnand_revision_init()
552 if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
553 ctrl->block_sizes = block_sizes_v6; in brcmnand_revision_init()
555 ctrl->block_sizes = block_sizes_v4; in brcmnand_revision_init()
557 if (ctrl->nand_version < 0x0400) { in brcmnand_revision_init()
558 ctrl->max_page_size = 4096; in brcmnand_revision_init()
559 ctrl->max_block_size = 512 * 1024; in brcmnand_revision_init()
564 if (ctrl->nand_version == 0x0702) in brcmnand_revision_init()
565 ctrl->max_oob = 128; in brcmnand_revision_init()
566 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
567 ctrl->max_oob = 64; in brcmnand_revision_init()
568 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
569 ctrl->max_oob = 32; in brcmnand_revision_init()
571 ctrl->max_oob = 16; in brcmnand_revision_init()
574 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) in brcmnand_revision_init()
575 ctrl->features |= BRCMNAND_HAS_PREFETCH; in brcmnand_revision_init()
581 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
582 ctrl->features |= BRCMNAND_HAS_CACHE_MODE; in brcmnand_revision_init()
584 if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
585 ctrl->features |= BRCMNAND_HAS_1K_SECTORS; in brcmnand_revision_init()
587 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
588 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
589 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) in brcmnand_revision_init()
590 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
598 if (ctrl->nand_version >= 0x0703) in brcmnand_flash_dma_revision_init()
599 ctrl->flash_dma_offsets = flash_dma_regs_v4; in brcmnand_flash_dma_revision_init()
601 ctrl->flash_dma_offsets = flash_dma_regs_v1; in brcmnand_flash_dma_revision_init()
607 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_read_reg()
618 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_write_reg()
637 return __raw_readl(ctrl->nand_fc + word * 4); in brcmnand_read_fc()
643 __raw_writel(val, ctrl->nand_fc + word * 4); in brcmnand_write_fc()
684 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cmd_addr()
687 (host->cs << 16) | ((addr >> 32) & 0xffff)); in brcmnand_set_cmd_addr()
697 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; in brcmnand_cs_offset()
698 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; in brcmnand_cs_offset()
701 if (cs == 0 && ctrl->cs0_offsets) in brcmnand_cs_offset()
702 cs_offs = ctrl->cs0_offsets[reg]; in brcmnand_cs_offset()
704 cs_offs = ctrl->cs_offsets[reg]; in brcmnand_cs_offset()
707 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
709 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
714 if (ctrl->nand_version < 0x0600) in brcmnand_count_corrected()
721 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wr_corr_thresh()
724 int cs = host->cs; in brcmnand_wr_corr_thresh()
726 if (ctrl->nand_version == 0x0702) in brcmnand_wr_corr_thresh()
728 else if (ctrl->nand_version >= 0x0600) in brcmnand_wr_corr_thresh()
730 else if (ctrl->nand_version >= 0x0500) in brcmnand_wr_corr_thresh()
735 if (ctrl->nand_version >= 0x0702) { in brcmnand_wr_corr_thresh()
739 } else if (ctrl->nand_version >= 0x0600) { in brcmnand_wr_corr_thresh()
744 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); in brcmnand_wr_corr_thresh()
749 if (ctrl->nand_version < 0x0602) in brcmnand_cmd_shift()
755 * NAND ACC CONTROL bitfield
780 if (ctrl->nand_version == 0x0702) in brcmnand_spare_area_mask()
782 else if (ctrl->nand_version >= 0x0600) in brcmnand_spare_area_mask()
793 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; in brcmnand_ecc_level_mask()
797 /* v7.2 includes additional ECC levels */ in brcmnand_ecc_level_mask()
798 if (ctrl->nand_version >= 0x0702) in brcmnand_ecc_level_mask()
806 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_ecc_enabled()
807 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_set_ecc_enabled()
812 acc_control |= ecc_flags; /* enable RD/WR ECC */ in brcmnand_set_ecc_enabled()
813 acc_control |= host->hwcfg.ecc_level in brcmnand_set_ecc_enabled()
816 acc_control &= ~ecc_flags; /* disable RD/WR ECC */ in brcmnand_set_ecc_enabled()
825 if (ctrl->nand_version >= 0x0702) in brcmnand_sector_1k_shift()
827 else if (ctrl->nand_version >= 0x0600) in brcmnand_sector_1k_shift()
829 else if (ctrl->nand_version >= 0x0500) in brcmnand_sector_1k_shift()
832 return -1; in brcmnand_sector_1k_shift()
837 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_get_sector_size_1k()
839 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_get_sector_size_1k()
850 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_sector_size_1k()
852 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_sector_size_1k()
893 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", in bcmnand_ctrl_poll_status()
896 return -ETIMEDOUT; in bcmnand_ctrl_poll_status()
912 return ctrl->flash_dma_base; in has_flash_dma()
917 if (ctrl->pio_poll_mode) in disable_ctrl_irqs()
921 ctrl->flash_dma_base = 0; in disable_ctrl_irqs()
922 disable_irq(ctrl->dma_irq); in disable_ctrl_irqs()
925 disable_irq(ctrl->irq); in disable_ctrl_irqs()
926 ctrl->pio_poll_mode = true; in disable_ctrl_irqs()
938 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_writel()
940 brcmnand_writel(val, ctrl->flash_dma_base + offs); in flash_dma_writel()
946 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_readl()
948 return brcmnand_readl(ctrl->flash_dma_base + offs); in flash_dma_readl()
951 /* Low-level operation types: command, address, write, or read */
966 if (ctrl->nand_version <= 0x0701) in is_hamming_ecc()
967 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 && in is_hamming_ecc()
968 cfg->ecc_level == 15; in is_hamming_ecc()
970 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 && in is_hamming_ecc()
971 cfg->ecc_level == 15) || in is_hamming_ecc()
972 (cfg->spare_area_size == 28 && cfg->ecc_level == 16)); in is_hamming_ecc()
976 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
978 * Returns -ERRCODE on failure.
985 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_hamming_ooblayout_ecc()
986 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_hamming_ooblayout_ecc()
987 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_hamming_ooblayout_ecc()
990 return -ERANGE; in brcmnand_hamming_ooblayout_ecc()
992 oobregion->offset = (section * sas) + 6; in brcmnand_hamming_ooblayout_ecc()
993 oobregion->length = 3; in brcmnand_hamming_ooblayout_ecc()
1003 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_hamming_ooblayout_free()
1004 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_hamming_ooblayout_free()
1005 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_hamming_ooblayout_free()
1008 return -ERANGE; in brcmnand_hamming_ooblayout_free()
1010 oobregion->offset = (section / 2) * sas; in brcmnand_hamming_ooblayout_free()
1013 oobregion->offset += 9; in brcmnand_hamming_ooblayout_free()
1014 oobregion->length = 7; in brcmnand_hamming_ooblayout_free()
1016 oobregion->length = 6; in brcmnand_hamming_ooblayout_free()
1021 * Small-page NAND use byte 6 for BBI while large-page in brcmnand_hamming_ooblayout_free()
1022 * NAND use byte 0. in brcmnand_hamming_ooblayout_free()
1024 if (cfg->page_size > 512) in brcmnand_hamming_ooblayout_free()
1025 oobregion->offset++; in brcmnand_hamming_ooblayout_free()
1026 oobregion->length--; in brcmnand_hamming_ooblayout_free()
1034 .ecc = brcmnand_hamming_ooblayout_ecc,
1043 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_ecc()
1044 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_ecc()
1045 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_bch_ooblayout_ecc()
1048 return -ERANGE; in brcmnand_bch_ooblayout_ecc()
1050 oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes; in brcmnand_bch_ooblayout_ecc()
1051 oobregion->length = chip->ecc.bytes; in brcmnand_bch_ooblayout_ecc()
1061 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_free_lp()
1062 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_free_lp()
1063 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_bch_ooblayout_free_lp()
1066 return -ERANGE; in brcmnand_bch_ooblayout_free_lp()
1068 if (sas <= chip->ecc.bytes) in brcmnand_bch_ooblayout_free_lp()
1071 oobregion->offset = section * sas; in brcmnand_bch_ooblayout_free_lp()
1072 oobregion->length = sas - chip->ecc.bytes; in brcmnand_bch_ooblayout_free_lp()
1075 oobregion->offset++; in brcmnand_bch_ooblayout_free_lp()
1076 oobregion->length--; in brcmnand_bch_ooblayout_free_lp()
1087 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_free_sp()
1088 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_free_sp()
1090 if (section > 1 || sas - chip->ecc.bytes < 6 || in brcmnand_bch_ooblayout_free_sp()
1091 (section && sas - chip->ecc.bytes == 6)) in brcmnand_bch_ooblayout_free_sp()
1092 return -ERANGE; in brcmnand_bch_ooblayout_free_sp()
1095 oobregion->offset = 0; in brcmnand_bch_ooblayout_free_sp()
1096 oobregion->length = 5; in brcmnand_bch_ooblayout_free_sp()
1098 oobregion->offset = 6; in brcmnand_bch_ooblayout_free_sp()
1099 oobregion->length = sas - chip->ecc.bytes - 6; in brcmnand_bch_ooblayout_free_sp()
1106 .ecc = brcmnand_bch_ooblayout_ecc,
1111 .ecc = brcmnand_bch_ooblayout_ecc,
1117 struct brcmnand_cfg *p = &host->hwcfg; in brcmstb_choose_ecc_layout()
1118 struct mtd_info *mtd = nand_to_mtd(&host->chip); in brcmstb_choose_ecc_layout()
1119 struct nand_ecc_ctrl *ecc = &host->chip.ecc; in brcmstb_choose_ecc_layout() local
1120 unsigned int ecc_level = p->ecc_level; in brcmstb_choose_ecc_layout()
1121 int sas = p->spare_area_size << p->sector_size_1k; in brcmstb_choose_ecc_layout()
1122 int sectors = p->page_size / (512 << p->sector_size_1k); in brcmstb_choose_ecc_layout()
1124 if (p->sector_size_1k) in brcmstb_choose_ecc_layout()
1127 if (is_hamming_ecc(host->ctrl, p)) { in brcmstb_choose_ecc_layout()
1128 ecc->bytes = 3 * sectors; in brcmstb_choose_ecc_layout()
1139 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8); in brcmstb_choose_ecc_layout()
1140 if (p->page_size == 512) in brcmstb_choose_ecc_layout()
1145 if (ecc->bytes >= sas) { in brcmstb_choose_ecc_layout()
1146 dev_err(&host->pdev->dev, in brcmstb_choose_ecc_layout()
1147 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n", in brcmstb_choose_ecc_layout()
1148 ecc->bytes, sas); in brcmstb_choose_ecc_layout()
1149 return -EINVAL; in brcmstb_choose_ecc_layout()
1159 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wp()
1161 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { in brcmnand_wp()
1162 static int old_wp = -1; in brcmnand_wp()
1166 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); in brcmnand_wp()
1193 dev_err_ratelimited(&host->pdev->dev, in brcmnand_wp()
1194 "nand #WP expected %s\n", in brcmnand_wp()
1204 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; in oob_reg_read()
1205 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; in oob_reg_read()
1207 if (offs >= ctrl->max_oob) in oob_reg_read()
1211 reg_offs = offset10 + ((offs - 0x10) & ~0x03); in oob_reg_read()
1215 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); in oob_reg_read()
1223 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; in oob_reg_write()
1224 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; in oob_reg_write()
1226 if (offs >= ctrl->max_oob) in oob_reg_write()
1230 reg_offs = offset10 + ((offs - 0x10) & ~0x03); in oob_reg_write()
1238 * read_oob_from_regs - read data from OOB registers
1239 * @ctrl: NAND controller
1240 * @i: sub-page sector index
1253 tbytes = max(0, tbytes - (int)ctrl->max_oob); in read_oob_from_regs()
1254 tbytes = min_t(int, tbytes, ctrl->max_oob); in read_oob_from_regs()
1262 * write_oob_to_regs - write data to OOB registers
1263 * @i: sub-page sector index
1276 tbytes = max(0, tbytes - (int)ctrl->max_oob); in write_oob_to_regs()
1277 tbytes = min_t(int, tbytes, ctrl->max_oob); in write_oob_to_regs()
1293 if (ctrl->dma_pending) in brcmnand_ctlrdy_irq()
1296 complete(&ctrl->done); in brcmnand_ctlrdy_irq()
1300 /* Handle SoC-specific interrupt hardware */
1305 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) in brcmnand_irq()
1315 complete(&ctrl->dma_done); in brcmnand_dma_irq()
1322 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_send_cmd()
1328 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); in brcmnand_send_cmd()
1330 BUG_ON(ctrl->cmd_pending != 0); in brcmnand_send_cmd()
1331 ctrl->cmd_pending = cmd; in brcmnand_send_cmd()
1342 * NAND MTD API: read/program/erase
1354 struct brcmnand_controller *ctrl = host->ctrl; in brcmstb_nand_wait_for_completion()
1359 if (mtd->oops_panic_write) { in brcmstb_nand_wait_for_completion()
1369 sts = wait_for_completion_timeout(&ctrl->done, timeo); in brcmstb_nand_wait_for_completion()
1379 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_waitfunc()
1382 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); in brcmnand_waitfunc()
1383 if (ctrl->cmd_pending) in brcmnand_waitfunc()
1390 dev_err_ratelimited(ctrl->dev, in brcmnand_waitfunc()
1392 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", in brcmnand_waitfunc()
1395 ctrl->cmd_pending = 0; in brcmnand_waitfunc()
1414 struct nand_chip *chip = &host->chip; in brcmnand_low_level_op()
1415 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_low_level_op()
1440 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); in brcmnand_low_level_op()
1454 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_cmdfunc()
1455 u64 addr = (u64)page_addr << chip->page_shift; in brcmnand_cmdfunc()
1461 /* Avoid propagating a negative, don't-care address */ in brcmnand_cmdfunc()
1465 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command, in brcmnand_cmdfunc()
1468 host->last_cmd = command; in brcmnand_cmdfunc()
1469 host->last_byte = 0; in brcmnand_cmdfunc()
1470 host->last_addr = addr; in brcmnand_cmdfunc()
1499 addr &= ~((u64)(FC_BYTES - 1)); in brcmnand_cmdfunc()
1505 host->hwcfg.sector_size_1k = in brcmnand_cmdfunc()
1521 /* Copy flash cache word-wise */ in brcmnand_cmdfunc()
1522 u32 *flash_cache = (u32 *)ctrl->flash_cache; in brcmnand_cmdfunc()
1525 brcmnand_soc_data_bus_prepare(ctrl->soc, true); in brcmnand_cmdfunc()
1538 brcmnand_soc_data_bus_unprepare(ctrl->soc, true); in brcmnand_cmdfunc()
1541 if (host->hwcfg.sector_size_1k) in brcmnand_cmdfunc()
1543 host->hwcfg.sector_size_1k); in brcmnand_cmdfunc()
1546 /* Re-enable protection is necessary only after erase */ in brcmnand_cmdfunc()
1554 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_byte()
1558 switch (host->last_cmd) { in brcmnand_read_byte()
1560 if (host->last_byte < 4) in brcmnand_read_byte()
1562 (24 - (host->last_byte << 3)); in brcmnand_read_byte()
1563 else if (host->last_byte < 8) in brcmnand_read_byte()
1565 (56 - (host->last_byte << 3)); in brcmnand_read_byte()
1569 ret = oob_reg_read(ctrl, host->last_byte); in brcmnand_read_byte()
1581 addr = host->last_addr + host->last_byte; in brcmnand_read_byte()
1582 offs = addr & (FC_BYTES - 1); in brcmnand_read_byte()
1585 if (host->last_byte > 0 && offs == 0) in brcmnand_read_byte()
1588 ret = ctrl->flash_cache[offs]; in brcmnand_read_byte()
1591 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) { in brcmnand_read_byte()
1594 bool last = host->last_byte == in brcmnand_read_byte()
1595 ONFI_SUBFEATURE_PARAM_LEN - 1; in brcmnand_read_byte()
1601 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret); in brcmnand_read_byte()
1602 host->last_byte++; in brcmnand_read_byte()
1621 switch (host->last_cmd) { in brcmnand_write_buf()
1636 * - Is this descriptor the beginning or end of a linked list?
1637 * - What is the (DMA) address of the next descriptor in the linked list?
1647 desc->next_desc = lower_32_bits(next_desc); in brcmnand_fill_dma_desc()
1648 desc->next_desc_ext = upper_32_bits(next_desc); in brcmnand_fill_dma_desc()
1649 desc->cmd_irq = (dma_cmd << 24) | in brcmnand_fill_dma_desc()
1653 desc->cmd_irq |= 0x01 << 12; in brcmnand_fill_dma_desc()
1655 desc->dram_addr = lower_32_bits(buf); in brcmnand_fill_dma_desc()
1656 desc->dram_addr_ext = upper_32_bits(buf); in brcmnand_fill_dma_desc()
1657 desc->tfr_len = len; in brcmnand_fill_dma_desc()
1658 desc->total_len = len; in brcmnand_fill_dma_desc()
1659 desc->flash_addr = lower_32_bits(addr); in brcmnand_fill_dma_desc()
1660 desc->flash_addr_ext = upper_32_bits(addr); in brcmnand_fill_dma_desc()
1661 desc->cs = host->cs; in brcmnand_fill_dma_desc()
1662 desc->status_valid = 0x01; in brcmnand_fill_dma_desc()
1671 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_run()
1680 ctrl->dma_pending = true; in brcmnand_dma_run()
1684 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { in brcmnand_dma_run()
1685 dev_err(ctrl->dev, in brcmnand_dma_run()
1690 ctrl->dma_pending = false; in brcmnand_dma_run()
1697 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_trans()
1701 buf_pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_dma_trans()
1702 if (dma_mapping_error(ctrl->dev, buf_pa)) { in brcmnand_dma_trans()
1703 dev_err(ctrl->dev, "unable to map buffer for DMA\n"); in brcmnand_dma_trans()
1704 return -ENOMEM; in brcmnand_dma_trans()
1707 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, in brcmnand_dma_trans()
1710 brcmnand_dma_run(host, ctrl->dma_pa); in brcmnand_dma_trans()
1712 dma_unmap_single(ctrl->dev, buf_pa, len, dir); in brcmnand_dma_trans()
1714 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) in brcmnand_dma_trans()
1715 return -EBADMSG; in brcmnand_dma_trans()
1716 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) in brcmnand_dma_trans()
1717 return -EUCLEAN; in brcmnand_dma_trans()
1730 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_by_pio()
1737 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */ in brcmnand_read_by_pio()
1742 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_read_by_pio()
1747 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_read_by_pio()
1752 mtd->oobsize / trans, in brcmnand_read_by_pio()
1753 host->hwcfg.sector_size_1k); in brcmnand_read_by_pio()
1759 ret = -EBADMSG; in brcmnand_read_by_pio()
1766 ret = -EUCLEAN; in brcmnand_read_by_pio()
1774 * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
1777 * Because the HW ECC signals an ECC error if an erase paged has even a single
1778 * bitflip, we must check each ECC error to see if it is actually an erased
1781 * On a real error, return a negative error code (-EBADMSG for ECC error), and
1784 * bitflips-per-ECC-sector to the caller.
1791 void *oob = chip->oob_poi; in brcmstb_nand_verify_erased_page()
1793 int page = addr >> chip->page_shift; in brcmstb_nand_verify_erased_page()
1800 sas = mtd->oobsize / chip->ecc.steps; in brcmstb_nand_verify_erased_page()
1802 /* read without ecc for verification */ in brcmstb_nand_verify_erased_page()
1803 ret = chip->ecc.read_page_raw(chip, buf, true, page); in brcmstb_nand_verify_erased_page()
1807 for (i = 0; i < chip->ecc.steps; i++, oob += sas) { in brcmstb_nand_verify_erased_page()
1808 ecc_chunk = buf + chip->ecc.size * i; in brcmstb_nand_verify_erased_page()
1810 chip->ecc.size, in brcmstb_nand_verify_erased_page()
1812 chip->ecc.strength); in brcmstb_nand_verify_erased_page()
1826 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read()
1831 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); in brcmnand_read()
1843 return -EIO; in brcmnand_read()
1847 memset(oob, 0x99, mtd->oobsize); in brcmnand_read()
1862 if ((ctrl->nand_version == 0x0700) || in brcmnand_read()
1863 (ctrl->nand_version == 0x0701)) { in brcmnand_read()
1874 if (ctrl->nand_version < 0x0702) { in brcmnand_read()
1882 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", in brcmnand_read()
1884 mtd->ecc_stats.failed++; in brcmnand_read()
1885 /* NAND layer expects zero on ECC errors */ in brcmnand_read()
1892 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", in brcmnand_read()
1894 mtd->ecc_stats.corrected += corrected; in brcmnand_read()
1895 /* Always exceed the software-imposed threshold */ in brcmnand_read()
1896 return max(mtd->bitflip_threshold, corrected); in brcmnand_read()
1907 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; in brcmnand_read_page()
1911 return brcmnand_read(mtd, chip, host->last_addr, in brcmnand_read_page()
1912 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); in brcmnand_read_page()
1920 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; in brcmnand_read_page_raw()
1926 ret = brcmnand_read(mtd, chip, host->last_addr, in brcmnand_read_page_raw()
1927 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); in brcmnand_read_page_raw()
1936 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift, in brcmnand_read_oob()
1937 mtd->writesize >> FC_SHIFT, in brcmnand_read_oob()
1938 NULL, (u8 *)chip->oob_poi); in brcmnand_read_oob()
1947 brcmnand_read(mtd, chip, (u64)page << chip->page_shift, in brcmnand_read_oob_raw()
1948 mtd->writesize >> FC_SHIFT, in brcmnand_read_oob_raw()
1949 NULL, (u8 *)chip->oob_poi); in brcmnand_read_oob_raw()
1958 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_write()
1959 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT; in brcmnand_write()
1962 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); in brcmnand_write()
1965 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); in brcmnand_write()
1971 for (i = 0; i < ctrl->max_oob; i += 4) in brcmnand_write()
1976 mtd->writesize, CMD_PROGRAM_PAGE)) in brcmnand_write()
1977 ret = -EIO; in brcmnand_write()
1986 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_write()
1991 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_write()
1999 mtd->oobsize / trans, in brcmnand_write()
2000 host->hwcfg.sector_size_1k); in brcmnand_write()
2008 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_write()
2010 ret = -EIO; in brcmnand_write()
2024 void *oob = oob_required ? chip->oob_poi : NULL; in brcmnand_write_page()
2027 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); in brcmnand_write_page()
2037 void *oob = oob_required ? chip->oob_poi : NULL; in brcmnand_write_page_raw()
2041 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); in brcmnand_write_page_raw()
2050 (u64)page << chip->page_shift, NULL, in brcmnand_write_oob()
2051 chip->oob_poi); in brcmnand_write_oob()
2061 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL, in brcmnand_write_oob_raw()
2062 (u8 *)chip->oob_poi); in brcmnand_write_oob_raw()
2069 * Per-CS setup (1 NAND device)
2075 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cfg()
2076 struct nand_chip *chip = &host->chip; in brcmnand_set_cfg()
2077 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_set_cfg()
2078 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2080 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2085 if (ctrl->block_sizes) { in brcmnand_set_cfg()
2088 for (i = 0, found = 0; ctrl->block_sizes[i]; i++) in brcmnand_set_cfg()
2089 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { in brcmnand_set_cfg()
2094 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2095 cfg->block_size); in brcmnand_set_cfg()
2096 return -EINVAL; in brcmnand_set_cfg()
2099 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE); in brcmnand_set_cfg()
2102 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && in brcmnand_set_cfg()
2103 cfg->block_size > ctrl->max_block_size)) { in brcmnand_set_cfg()
2104 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2105 cfg->block_size); in brcmnand_set_cfg()
2109 if (ctrl->page_sizes) { in brcmnand_set_cfg()
2112 for (i = 0, found = 0; ctrl->page_sizes[i]; i++) in brcmnand_set_cfg()
2113 if (ctrl->page_sizes[i] == cfg->page_size) { in brcmnand_set_cfg()
2118 dev_warn(ctrl->dev, "invalid page size %u\n", in brcmnand_set_cfg()
2119 cfg->page_size); in brcmnand_set_cfg()
2120 return -EINVAL; in brcmnand_set_cfg()
2123 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE); in brcmnand_set_cfg()
2126 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && in brcmnand_set_cfg()
2127 cfg->page_size > ctrl->max_page_size)) { in brcmnand_set_cfg()
2128 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); in brcmnand_set_cfg()
2129 return -EINVAL; in brcmnand_set_cfg()
2132 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) { in brcmnand_set_cfg()
2133 dev_warn(ctrl->dev, "invalid device size 0x%llx\n", in brcmnand_set_cfg()
2134 (unsigned long long)cfg->device_size); in brcmnand_set_cfg()
2135 return -EINVAL; in brcmnand_set_cfg()
2137 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE); in brcmnand_set_cfg()
2139 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2140 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2141 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2142 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) | in brcmnand_set_cfg()
2157 tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; in brcmnand_set_cfg()
2159 tmp |= cfg->spare_area_size; in brcmnand_set_cfg()
2162 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); in brcmnand_set_cfg()
2164 /* threshold = ceil(BCH-level * 0.75) */ in brcmnand_set_cfg()
2165 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4)); in brcmnand_set_cfg()
2174 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit", in brcmnand_print_cfg()
2175 (unsigned long long)cfg->device_size >> 20, in brcmnand_print_cfg()
2176 cfg->block_size >> 10, in brcmnand_print_cfg()
2177 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size, in brcmnand_print_cfg()
2178 cfg->page_size >= 1024 ? "KiB" : "B", in brcmnand_print_cfg()
2179 cfg->spare_area_size, cfg->device_width); in brcmnand_print_cfg()
2181 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */ in brcmnand_print_cfg()
2182 if (is_hamming_ecc(host->ctrl, cfg)) in brcmnand_print_cfg()
2183 sprintf(buf, ", Hamming ECC"); in brcmnand_print_cfg()
2184 else if (cfg->sector_size_1k) in brcmnand_print_cfg()
2185 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1); in brcmnand_print_cfg()
2187 sprintf(buf, ", BCH-%u", cfg->ecc_level); in brcmnand_print_cfg()
2192 * roundup(log2(size / page-size) / 8)
2194 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2199 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3; in get_blk_adr_bytes()
2204 struct mtd_info *mtd = nand_to_mtd(&host->chip); in brcmnand_setup_dev()
2205 struct nand_chip *chip = &host->chip; in brcmnand_setup_dev()
2206 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_setup_dev()
2207 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_setup_dev()
2215 "brcm,nand-oob-sector-size", in brcmnand_setup_dev()
2219 cfg->spare_area_size = mtd->oobsize / in brcmnand_setup_dev()
2220 (mtd->writesize >> FC_SHIFT); in brcmnand_setup_dev()
2222 cfg->spare_area_size = oob_sector; in brcmnand_setup_dev()
2224 if (cfg->spare_area_size > ctrl->max_oob) in brcmnand_setup_dev()
2225 cfg->spare_area_size = ctrl->max_oob; in brcmnand_setup_dev()
2230 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); in brcmnand_setup_dev()
2232 cfg->device_size = mtd->size; in brcmnand_setup_dev()
2233 cfg->block_size = mtd->erasesize; in brcmnand_setup_dev()
2234 cfg->page_size = mtd->writesize; in brcmnand_setup_dev()
2235 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8; in brcmnand_setup_dev()
2236 cfg->col_adr_bytes = 2; in brcmnand_setup_dev()
2237 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize); in brcmnand_setup_dev()
2239 if (chip->ecc.mode != NAND_ECC_HW) { in brcmnand_setup_dev()
2240 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", in brcmnand_setup_dev()
2241 chip->ecc.mode); in brcmnand_setup_dev()
2242 return -EINVAL; in brcmnand_setup_dev()
2245 if (chip->ecc.algo == NAND_ECC_UNKNOWN) { in brcmnand_setup_dev()
2246 if (chip->ecc.strength == 1 && chip->ecc.size == 512) in brcmnand_setup_dev()
2247 /* Default to Hamming for 1-bit ECC, if unspecified */ in brcmnand_setup_dev()
2248 chip->ecc.algo = NAND_ECC_HAMMING; in brcmnand_setup_dev()
2251 chip->ecc.algo = NAND_ECC_BCH; in brcmnand_setup_dev()
2254 if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 || in brcmnand_setup_dev()
2255 chip->ecc.size != 512)) { in brcmnand_setup_dev()
2256 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", in brcmnand_setup_dev()
2257 chip->ecc.strength, chip->ecc.size); in brcmnand_setup_dev()
2258 return -EINVAL; in brcmnand_setup_dev()
2261 if (chip->ecc.mode != NAND_ECC_NONE && in brcmnand_setup_dev()
2262 (!chip->ecc.size || !chip->ecc.strength)) { in brcmnand_setup_dev()
2263 if (chip->base.eccreq.step_size && chip->base.eccreq.strength) { in brcmnand_setup_dev()
2264 /* use detected ECC parameters */ in brcmnand_setup_dev()
2265 chip->ecc.size = chip->base.eccreq.step_size; in brcmnand_setup_dev()
2266 chip->ecc.strength = chip->base.eccreq.strength; in brcmnand_setup_dev()
2267 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", in brcmnand_setup_dev()
2268 chip->ecc.size, chip->ecc.strength); in brcmnand_setup_dev()
2272 switch (chip->ecc.size) { in brcmnand_setup_dev()
2274 if (chip->ecc.algo == NAND_ECC_HAMMING) in brcmnand_setup_dev()
2275 cfg->ecc_level = 15; in brcmnand_setup_dev()
2277 cfg->ecc_level = chip->ecc.strength; in brcmnand_setup_dev()
2278 cfg->sector_size_1k = 0; in brcmnand_setup_dev()
2281 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { in brcmnand_setup_dev()
2282 dev_err(ctrl->dev, "1KB sectors not supported\n"); in brcmnand_setup_dev()
2283 return -EINVAL; in brcmnand_setup_dev()
2285 if (chip->ecc.strength & 0x1) { in brcmnand_setup_dev()
2286 dev_err(ctrl->dev, in brcmnand_setup_dev()
2287 "odd ECC not supported with 1KB sectors\n"); in brcmnand_setup_dev()
2288 return -EINVAL; in brcmnand_setup_dev()
2291 cfg->ecc_level = chip->ecc.strength >> 1; in brcmnand_setup_dev()
2292 cfg->sector_size_1k = 1; in brcmnand_setup_dev()
2295 dev_err(ctrl->dev, "unsupported ECC size: %d\n", in brcmnand_setup_dev()
2296 chip->ecc.size); in brcmnand_setup_dev()
2297 return -EINVAL; in brcmnand_setup_dev()
2300 cfg->ful_adr_bytes = cfg->blk_adr_bytes; in brcmnand_setup_dev()
2301 if (mtd->writesize > 512) in brcmnand_setup_dev()
2302 cfg->ful_adr_bytes += cfg->col_adr_bytes; in brcmnand_setup_dev()
2304 cfg->ful_adr_bytes += 1; in brcmnand_setup_dev()
2313 dev_info(ctrl->dev, "detected %s\n", msg); in brcmnand_setup_dev()
2316 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_setup_dev()
2321 /* We need to turn on Read from erased paged protected by ECC */ in brcmnand_setup_dev()
2322 if (ctrl->nand_version >= 0x0702) in brcmnand_setup_dev()
2325 if (ctrl->features & BRCMNAND_HAS_PREFETCH) in brcmnand_setup_dev()
2339 chip->options |= NAND_NO_SUBPAGE_WRITE; in brcmnand_attach_chip()
2345 chip->options |= NAND_USE_BOUNCE_BUFFER; in brcmnand_attach_chip()
2347 if (chip->bbt_options & NAND_BBT_USE_FLASH) in brcmnand_attach_chip()
2348 chip->bbt_options |= NAND_BBT_NO_OOB; in brcmnand_attach_chip()
2351 return -ENXIO; in brcmnand_attach_chip()
2353 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512; in brcmnand_attach_chip()
2356 mtd->bitflip_threshold = 1; in brcmnand_attach_chip()
2369 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_init_cs()
2370 struct platform_device *pdev = host->pdev; in brcmnand_init_cs()
2376 ret = of_property_read_u32(dn, "reg", &host->cs); in brcmnand_init_cs()
2378 dev_err(&pdev->dev, "can't get chip-select\n"); in brcmnand_init_cs()
2379 return -ENXIO; in brcmnand_init_cs()
2382 mtd = nand_to_mtd(&host->chip); in brcmnand_init_cs()
2383 chip = &host->chip; in brcmnand_init_cs()
2387 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d", in brcmnand_init_cs()
2388 host->cs); in brcmnand_init_cs()
2389 if (!mtd->name) in brcmnand_init_cs()
2390 return -ENOMEM; in brcmnand_init_cs()
2392 mtd->owner = THIS_MODULE; in brcmnand_init_cs()
2393 mtd->dev.parent = &pdev->dev; in brcmnand_init_cs()
2395 chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl; in brcmnand_init_cs()
2396 chip->legacy.cmdfunc = brcmnand_cmdfunc; in brcmnand_init_cs()
2397 chip->legacy.waitfunc = brcmnand_waitfunc; in brcmnand_init_cs()
2398 chip->legacy.read_byte = brcmnand_read_byte; in brcmnand_init_cs()
2399 chip->legacy.read_buf = brcmnand_read_buf; in brcmnand_init_cs()
2400 chip->legacy.write_buf = brcmnand_write_buf; in brcmnand_init_cs()
2402 chip->ecc.mode = NAND_ECC_HW; in brcmnand_init_cs()
2403 chip->ecc.read_page = brcmnand_read_page; in brcmnand_init_cs()
2404 chip->ecc.write_page = brcmnand_write_page; in brcmnand_init_cs()
2405 chip->ecc.read_page_raw = brcmnand_read_page_raw; in brcmnand_init_cs()
2406 chip->ecc.write_page_raw = brcmnand_write_page_raw; in brcmnand_init_cs()
2407 chip->ecc.write_oob_raw = brcmnand_write_oob_raw; in brcmnand_init_cs()
2408 chip->ecc.read_oob_raw = brcmnand_read_oob_raw; in brcmnand_init_cs()
2409 chip->ecc.read_oob = brcmnand_read_oob; in brcmnand_init_cs()
2410 chip->ecc.write_oob = brcmnand_write_oob; in brcmnand_init_cs()
2412 chip->controller = &ctrl->controller; in brcmnand_init_cs()
2416 * NAND READID command only works in 8bit mode. We force in brcmnand_init_cs()
2417 * 8bit mode here to ensure that NAND READID commands works. in brcmnand_init_cs()
2419 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_init_cs()
2437 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_save_restore_cs_config()
2438 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_save_restore_cs_config()
2439 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2441 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2443 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); in brcmnand_save_restore_cs_config()
2444 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); in brcmnand_save_restore_cs_config()
2447 nand_writereg(ctrl, cfg_offs, host->hwcfg.config); in brcmnand_save_restore_cs_config()
2450 host->hwcfg.config_ext); in brcmnand_save_restore_cs_config()
2451 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); in brcmnand_save_restore_cs_config()
2452 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); in brcmnand_save_restore_cs_config()
2453 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); in brcmnand_save_restore_cs_config()
2455 host->hwcfg.config = nand_readreg(ctrl, cfg_offs); in brcmnand_save_restore_cs_config()
2457 host->hwcfg.config_ext = in brcmnand_save_restore_cs_config()
2459 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); in brcmnand_save_restore_cs_config()
2460 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); in brcmnand_save_restore_cs_config()
2461 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); in brcmnand_save_restore_cs_config()
2470 list_for_each_entry(host, &ctrl->host_list, node) in brcmnand_suspend()
2473 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); in brcmnand_suspend()
2474 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); in brcmnand_suspend()
2475 ctrl->corr_stat_threshold = in brcmnand_suspend()
2479 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); in brcmnand_suspend()
2490 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); in brcmnand_resume()
2494 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); in brcmnand_resume()
2495 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); in brcmnand_resume()
2497 ctrl->corr_stat_threshold); in brcmnand_resume()
2498 if (ctrl->soc) { in brcmnand_resume()
2499 /* Clear/re-enable interrupt */ in brcmnand_resume()
2500 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_resume()
2501 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_resume()
2504 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_resume()
2505 struct nand_chip *chip = &host->chip; in brcmnand_resume()
2509 /* Reset the chip, required by some chips after power-up */ in brcmnand_resume()
2523 { .compatible = "brcm,brcmnand-v4.0" },
2524 { .compatible = "brcm,brcmnand-v5.0" },
2525 { .compatible = "brcm,brcmnand-v6.0" },
2526 { .compatible = "brcm,brcmnand-v6.1" },
2527 { .compatible = "brcm,brcmnand-v6.2" },
2528 { .compatible = "brcm,brcmnand-v7.0" },
2529 { .compatible = "brcm,brcmnand-v7.1" },
2530 { .compatible = "brcm,brcmnand-v7.2" },
2531 { .compatible = "brcm,brcmnand-v7.3" },
2542 struct device *dev = &pdev->dev; in brcmnand_probe()
2543 struct device_node *dn = dev->of_node, *child; in brcmnand_probe()
2548 /* We only support device-tree instantiation */ in brcmnand_probe()
2550 return -ENODEV; in brcmnand_probe()
2553 return -ENODEV; in brcmnand_probe()
2557 return -ENOMEM; in brcmnand_probe()
2560 ctrl->dev = dev; in brcmnand_probe()
2562 init_completion(&ctrl->done); in brcmnand_probe()
2563 init_completion(&ctrl->dma_done); in brcmnand_probe()
2564 nand_controller_init(&ctrl->controller); in brcmnand_probe()
2565 ctrl->controller.ops = &brcmnand_controller_ops; in brcmnand_probe()
2566 INIT_LIST_HEAD(&ctrl->host_list); in brcmnand_probe()
2568 /* NAND register range */ in brcmnand_probe()
2570 ctrl->nand_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
2571 if (IS_ERR(ctrl->nand_base)) in brcmnand_probe()
2572 return PTR_ERR(ctrl->nand_base); in brcmnand_probe()
2574 /* Enable clock before using NAND registers */ in brcmnand_probe()
2575 ctrl->clk = devm_clk_get(dev, "nand"); in brcmnand_probe()
2576 if (!IS_ERR(ctrl->clk)) { in brcmnand_probe()
2577 ret = clk_prepare_enable(ctrl->clk); in brcmnand_probe()
2581 ret = PTR_ERR(ctrl->clk); in brcmnand_probe()
2582 if (ret == -EPROBE_DEFER) in brcmnand_probe()
2585 ctrl->clk = NULL; in brcmnand_probe()
2588 /* Initialize NAND revision */ in brcmnand_probe()
2594 * Most chips have this cache at a fixed offset within 'nand' block. in brcmnand_probe()
2597 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache"); in brcmnand_probe()
2599 ctrl->nand_fc = devm_ioremap_resource(dev, res); in brcmnand_probe()
2600 if (IS_ERR(ctrl->nand_fc)) { in brcmnand_probe()
2601 ret = PTR_ERR(ctrl->nand_fc); in brcmnand_probe()
2605 ctrl->nand_fc = ctrl->nand_base + in brcmnand_probe()
2606 ctrl->reg_offsets[BRCMNAND_FC_BASE]; in brcmnand_probe()
2610 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma"); in brcmnand_probe()
2612 ctrl->flash_dma_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
2613 if (IS_ERR(ctrl->flash_dma_base)) { in brcmnand_probe()
2614 ret = PTR_ERR(ctrl->flash_dma_base); in brcmnand_probe()
2621 /* linked-list and stop on error */ in brcmnand_probe()
2626 ctrl->dma_desc = dmam_alloc_coherent(dev, in brcmnand_probe()
2627 sizeof(*ctrl->dma_desc), in brcmnand_probe()
2628 &ctrl->dma_pa, GFP_KERNEL); in brcmnand_probe()
2629 if (!ctrl->dma_desc) { in brcmnand_probe()
2630 ret = -ENOMEM; in brcmnand_probe()
2634 ctrl->dma_irq = platform_get_irq(pdev, 1); in brcmnand_probe()
2635 if ((int)ctrl->dma_irq < 0) { in brcmnand_probe()
2637 ret = -ENODEV; in brcmnand_probe()
2641 ret = devm_request_irq(dev, ctrl->dma_irq, in brcmnand_probe()
2646 ctrl->dma_irq, ret); in brcmnand_probe()
2659 if (ctrl->features & BRCMNAND_HAS_WP) { in brcmnand_probe()
2668 ctrl->irq = platform_get_irq(pdev, 0); in brcmnand_probe()
2669 if ((int)ctrl->irq < 0) { in brcmnand_probe()
2671 ret = -ENODEV; in brcmnand_probe()
2680 ctrl->soc = soc; in brcmnand_probe()
2682 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, in brcmnand_probe()
2686 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_probe()
2687 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_probe()
2690 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, in brcmnand_probe()
2695 ctrl->irq, ret); in brcmnand_probe()
2706 ret = -ENOMEM; in brcmnand_probe()
2709 host->pdev = pdev; in brcmnand_probe()
2710 host->ctrl = ctrl; in brcmnand_probe()
2715 continue; /* Try all chip-selects */ in brcmnand_probe()
2718 list_add_tail(&host->node, &ctrl->host_list); in brcmnand_probe()
2722 /* No chip-selects could initialize properly */ in brcmnand_probe()
2723 if (list_empty(&ctrl->host_list)) { in brcmnand_probe()
2724 ret = -ENODEV; in brcmnand_probe()
2731 clk_disable_unprepare(ctrl->clk); in brcmnand_probe()
2739 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_remove()
2742 list_for_each_entry(host, &ctrl->host_list, node) in brcmnand_remove()
2743 nand_release(&host->chip); in brcmnand_remove()
2745 clk_disable_unprepare(ctrl->clk); in brcmnand_remove()
2747 dev_set_drvdata(&pdev->dev, NULL); in brcmnand_remove()
2756 MODULE_DESCRIPTION("NAND driver for Broadcom chips");