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/Linux-v6.1/arch/mips/boot/dts/ralink/
Dmt7621.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 #include <dt-bindings/interrupt-controller/mips-gic.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/reset/mt7621-reset.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "mediatek,mt7621-soc";
13 #address-cells = <1>;
14 #size-cells = <0>;
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Dmt7628a.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,mt7628a-soc";
9 #address-cells = <1>;
10 #size-cells = <0>;
19 resetc: reset-controller {
20 compatible = "ralink,rt2880-reset";
21 #reset-cells = <1>;
24 cpuintc: interrupt-controller {
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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dmediatek,mt7621-sysc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MT7621 Clock
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 The MT7621 has a PLL controller from where the cpu clock is provided
21 [1]: <include/dt-bindings/clock/mt7621-clk.h>.
28 [2]: <include/dt-bindings/reset/mt7621-reset.h>.
33 - const: mediatek,mt7621-sysc
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/Linux-v6.1/arch/mips/ralink/
Dmt7621.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <asm/smp-ops.h>
19 #include <asm/mips-cps.h>
20 #include <asm/mach-ralink/ralink_regs.h>
21 #include <asm/mach-ralink/mt7621.h>
34 entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); in pcibios_root_bridge_prepare()
37 return -EINVAL; in pcibios_root_bridge_prepare()
45 mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK; in pcibios_root_bridge_prepare()
46 WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask); in pcibios_root_bridge_prepare()
48 write_gcr_reg1_base(entry->res->start); in pcibios_root_bridge_prepare()
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/Linux-v6.1/Documentation/devicetree/bindings/spi/
Dralink,mt7621-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/ralink,mt7621-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
10 title: Mediatek MT7621/MT7628 SPI controller
13 - $ref: /schemas/spi/spi-controller.yaml#
17 const: ralink,mt7621-spi
25 clock-names:
31 reset-names:
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/Linux-v6.1/Documentation/devicetree/bindings/i2c/
Dmediatek,mt7621-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/mediatek,mt7621-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Stefan Roese <sr@denx.de>
10 title: Mediatek MT7621/MT7628 I2C master controller
13 - $ref: /schemas/i2c/i2c-controller.yaml#
17 const: mediatek,mt7621-i2c
25 clock-names:
31 reset-names:
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/Linux-v6.1/drivers/clk/ralink/
Dclk-mt7621.c1 // SPDX-License-Identifier: GPL-2.0
3 * Mediatek MT7621 Clock Driver
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/clock/mt7621-clk.h>
17 #include <dt-bindings/reset/mt7621-reset.h>
36 struct regmap *sysc; member
101 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_enable() local
103 return regmap_update_bits(sysc, SYSC_REG_CLKCFG1, in mt7621_gate_enable()
104 clk_gate->bit_idx, clk_gate->bit_idx); in mt7621_gate_enable()
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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dmediatek,mt7621-pci-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Mediatek Mt7621 PCIe PHY
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
14 const: mediatek,mt7621-pci-phy
22 "#phy-cells":
24 description: selects if the phy is dual-ported
27 - compatible
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/Linux-v6.1/Documentation/devicetree/bindings/net/dsa/
Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
16 There are two versions of MT7530, standalone and in a multi-chip module.
18 MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN,
31 - Port 5 can be used as a CPU port.
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/Linux-v6.1/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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