Lines Matching +full:mt7621 +full:- +full:sysc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MT7621 Clock
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 The MT7621 has a PLL controller from where the cpu clock is provided
21 [1]: <include/dt-bindings/clock/mt7621-clk.h>.
28 [2]: <include/dt-bindings/reset/mt7621-reset.h>.
33 - const: mediatek,mt7621-sysc
34 - const: syscon
39 "#clock-cells":
45 "#reset-cells":
56 clock-output-names:
60 - compatible
61 - reg
62 - '#clock-cells'
63 - ralink,memctl
68 - |
69 #include <dt-bindings/clock/mt7621-clk.h>
71 sysc: sysc@0 {
72 compatible = "mediatek,mt7621-sysc", "syscon";
74 #clock-cells = <1>;
75 #reset-cells = <1>;
77 clock-output-names = "xtal", "cpu", "bus",