Lines Matching +full:mt7621 +full:- +full:sysc
1 // SPDX-License-Identifier: GPL-2.0
3 * Mediatek MT7621 Clock Driver
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/clock/mt7621-clk.h>
17 #include <dt-bindings/reset/mt7621-reset.h>
36 struct regmap *sysc; member
101 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_enable() local
103 return regmap_update_bits(sysc, SYSC_REG_CLKCFG1, in mt7621_gate_enable()
104 clk_gate->bit_idx, clk_gate->bit_idx); in mt7621_gate_enable()
110 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_disable() local
112 regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0); in mt7621_gate_disable()
118 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_is_enabled() local
121 if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val)) in mt7621_gate_is_enabled()
124 return val & BIT(clk_gate->bit_idx); in mt7621_gate_is_enabled()
139 .parent_names = &sclk->parent_name, in mt7621_gate_ops_init()
141 .name = sclk->name, in mt7621_gate_ops_init()
144 sclk->hw.init = &init; in mt7621_gate_ops_init()
145 return devm_clk_hw_register(dev, &sclk->hw); in mt7621_gate_ops_init()
152 struct clk_hw **hws = clk_data->hws; in mt7621_register_gates()
158 sclk->priv = priv; in mt7621_register_gates()
161 dev_err(dev, "Couldn't register clock %s\n", sclk->name); in mt7621_register_gates()
165 hws[sclk->idx] = &sclk->hw; in mt7621_register_gates()
171 while (--i >= 0) { in mt7621_register_gates()
173 clk_hw_unregister(&sclk->hw); in mt7621_register_gates()
197 struct clk_hw **hws = clk_data->hws; in mt7621_register_fixed_clocks()
203 sclk->hw = clk_hw_register_fixed_rate(dev, sclk->name, in mt7621_register_fixed_clocks()
204 sclk->parent_name, 0, in mt7621_register_fixed_clocks()
205 sclk->rate); in mt7621_register_fixed_clocks()
206 if (IS_ERR(sclk->hw)) { in mt7621_register_fixed_clocks()
207 dev_err(dev, "Couldn't register clock %s\n", sclk->name); in mt7621_register_fixed_clocks()
208 ret = PTR_ERR(sclk->hw); in mt7621_register_fixed_clocks()
212 hws[sclk->idx] = sclk->hw; in mt7621_register_fixed_clocks()
218 while (--i >= 0) { in mt7621_register_fixed_clocks()
220 clk_hw_unregister_fixed_rate(sclk->hw); in mt7621_register_fixed_clocks()
234 struct regmap *sysc = clk->priv->sysc; in mt7621_xtal_recalc_rate() local
237 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG0, &val); in mt7621_xtal_recalc_rate()
253 struct regmap *sysc = clk->priv->sysc; in mt7621_cpu_recalc_rate() local
254 struct regmap *memc = clk->priv->memc; in mt7621_cpu_recalc_rate()
259 regmap_read(sysc, SYSC_REG_CLKCFG0, &clkcfg); in mt7621_cpu_recalc_rate()
262 regmap_read(sysc, SYSC_REG_CUR_CLK_STS, &curclk); in mt7621_cpu_recalc_rate()
315 struct clk_hw **hws = clk_data->hws; in mt7621_register_early_clocks()
321 sclk->priv = priv; in mt7621_register_early_clocks()
322 ret = of_clk_hw_register(np, &sclk->hw); in mt7621_register_early_clocks()
328 hws[i] = &sclk->hw; in mt7621_register_early_clocks()
329 mt7621_clk_early[i] = &sclk->hw; in mt7621_register_early_clocks()
333 mt7621_clk_early[j] = ERR_PTR(-EPROBE_DEFER); in mt7621_register_early_clocks()
338 while (--i >= 0) { in mt7621_register_early_clocks()
340 clk_hw_unregister(&sclk->hw); in mt7621_register_early_clocks()
355 priv->sysc = syscon_node_to_regmap(node); in mt7621_clk_init()
356 if (IS_ERR(priv->sysc)) { in mt7621_clk_init()
357 pr_err("Could not get sysc syscon regmap\n"); in mt7621_clk_init()
361 priv->memc = syscon_regmap_lookup_by_phandle(node, "ralink,memctl"); in mt7621_clk_init()
362 if (IS_ERR(priv->memc)) { in mt7621_clk_init()
379 clk_data->num = count; in mt7621_clk_init()
393 clk_hw_unregister(&sclk->hw); in mt7621_clk_init()
402 CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init);
406 struct regmap *sysc; member
418 struct regmap *sysc = data->sysc; in mt7621_assert_device() local
420 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); in mt7621_assert_device()
427 struct regmap *sysc = data->sysc; in mt7621_deassert_device() local
429 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); in mt7621_deassert_device()
447 unsigned long id = reset_spec->args[0]; in mt7621_rst_xlate()
449 if (id == MT7621_RST_SYS || id >= rcdev->nr_resets) in mt7621_rst_xlate()
450 return -EINVAL; in mt7621_rst_xlate()
461 static int mt7621_reset_init(struct device *dev, struct regmap *sysc) in mt7621_reset_init() argument
467 return -ENOMEM; in mt7621_reset_init()
469 rst_data->sysc = sysc; in mt7621_reset_init()
470 rst_data->rcdev.ops = &reset_ops; in mt7621_reset_init()
471 rst_data->rcdev.owner = THIS_MODULE; in mt7621_reset_init()
472 rst_data->rcdev.nr_resets = 32; in mt7621_reset_init()
473 rst_data->rcdev.of_reset_n_cells = 1; in mt7621_reset_init()
474 rst_data->rcdev.of_xlate = mt7621_rst_xlate; in mt7621_reset_init()
475 rst_data->rcdev.of_node = dev_of_node(dev); in mt7621_reset_init()
477 return devm_reset_controller_register(dev, &rst_data->rcdev); in mt7621_reset_init()
482 struct device_node *np = pdev->dev.of_node; in mt7621_clk_probe()
484 struct device *dev = &pdev->dev; in mt7621_clk_probe()
490 return -ENOMEM; in mt7621_clk_probe()
492 priv->sysc = syscon_node_to_regmap(np); in mt7621_clk_probe()
493 if (IS_ERR(priv->sysc)) { in mt7621_clk_probe()
494 ret = PTR_ERR(priv->sysc); in mt7621_clk_probe()
495 dev_err(dev, "Could not get sysc syscon regmap\n"); in mt7621_clk_probe()
499 priv->memc = syscon_regmap_lookup_by_phandle(np, "ralink,memctl"); in mt7621_clk_probe()
500 if (IS_ERR(priv->memc)) { in mt7621_clk_probe()
501 ret = PTR_ERR(priv->memc); in mt7621_clk_probe()
506 ret = mt7621_reset_init(dev, priv->sysc); in mt7621_clk_probe()
517 return -ENOMEM; in mt7621_clk_probe()
520 clk_data->hws[i] = mt7621_clk_early[i]; in mt7621_clk_probe()
534 clk_data->num = count; in mt7621_clk_probe()
548 clk_hw_unregister(&sclk->hw); in mt7621_clk_probe()
555 clk_hw_unregister_fixed_rate(sclk->hw); in mt7621_clk_probe()
562 { .compatible = "mediatek,mt7621-sysc" },
569 .name = "mt7621-clk",