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Searched +full:mt7621 +full:- +full:sysc (Results 1 – 7 of 7) sorted by relevance

/Linux-v5.15/drivers/staging/mt7621-dts/
Dmt7621.dtsi1 #include <dt-bindings/interrupt-controller/mips-gic.h>
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/clock/mt7621-clk.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
8 compatible = "mediatek,mt7621-soc";
21 #address-cells = <0>;
22 #interrupt-cells = <1>;
23 interrupt-controller;
24 compatible = "mti,cpu-interrupt-controller";
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/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dmediatek,mt7621-sysc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MT7621 Clock Device Tree Bindings
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 The MT7621 has a PLL controller from where the cpu clock is provided
21 [1]: <include/dt-bindings/clock/mt7621-clk.h>.
28 - const: mediatek,mt7621-sysc
29 - const: syscon
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/Linux-v5.15/arch/mips/ralink/
Dmt7621.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <asm/smp-ops.h>
17 #include <asm/mips-cps.h>
18 #include <asm/mach-ralink/ralink_regs.h>
19 #include <asm/mach-ralink/mt7621.h>
52 rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc"); in ralink_of_remap()
53 rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc"); in ralink_of_remap()
68 soc_dev_attr->soc_id = "mt7621"; in soc_dev_init()
69 soc_dev_attr->family = "Ralink"; in soc_dev_init()
73 soc_dev_attr->revision = "E2"; in soc_dev_init()
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/Linux-v5.15/drivers/clk/ralink/
Dclk-mt7621.c1 // SPDX-License-Identifier: GPL-2.0
3 * Mediatek MT7621 Clock Driver
9 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/mt7621-clk.h>
33 struct regmap *sysc; member
98 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_enable() local
100 return regmap_update_bits(sysc, SYSC_REG_CLKCFG1, in mt7621_gate_enable()
101 clk_gate->bit_idx, clk_gate->bit_idx); in mt7621_gate_enable()
107 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_disable() local
109 regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0); in mt7621_gate_disable()
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/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dmediatek,mt7621-pci-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Mediatek Mt7621 PCIe PHY Device Tree Bindings
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
14 const: mediatek,mt7621-pci-phy
22 "#phy-cells":
24 description: selects if the phy is dual-ported
27 - compatible
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/Linux-v5.15/arch/mips/boot/dts/ralink/
Dmt7628a.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,mt7628a-soc";
9 #address-cells = <1>;
10 #size-cells = <0>;
19 resetc: reset-controller {
20 compatible = "ralink,rt2880-reset";
21 #reset-cells = <1>;
24 cpuintc: interrupt-controller {
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/Linux-v5.15/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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