1 // SPDX-License-Identifier: GPL-2.0
3  * Mediatek MT7621 Clock Driver
9 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/mt7621-clk.h>
33 	struct regmap *sysc;  member
98 	struct regmap *sysc = clk_gate->priv->sysc;  in mt7621_gate_enable()  local
100 	return regmap_update_bits(sysc, SYSC_REG_CLKCFG1,  in mt7621_gate_enable()
101 				  clk_gate->bit_idx, clk_gate->bit_idx);  in mt7621_gate_enable()
107 	struct regmap *sysc = clk_gate->priv->sysc;  in mt7621_gate_disable()  local
109 	regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0);  in mt7621_gate_disable()
115 	struct regmap *sysc = clk_gate->priv->sysc;  in mt7621_gate_is_enabled()  local
118 	if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val))  in mt7621_gate_is_enabled()
121 	return val & BIT(clk_gate->bit_idx);  in mt7621_gate_is_enabled()
136 		.parent_names = &sclk->parent_name,  in mt7621_gate_ops_init()
138 		.name = sclk->name,  in mt7621_gate_ops_init()
141 	sclk->hw.init = &init;  in mt7621_gate_ops_init()
142 	return devm_clk_hw_register(dev, &sclk->hw);  in mt7621_gate_ops_init()
149 	struct clk_hw **hws = clk_data->hws;  in mt7621_register_gates()
155 		sclk->priv = priv;  in mt7621_register_gates()
158 			dev_err(dev, "Couldn't register clock %s\n", sclk->name);  in mt7621_register_gates()
162 		hws[sclk->idx] = &sclk->hw;  in mt7621_register_gates()
168 	while (--i >= 0) {  in mt7621_register_gates()
170 		clk_hw_unregister(&sclk->hw);  in mt7621_register_gates()
194 	struct clk_hw **hws = clk_data->hws;  in mt7621_register_fixed_clocks()
200 		sclk->hw = clk_hw_register_fixed_rate(dev, sclk->name,  in mt7621_register_fixed_clocks()
201 						      sclk->parent_name, 0,  in mt7621_register_fixed_clocks()
202 						      sclk->rate);  in mt7621_register_fixed_clocks()
203 		if (IS_ERR(sclk->hw)) {  in mt7621_register_fixed_clocks()
204 			dev_err(dev, "Couldn't register clock %s\n", sclk->name);  in mt7621_register_fixed_clocks()
205 			ret = PTR_ERR(sclk->hw);  in mt7621_register_fixed_clocks()
209 		hws[sclk->idx] = sclk->hw;  in mt7621_register_fixed_clocks()
215 	while (--i >= 0) {  in mt7621_register_fixed_clocks()
217 		clk_hw_unregister_fixed_rate(sclk->hw);  in mt7621_register_fixed_clocks()
231 	struct regmap *sysc = clk->priv->sysc;  in mt7621_xtal_recalc_rate()  local
234 	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG0, &val);  in mt7621_xtal_recalc_rate()
250 	struct regmap *sysc = clk->priv->sysc;  in mt7621_cpu_recalc_rate()  local
251 	struct regmap *memc = clk->priv->memc;  in mt7621_cpu_recalc_rate()
256 	regmap_read(sysc, SYSC_REG_CLKCFG0, &clkcfg);  in mt7621_cpu_recalc_rate()
259 	regmap_read(sysc, SYSC_REG_CUR_CLK_STS, &curclk);  in mt7621_cpu_recalc_rate()
312 	struct clk_hw **hws = clk_data->hws;  in mt7621_register_early_clocks()
318 		sclk->priv = priv;  in mt7621_register_early_clocks()
319 		ret = of_clk_hw_register(np, &sclk->hw);  in mt7621_register_early_clocks()
325 		hws[i] = &sclk->hw;  in mt7621_register_early_clocks()
326 		mt7621_clk_early[i] = &sclk->hw;  in mt7621_register_early_clocks()
330 		mt7621_clk_early[j] = ERR_PTR(-EPROBE_DEFER);  in mt7621_register_early_clocks()
335 	while (--i >= 0) {  in mt7621_register_early_clocks()
337 		clk_hw_unregister(&sclk->hw);  in mt7621_register_early_clocks()
352 	priv->sysc = syscon_node_to_regmap(node);  in mt7621_clk_init()
353 	if (IS_ERR(priv->sysc)) {  in mt7621_clk_init()
354 		pr_err("Could not get sysc syscon regmap\n");  in mt7621_clk_init()
358 	priv->memc = syscon_regmap_lookup_by_phandle(node, "ralink,memctl");  in mt7621_clk_init()
359 	if (IS_ERR(priv->memc)) {  in mt7621_clk_init()
376 	clk_data->num = count;  in mt7621_clk_init()
390 		clk_hw_unregister(&sclk->hw);  in mt7621_clk_init()
399 CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init);
403 	struct device_node *np = pdev->dev.of_node;  in mt7621_clk_probe()
405 	struct device *dev = &pdev->dev;  in mt7621_clk_probe()
411 		return -ENOMEM;  in mt7621_clk_probe()
413 	priv->sysc = syscon_node_to_regmap(np);  in mt7621_clk_probe()
414 	if (IS_ERR(priv->sysc)) {  in mt7621_clk_probe()
415 		ret = PTR_ERR(priv->sysc);  in mt7621_clk_probe()
416 		dev_err(dev, "Could not get sysc syscon regmap\n");  in mt7621_clk_probe()
420 	priv->memc = syscon_regmap_lookup_by_phandle(np, "ralink,memctl");  in mt7621_clk_probe()
421 	if (IS_ERR(priv->memc)) {  in mt7621_clk_probe()
422 		ret = PTR_ERR(priv->memc);  in mt7621_clk_probe()
432 		return -ENOMEM;  in mt7621_clk_probe()
435 		clk_data->hws[i] = mt7621_clk_early[i];  in mt7621_clk_probe()
449 	clk_data->num = count;  in mt7621_clk_probe()
463 		clk_hw_unregister(&sclk->hw);  in mt7621_clk_probe()
470 		clk_hw_unregister_fixed_rate(sclk->hw);  in mt7621_clk_probe()
477 	{ .compatible = "mediatek,mt7621-sysc" },
484 		.name = "mt7621-clk",