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/Linux-v5.10/Documentation/devicetree/bindings/pci/
Dpci-msi.txt2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
[all …]
Dbrcm,iproc-pcie.txt1 * Broadcom iProc PCIe controller with the platform bus interface
4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
10 controller, used in NS2
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
12 controller, used in Stingray
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
[all …]
Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
[all …]
Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Brcmstb PCIe Host Controller Device Tree Bindings
10 - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
18 - brcm,bcm7278-pcie # Broadcom 7278 Arm
[all …]
Daltera-pcie-msi.txt1 * Altera PCIe MSI controller
4 - compatible: should contain "altr,msi-1.0"
5 - reg: specifies the physical base address of the controller and
7 - reg-names: must include the following entries:
10 - interrupts: specifies the interrupt source of the parent interrupt
11 controller. The format of the interrupt specifier depends on the
12 parent interrupt controller.
13 - num-vectors: number of vectors, range 1 to 32.
14 - msi-controller: indicates that this is MSI controller node
18 msi0: msi@0xFF200000 {
[all …]
Dlayerscape-pcie-gen4.txt1 NXP Layerscape PCIe Gen4 controller
3 This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
4 the common properties defined in mobiveil-pcie.txt.
7 - compatible: should contain the platform identifier such as:
8 "fsl,lx2160a-pcie"
9 - reg: base addresses and lengths of the PCIe controller register blocks.
11 "config_axi_slave": PCIe controller registers
12 - interrupts: A list of interrupt outputs of the controller. Must contain an
13 entry for each entry in the interrupt-names property.
14 - interrupt-names: It could include the following entries:
[all …]
Daardvark-pci.txt1 Aardvark PCIe controller
3 This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
5 The Device Tree node describing an Aardvark PCIe controller must
8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
11 - #address-cells: set to <3>
12 - #size-cells: set to <2>
13 - device_type: set to "pci"
14 - ranges: ranges for the PCI memory and I/O regions
[all …]
Dxilinx-nwl-pcie.txt4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
13 "pcireg": PCIe controller registers
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
[all …]
Dxilinx-versal-cpm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CPM Host Controller device tree for Xilinx Versal SoCs
10 - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
17 const: xlnx,versal-cpm-host-1.00
21 - description: Configuration space region and bridge registers.
22 - description: CPM system level control and status registers.
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/
Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
[all …]
Dfsl,ls-scfg-msi.txt1 * Freescale Layerscape SCFG PCIe MSI controller
5 - compatible: should be "fsl,<soc-name>-msi" to identify
6 Layerscape PCIe MSI controller block such as:
7 "fsl,ls1021a-msi"
8 "fsl,ls1043a-msi"
9 "fsl,ls1046a-msi"
10 "fsl,ls1043a-v1.1-msi"
11 "fsl,ls1012a-msi"
12 - msi-controller: indicates that this is a PCIe MSI controller node
13 - reg: physical base address of the controller and length of memory mapped.
[all …]
Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson LS7A family of PCH for
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
[all …]
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <marc.zyngier@arm.com>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
[all …]
Dal,alpine-msix.txt1 Alpine MSIX controller
3 See arm,gic-v3.txt for SPI and MSI definitions.
7 - compatible: should be "al,alpine-msix"
8 - reg: physical base address and size of the registers
9 - interrupt-controller: identifies the node as an interrupt controller
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
11 controller
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
18 compatible = "al,alpine-msix";
[all …]
Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller v1 and v2
10 - Marc Zyngier <marc.zyngier@arm.com>
18 Secondary GICs are cascaded into the upward interrupt controller and do not
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
[all …]
Dmarvell,odmi-controller.txt2 * Marvell ODMI for MSI support
4 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
5 which can be used by on-board peripheral for MSI interrupts.
9 - compatible : The value here should contain:
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
13 - interrupt,controller : Identifies the node as an interrupt controller.
15 - msi-controller : Identifies the node as an MSI controller.
17 - marvell,odmi-frames : Number of ODMI frames available. Each frame
20 - reg : List of register definitions, one for each
23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
[all …]
Dhisilicon,mbigen-v2.txt6 MBI is kind of msi interrupt only used on Non-PCI devices.
12 Non-pci devices can connect to mbigen and generate the
18 -------------------------------------------
19 - compatible: Should be "hisilicon,mbigen-v2"
21 - reg: Specifies the base physical address and size of the Mbigen
25 ------------------------------------------
26 - interrupt controller: Identifies the node as an interrupt controller
28 - msi-parent: Specifies the MSI controller this mbigen use.
29 For more detail information,please refer to the generic msi-parent binding in
30 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
[all …]
/Linux-v5.10/arch/arm64/boot/dts/marvell/
Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/Linux-v5.10/drivers/pci/controller/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "PCI controller drivers"
7 bool "Marvell EBU PCIe controller"
15 tristate "Aardvark PCIe controller"
21 Add support for Aardvark 64bit PCIe Host Controller. This
22 controller is part of the South Bridge of the Marvel Armada
31 NWL PCIe controller. The controller can act as Root Port
36 bool "Faraday Technology FTPCI100 PCI controller"
41 bool "NVIDIA Tegra PCIe controller"
46 Say Y here if you want support for the PCIe host controller found
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.txt3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
31 The MSI writes are accompanied by sideband data which is derived from the ICID.
32 The msi-map property is used to associate the devices with both the ITS
33 controller and the sideband data which accompanies the writes.
35 For generic MSI bindings, see
[all …]
/Linux-v5.10/arch/mips/boot/dts/loongson/
Dloongson64c_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
[all …]
Dloongson64g_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64g-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
[all …]
/Linux-v5.10/Documentation/PCI/endpoint/
Dpci-test-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
9 This document is a guide to help users use pci-epf-test function driver
16 Endpoint Controller Devices
17 ---------------------------
19 To find the list of endpoint controller devices in the system::
31 -------------------------
35 # ls /sys/bus/pci-epf/drivers
44 Creating pci-epf-test Device
45 ----------------------------
48 pci-epf-test device, the following commands can be used::
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/powerpc/fsl/
Dmsi-pic.txt1 * Freescale MSI interrupt controller
4 - compatible : compatible list, may contain one or two entries
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
13 - reg : It may contain one or two regions. The first region should contain
17 region must be added because different MSI group has different MSIIR1 offset.
19 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
[all …]
/Linux-v5.10/include/linux/
Dpci-epc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * PCI Endpoint *Controller* (EPC) header file
12 #include <linux/pci-epf.h>
24 * struct pci_epc_ops - set of function pointers for performing EPC operations
30 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
32 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
33 * the MSI capability register
34 * @set_msix: ops to set the requested number of MSI-X interrupts in the
35 * MSI-X capability register
36 * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
[all …]

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