Lines Matching +full:msi +full:- +full:controller

1 * Freescale MSI interrupt controller
4 - compatible : compatible list, may contain one or two entries
5   The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6   etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7   "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
8   version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
9   provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
13 - reg : It may contain one or two regions. The first region should contain
17   region must be added because different MSI group has different MSIIR1 offset.
19 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
20   and routed to the host interrupt controller. the interrupts should
21   be set as edge sensitive.  If msi-available-ranges is present, only
25 - msi-available-ranges: use <start count> style section to define which
26   msi interrupt can be used in the 256 msi interrupts. This property is
27   optional, without this, all the MSI interrupts can be used.
29   no splitting an individual MSI register or the associated PIC interrupt).
33 - msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
34   is used for MSI messaging.  The address of MSIIR in PCI address space is
35   the MSI message address.
43 	msi@41600 {
44 		compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
46 		msi-available-ranges = <0 0x100>;
56 		interrupt-parent = <&mpic>;
59 	msi@41600 {
60 		compatible = "fsl,mpic-msi-v4.3";
81 The Freescale hypervisor and msi-address-64
82 -------------------------------------------
84 Freescale MSI driver calculates the address of MSIIR (in the MSI register
85 block) and sets that address as the MSI message address.
94 In the PAMU, each PCI controller is given only one primary window.  The
109 this.  The address specified in the msi-address-64 property is the PCI