Lines Matching +full:msi +full:- +full:controller

1 NXP Layerscape PCIe Gen4 controller
3 This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
4 the common properties defined in mobiveil-pcie.txt.
7 - compatible: should contain the platform identifier such as:
8   "fsl,lx2160a-pcie"
9 - reg: base addresses and lengths of the PCIe controller register blocks.
11   "config_axi_slave": PCIe controller registers
12 - interrupts: A list of interrupt outputs of the controller. Must contain an
13   entry for each entry in the interrupt-names property.
14 - interrupt-names: It could include the following entries:
15   "intr": The interrupt that is asserted for controller interrupts
17 	 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
19 	 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
20 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
23 - msi-parent : See the generic MSI binding described in
24   Documentation/devicetree/bindings/interrupt-controller/msi.txt.
29 		compatible = "fsl,lx2160a-pcie";
30 		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
32 		reg-names = "csr_axi_slave", "config_axi_slave";
35 			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
36 		interrupt-names = "aer", "pme", "intr";
37 		#address-cells = <3>;
38 		#size-cells = <2>;
40 		apio-wins = <8>;
41 		ppio-wins = <8>;
42 		dma-coherent;
43 		bus-range = <0x0 0xff>;
44 		msi-parent = <&its>;
46 		#interrupt-cells = <1>;
47 		interrupt-map-mask = <0 0 0 7>;
48 		interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,