Home
last modified time | relevance | path

Searched +full:lo +full:- +full:x2 +full:- +full:en (Results 1 – 18 of 18) sorted by relevance

/Linux-v6.1/Documentation/devicetree/bindings/iio/frequency/
Dadi,adrf6780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
16 https://www.analog.com/en/products/adrf6780.html
21 - adi,adrf6780
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
38 clock-output-names:
[all …]
/Linux-v6.1/drivers/iio/frequency/
Dadrf6780.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
98 st->data[0] = 0x80 | (reg << 1); in __adrf6780_spi_read()
99 st->data[1] = 0x0; in __adrf6780_spi_read()
100 st->data[2] = 0x0; in __adrf6780_spi_read()
102 t.rx_buf = &st->data[0]; in __adrf6780_spi_read()
103 t.tx_buf = &st->data[0]; in __adrf6780_spi_read()
106 ret = spi_sync_transfer(st->spi, &t, 1); in __adrf6780_spi_read()
110 *val = (get_unaligned_be24(&st->data[0]) >> 1) & GENMASK(15, 0); in __adrf6780_spi_read()
120 mutex_lock(&st->lock); in adrf6780_spi_read()
[all …]
/Linux-v6.1/drivers/iio/light/
Dmax44009.c1 // SPDX-License-Identifier: GPL-2.0
3 * max44009.c - Support for MAX44009 Ambient Light Sensor
7 * Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX44009.pdf
31 #define MAX44009_REG_CFG 0x2
51 /* The max44009 always scales raw readings by 0.045 and is non-configurable */
55 /* The fixed-point fractional multiplier for de-scaling threshold values */
112 int ret = i2c_smbus_read_byte_data(data->client, MAX44009_REG_CFG); in max44009_read_int_time()
123 struct i2c_client *client = data->client; in max44009_write_int_time()
156 if (mask == IIO_CHAN_INFO_INT_TIME && chan->type == IIO_LIGHT) { in max44009_write_raw()
157 mutex_lock(&data->lock); in max44009_write_raw()
[all …]
/Linux-v6.1/drivers/net/ethernet/chelsio/cxgb/
Dvsc7326.c1 // SPDX-License-Identifier: GPL-2.0
17 * for disabling the T2/MAC flow-control. When the interface is
40 spin_lock_bh(&adapter->mac_lock); in vsc_read()
60 spin_unlock_bh(&adapter->mac_lock); in vsc_read()
65 spin_lock_bh(&adapter->mac_lock); in vsc_write()
71 spin_unlock_bh(&adapter->mac_lock); in vsc_write()
240 (address != 0x2) && in bist_rd()
267 (address != 0x2) && in bist_wr()
385 int port = mac->instance->index; in mac_set_address()
387 vsc_write(mac->adapter, REG_MAC_LOW_ADDR(port), in mac_set_address()
[all …]
/Linux-v6.1/drivers/net/ethernet/atheros/atl1c/
Datl1c_hw.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
56 /* hw-ids */
103 #define PCIE_DEV_MISC_EXT_PIPE 0x2
152 * ->L0s not L1 */
171 #define PM_CTRL_CLK_SWH_L1 BIT(13) /* en pcie clk sw in L1 */
205 #define MASTER_CTRL_SA_TIMER_EN BIT(7) /* SYS ALIVE TIMER EN */
307 #define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is
308 * un-repairable because
[all …]
/Linux-v6.1/drivers/thermal/tegra/
Dsoctherm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
81 #define THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY 0x2
84 #define THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY 0x2
106 #define STATS_CTL_CLR_UP 0x2
127 #define OC_STATS_CTL_CLR_ALL 0x2
197 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
200 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
203 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
[all …]
/Linux-v6.1/Documentation/translations/it_IT/doc-guide/
Dsphinx.rst1 .. include:: ../disclaimer-ita.rst
4 :ref:`Documentation/doc-guide/index.rst <doc_guide>`
18 .. _Sphinx: http://www.sphinx-doc.org/
22 includere i commenti di documentazione, o di tipo kernel-doc, dai file
25 e l'architettura del codice. I commenti di tipo kernel-doc hanno una struttura
42 consultate :ref:`it_sphinx-pre-install`.
52 ``virtualenv-3`` o ``virtualenv`` a seconda di come Python 3 è stato
70 (sphinx_2.4.4) $ pip install -r Documentation/sphinx/requirements.txt
78 ----------------------
90 --------------------------
[all …]
/Linux-v6.1/drivers/net/ethernet/freescale/enetc/
Denetc.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2017-2019 NXP */
16 int num_tx_rings = priv->num_tx_rings; in enetc_num_stack_tx_queues()
19 for (i = 0; i < priv->num_rx_rings; i++) in enetc_num_stack_tx_queues()
20 if (priv->rx_ring[i]->xdp.prog) in enetc_num_stack_tx_queues()
21 return num_tx_rings - num_possible_cpus(); in enetc_num_stack_tx_queues()
29 int index = &priv->tx_ring[tx_ring->index] - priv->xdp_tx_ring; in enetc_rx_ring_from_xdp_tx_ring()
31 return priv->rx_ring[index]; in enetc_rx_ring_from_xdp_tx_ring()
36 if (tx_swbd->is_xdp_tx || tx_swbd->is_xdp_redirect) in enetc_tx_swbd_get_skb()
39 return tx_swbd->skb; in enetc_tx_swbd_get_skb()
[all …]
/Linux-v6.1/drivers/net/ethernet/agere/
Det131x.h52 /* LBCIF Register Groups (addressed via 32-bit offsets) */
56 /* LBCIF Registers (addressed via 8-bit offsets) */
196 * 31-10: unused
197 * 9-0: pr ndes
217 * txdma status writeback address lo reg in txdma address map at 0x1020
276 * 1-3: tc
281 * 8-9: fbr0_size
283 * 11-12: fbr1_size
289 * 18-31: unused
300 /* structure for dma writeback lo reg in rxdma address map
[all …]
/Linux-v6.1/drivers/net/ethernet/
Djme.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
34 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
39 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
117 PE1_GPREG0_ENBG = 0x00000000, /* en BG */
377 #define NET_STAT(priv) (priv->dev->stats)
387 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
389 if (!napi_disable_pending(&priv->napi)) \
390 napi_disable(&priv->napi);
[all …]
/Linux-v6.1/arch/mips/include/asm/
Dkvm_host.h102 #define KVM_HVA_ERR_BAD (-1UL)
103 #define KVM_HVA_ERR_RO_BAD (-2UL)
153 uint32_t en; member
265 #define VPN2_MASK GENMASK(cpu_vmbits - 1, 13)
288 #define KVM_MIPS_AUX_MSA 0x2
311 unsigned long lo; member
439 return cop0->reg[(_reg)][(sel)]; \
444 cop0->reg[(_reg)][(sel)] = val; \
452 cop0->reg[(_reg)][(sel)] |= val; \
457 cop0->reg[(_reg)][(sel)] &= ~val; \
[all …]
/Linux-v6.1/drivers/pinctrl/nuvoton/
Dpinctrl-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2016-2018 Nuvoton Technology corporation.
16 #include <linux/pinctrl/pinconf-generic.h>
48 #define NPCM7XX_GP_N_PU 0x1c /* Pull-up */
49 #define NPCM7XX_GP_N_PD 0x20 /* Pull-down */
108 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_set()
113 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_set()
122 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_clr()
127 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_clr()
134 seq_printf(s, "-- module %d [gpio%d - %d]\n", in npcmgpio_dbg_show()
[all …]
/Linux-v6.1/drivers/net/wireless/realtek/rtw89/
Dcoex.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
31 CXTDMA_AUTO = 0x2,
39 CXFLC_QOSNULL = 0x2,
166 CXPOLICY_TYPE = 0x2,
262 /* TDMA off + pri: WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo */
265 /* TDMA off + pri: WL_Hi-Tx > BT, BT_Hi > other-WL > BT_Lo */
268 /* TDMA off + pri: WL_Hi-Tx = BT */
271 /* TDMA off+Bcn-Protect + pri: WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo*/
274 /* TDMA off + Ext-Ctrl + pri: default */
[all …]
/Linux-v6.1/drivers/net/wireless/broadcom/b43/
Dmain.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
8 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
11 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
17 driver Copyright(c) 2003 - 2004 Intel Corporation.
31 #include <linux/dma-mapping.h>
45 #include "lo.h"
86 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
373 if (!wl || !wl->current_dev) in b43_ratelimit()
375 if (b43_status(wl->current_dev) < B43_STAT_STARTED) in b43_ratelimit()
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2
1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
[all …]
Dgfx_v11_0.c131 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx11_kiq_set_resources()
133 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx11_kiq_set_resources()
142 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); in gfx11_kiq_map_queues()
143 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx11_kiq_map_queues()
146 switch (ring->funcs->type) { in gfx11_kiq_map_queues()
168 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | in gfx11_kiq_map_queues()
169 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | in gfx11_kiq_map_queues()
175 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); in gfx11_kiq_map_queues()
187 struct amdgpu_device *adev = kiq_ring->adev; in gfx11_kiq_unmap_queues()
188 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; in gfx11_kiq_unmap_queues()
[all …]
Dgfx_v8_0.c740 switch (adev->asic_type) { in gfx_v8_0_init_golden_registers()
803 if ((adev->pdev->device == 0x67DF) && (adev->pdev->revision == 0xc7) && in gfx_v8_0_init_golden_registers()
804 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) || in gfx_v8_0_init_golden_registers()
805 (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) || in gfx_v8_0_init_golden_registers()
806 (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1680))) { in gfx_v8_0_init_golden_registers()
840 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_ring_test_ring()
851 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); in gfx_v8_0_ring_test_ring()
855 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_ring_test_ring()
862 if (i >= adev->usec_timeout) in gfx_v8_0_ring_test_ring()
863 r = -ETIMEDOUT; in gfx_v8_0_ring_test_ring()
[all …]
Dgfx_v9_0.c247 /* TCC (5 sub-ranges)*/
310 /* EA (3 sub-ranges)*/
722 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
723 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
724 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
725 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
726 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
727 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
728 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
729 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
[all …]