Lines Matching +full:lo +full:- +full:x2 +full:- +full:en
102 #define KVM_HVA_ERR_BAD (-1UL)
103 #define KVM_HVA_ERR_RO_BAD (-2UL)
153 uint32_t en; member
265 #define VPN2_MASK GENMASK(cpu_vmbits - 1, 13)
288 #define KVM_MIPS_AUX_MSA 0x2
311 unsigned long lo; member
439 return cop0->reg[(_reg)][(sel)]; \
444 cop0->reg[(_reg)][(sel)] = val; \
452 cop0->reg[(_reg)][(sel)] |= val; \
457 cop0->reg[(_reg)][(sel)] &= ~val; \
464 cop0->reg[(_reg)][(sel)] &= ~_mask; \
465 cop0->reg[(_reg)][(sel)] |= val & _mask; \
473 _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
478 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
484 _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \
528 write_gc0_##name(cop0->reg[(_reg)][(sel)]); \
532 cop0->reg[(_reg)][(sel)] = read_gc0_##name(); \
536 * __BUILD_KVM_$ops_WRAP(): kvm_$op_$name1() -> kvm_$op_$name2()
572 * __BUILD_KVM_$ops_SW(): kvm_$op_c0_guest_$reg() -> kvm_$op_sw_gc0_$reg()
595 * __BUILD_KVM_$ops_HW(): kvm_$op_c0_guest_$reg() -> kvm_$op_vz_gc0_$reg()
695 vcpu->fpu_enabled; in kvm_mips_guest_can_have_fpu()
701 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP; in kvm_mips_guest_has_fpu()
707 vcpu->msa_enabled; in kvm_mips_guest_can_have_msa()
713 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA; in kvm_mips_guest_has_msa()
821 * kvm_is_ifetch_fault() - Find whether a TLBL exception is due to ifetch fault.
829 unsigned long badvaddr = vcpu->host_cp0_badvaddr; in kvm_is_ifetch_fault()
830 unsigned long epc = msk_isa16_mode(vcpu->pc); in kvm_is_ifetch_fault()
831 u32 cause = vcpu->host_cp0_cause; in kvm_is_ifetch_fault()
837 * Branches may be 32-bit or 16-bit instructions. in kvm_is_ifetch_fault()
841 if ((cause & CAUSEF_BD) && badvaddr - epc <= 4) in kvm_is_ifetch_fault()