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Searched +full:ipq4019 +full:- +full:nand (Results 1 – 12 of 12) sorted by relevance

/Linux-v6.1/Documentation/devicetree/bindings/mtd/
Dqcom,nandc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm NAND controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - qcom,ipq806x-nand
16 - qcom,ipq4019-nand
17 - qcom,ipq6018-nand
18 - qcom,ipq8074-nand
19 - qcom,sdx55-nand
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dqcom-ipq4019.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 model = "Qualcomm Technologies, Inc. IPQ4019";
17 compatible = "qcom,ipq4019";
18 interrupt-parent = <&intc>;
[all …]
Dqcom-ipq4019-ap.dk04.1-c1.dts1 // SPDX-License-Identifier: GPL-2.0
4 #include "qcom-ipq4019-ap.dk04.1.dtsi"
7 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
8 compatible = "qcom,ipq4019-dk04.1-c1", "qcom,ipq4019";
11 dma-controller@7984000 {
15 qpic-nand@79b0000 {
Dqcom-ipq4019-ap.dk07.1.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
22 stdout-path = "serial0:115200n8";
27 serial_0_pins: serial0-pinmux {
30 bias-disable;
33 i2c_0_pins: i2c-0-pinmux {
36 bias-disable;
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Dqcom-ipq4019-ap.dk04.1.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
17 stdout-path = "serial0:115200n8";
27 serial_0_pins: serial0-pinmux {
30 bias-disable;
33 serial_1_pins: serial1-pinmux {
37 bias-disable;
[all …]
Dqcom-ipq4018-jalapeno.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
27 bias-pull-up;
35 bias-disable;
43 drive-strength = <2>;
44 bias-disable;
50 drive-strength = <2>;
51 bias-disable;
[all …]
Dqcom-ipq4018-ap120c-ac.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
8 model = "ALFA Network AP120C-AC";
9 compatible = "alfa-network,ap120c-ac";
12 compatible = "gpio-keys";
14 key-reset {
27 drive-strength = <16>;
28 bias-disable;
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 dtb-$(CONFIG_ARCH_ALPINE) += \
3 alpine-db.dtb
4 dtb-$(CONFIG_MACH_ARTPEC6) += \
5 artpec6-devboard.dtb
6 dtb-$(CONFIG_MACH_ASM9260) += \
7 alphascale-asm9260-devkit.dtb
9 dtb-$(CONFIG_SOC_AT91RM9200) += \
12 dtb-$(CONFIG_SOC_AT91SAM9) += \
14 at91-qil_a9260.dtb \
[all …]
/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dipq6018.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
11 #include <dt-bindings/clock/qcom,apss-ipq.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&intc>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
[all …]
Dipq8074.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
15 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
20 clock-frequency = <32768>;
21 #clock-cells = <0>;
25 compatible = "fixed-clock";
[all …]
/Linux-v6.1/drivers/mtd/nand/raw/
Dqcom_nandc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
151 /* NAND OP_CMDs */
171 * the NAND controller performs reads/writes with ECC in 516 byte chunks.
206 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
208 /* Returns the NAND register physical address */
209 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
213 ((chip)->reg_read_dma + \
214 ((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
240 * NAND transfers.
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/Linux-v6.1/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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