Lines Matching +full:ipq4019 +full:- +full:nand
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
151 /* NAND OP_CMDs */
171 * the NAND controller performs reads/writes with ECC in 516 byte chunks.
206 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
208 /* Returns the NAND register physical address */
209 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
213 ((chip)->reg_read_dma + \
214 ((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
240 * NAND transfers.
241 * @bam_ce - the array of BAM command elements
242 * @cmd_sgl - sgl for NAND BAM command pipe
243 * @data_sgl - sgl for NAND BAM consumer/producer pipe
244 * @last_data_desc - last DMA desc in data channel (tx/rx).
245 * @last_cmd_desc - last DMA desc in command channel.
246 * @txn_done - completion for NAND transfer.
247 * @bam_ce_pos - the index in bam_ce which is available for next sgl
248 * @bam_ce_start - the index in bam_ce which marks the start position ce
251 * @cmd_sgl_pos - current index in command sgl.
252 * @cmd_sgl_start - start index in command sgl.
253 * @tx_sgl_pos - current index in data sgl for tx.
254 * @tx_sgl_start - start index in data sgl for tx.
255 * @rx_sgl_pos - current index in data sgl for rx.
256 * @rx_sgl_start - start index in data sgl for rx.
257 * @wait_second_completion - wait for second DMA desc completion before making
258 * the NAND transfer completion.
279 * This data type corresponds to the nand dma descriptor
280 * @dma_desc - low level DMA engine descriptor
281 * @list - list for desc_info
283 * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
285 * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
286 * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
287 * @dir - DMA transfer direction
342 * NAND controller data struct
355 * @props: properties of current NAND controller,
377 * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
380 * from all connected NAND devices pagesize
438 * NAND special boot partitions
451 * NAND chip structure
456 * @chip: base NAND chip structure
476 * ecc/non-ecc mode for the current nand flash
518 * This data type corresponds to the NAND controller properties which varies
519 * among different NAND controllers.
520 * @ecc_modes - ecc mode for NAND
521 * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
522 * @is_bam - whether NAND controller is using BAM
523 * @is_qpic - whether NAND CTRL is part of qpic IP
524 * @qpic_v2 - flag to indicate QPIC IP version 2
525 * @use_codeword_fixup - whether NAND has different layout for boot partitions
539 struct bam_transaction *bam_txn = nandc->bam_txn; in free_bam_transaction()
541 devm_kfree(nandc->dev, bam_txn); in free_bam_transaction()
550 unsigned int num_cw = nandc->max_cwperpage; in alloc_bam_transaction()
555 ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) + in alloc_bam_transaction()
556 (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) + in alloc_bam_transaction()
557 (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL)); in alloc_bam_transaction()
559 bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL); in alloc_bam_transaction()
566 bam_txn->bam_ce = bam_txn_buf; in alloc_bam_transaction()
568 sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw; in alloc_bam_transaction()
570 bam_txn->cmd_sgl = bam_txn_buf; in alloc_bam_transaction()
572 sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw; in alloc_bam_transaction()
574 bam_txn->data_sgl = bam_txn_buf; in alloc_bam_transaction()
576 init_completion(&bam_txn->txn_done); in alloc_bam_transaction()
584 struct bam_transaction *bam_txn = nandc->bam_txn; in clear_bam_transaction()
586 if (!nandc->props->is_bam) in clear_bam_transaction()
589 bam_txn->bam_ce_pos = 0; in clear_bam_transaction()
590 bam_txn->bam_ce_start = 0; in clear_bam_transaction()
591 bam_txn->cmd_sgl_pos = 0; in clear_bam_transaction()
592 bam_txn->cmd_sgl_start = 0; in clear_bam_transaction()
593 bam_txn->tx_sgl_pos = 0; in clear_bam_transaction()
594 bam_txn->tx_sgl_start = 0; in clear_bam_transaction()
595 bam_txn->rx_sgl_pos = 0; in clear_bam_transaction()
596 bam_txn->rx_sgl_start = 0; in clear_bam_transaction()
597 bam_txn->last_data_desc = NULL; in clear_bam_transaction()
598 bam_txn->wait_second_completion = false; in clear_bam_transaction()
600 sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * in clear_bam_transaction()
602 sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage * in clear_bam_transaction()
605 reinit_completion(&bam_txn->txn_done); in clear_bam_transaction()
614 * In case of data transfer with NAND, 2 callbacks will be generated. in qpic_bam_dma_done()
620 if (bam_txn->wait_second_completion) in qpic_bam_dma_done()
621 bam_txn->wait_second_completion = false; in qpic_bam_dma_done()
623 complete(&bam_txn->txn_done); in qpic_bam_dma_done()
634 return container_of(chip->controller, struct qcom_nand_controller, in get_qcom_nand_controller()
640 return ioread32(nandc->base + offset); in nandc_read()
646 iowrite32(val, nandc->base + offset); in nandc_write()
652 if (!nandc->props->is_bam) in nandc_read_buffer_sync()
656 dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
658 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
661 dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
663 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
671 return ®s->cmd; in offset_to_nandc_reg()
673 return ®s->addr0; in offset_to_nandc_reg()
675 return ®s->addr1; in offset_to_nandc_reg()
677 return ®s->chip_sel; in offset_to_nandc_reg()
679 return ®s->exec; in offset_to_nandc_reg()
681 return ®s->clrflashstatus; in offset_to_nandc_reg()
683 return ®s->cfg0; in offset_to_nandc_reg()
685 return ®s->cfg1; in offset_to_nandc_reg()
687 return ®s->ecc_bch_cfg; in offset_to_nandc_reg()
689 return ®s->clrreadstatus; in offset_to_nandc_reg()
691 return ®s->cmd1; in offset_to_nandc_reg()
693 return ®s->orig_cmd1; in offset_to_nandc_reg()
695 return ®s->vld; in offset_to_nandc_reg()
697 return ®s->orig_vld; in offset_to_nandc_reg()
699 return ®s->ecc_buf_cfg; in offset_to_nandc_reg()
701 return ®s->read_location0; in offset_to_nandc_reg()
703 return ®s->read_location1; in offset_to_nandc_reg()
705 return ®s->read_location2; in offset_to_nandc_reg()
707 return ®s->read_location3; in offset_to_nandc_reg()
709 return ®s->read_location_last0; in offset_to_nandc_reg()
711 return ®s->read_location_last1; in offset_to_nandc_reg()
713 return ®s->read_location_last2; in offset_to_nandc_reg()
715 return ®s->read_location_last3; in offset_to_nandc_reg()
725 struct nandc_regs *regs = nandc->regs; in nandc_set_reg()
737 return cw == (ecc->steps - 1); in qcom_nandc_is_last_cw()
745 struct nand_ecc_ctrl *ecc = &chip->ecc; in nandc_set_read_loc()
748 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
753 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
764 struct nand_chip *chip = &host->chip; in set_address()
766 if (chip->options & NAND_BUSWIDTH_16) in set_address()
775 * written to the NAND controller registers via DMA
783 struct nand_chip *chip = &host->chip; in update_rw_regs()
788 if (host->use_ecc) in update_rw_regs()
796 if (host->use_ecc) { in update_rw_regs()
797 cfg0 = (host->cfg0 & ~(7U << CW_PER_PAGE)) | in update_rw_regs()
798 (num_cw - 1) << CW_PER_PAGE; in update_rw_regs()
800 cfg1 = host->cfg1; in update_rw_regs()
801 ecc_bch_cfg = host->ecc_bch_cfg; in update_rw_regs()
803 cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) | in update_rw_regs()
804 (num_cw - 1) << CW_PER_PAGE; in update_rw_regs()
806 cfg1 = host->cfg1_raw; in update_rw_regs()
814 if (!nandc->props->qpic_v2) in update_rw_regs()
815 nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg); in update_rw_regs()
816 nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus); in update_rw_regs()
817 nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus); in update_rw_regs()
821 nandc_set_read_loc(chip, cw, 0, 0, host->use_ecc ? in update_rw_regs()
822 host->cw_data : host->cw_size, 1); in update_rw_regs()
827 * for BAM. This descriptor will be added in the NAND DMA descriptor queue
838 struct bam_transaction *bam_txn = nandc->bam_txn; in prepare_bam_async_desc()
844 return -ENOMEM; in prepare_bam_async_desc()
846 if (chan == nandc->cmd_chan) { in prepare_bam_async_desc()
847 sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start]; in prepare_bam_async_desc()
848 sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start; in prepare_bam_async_desc()
849 bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos; in prepare_bam_async_desc()
851 desc->dir = DMA_TO_DEVICE; in prepare_bam_async_desc()
852 } else if (chan == nandc->tx_chan) { in prepare_bam_async_desc()
853 sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start]; in prepare_bam_async_desc()
854 sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start; in prepare_bam_async_desc()
855 bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos; in prepare_bam_async_desc()
857 desc->dir = DMA_TO_DEVICE; in prepare_bam_async_desc()
859 sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start]; in prepare_bam_async_desc()
860 sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start; in prepare_bam_async_desc()
861 bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos; in prepare_bam_async_desc()
863 desc->dir = DMA_FROM_DEVICE; in prepare_bam_async_desc()
866 sg_mark_end(sgl + sgl_cnt - 1); in prepare_bam_async_desc()
867 ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
869 dev_err(nandc->dev, "failure in mapping desc\n"); in prepare_bam_async_desc()
871 return -ENOMEM; in prepare_bam_async_desc()
874 desc->sgl_cnt = sgl_cnt; in prepare_bam_async_desc()
875 desc->bam_sgl = sgl; in prepare_bam_async_desc()
881 dev_err(nandc->dev, "failure in prep desc\n"); in prepare_bam_async_desc()
882 dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
884 return -EINVAL; in prepare_bam_async_desc()
887 desc->dma_desc = dma_desc; in prepare_bam_async_desc()
890 if (chan == nandc->cmd_chan) in prepare_bam_async_desc()
891 bam_txn->last_cmd_desc = dma_desc; in prepare_bam_async_desc()
893 bam_txn->last_data_desc = dma_desc; in prepare_bam_async_desc()
895 list_add_tail(&desc->node, &nandc->desc_list); in prepare_bam_async_desc()
901 * Prepares the command descriptor for BAM DMA which will be used for NAND
916 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_cmd()
918 bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos]; in prep_bam_dma_desc_cmd()
935 bam_txn->bam_ce_pos += size; in prep_bam_dma_desc_cmd()
939 bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start]; in prep_bam_dma_desc_cmd()
940 bam_ce_size = (bam_txn->bam_ce_pos - in prep_bam_dma_desc_cmd()
941 bam_txn->bam_ce_start) * in prep_bam_dma_desc_cmd()
943 sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos], in prep_bam_dma_desc_cmd()
945 bam_txn->cmd_sgl_pos++; in prep_bam_dma_desc_cmd()
946 bam_txn->bam_ce_start = bam_txn->bam_ce_pos; in prep_bam_dma_desc_cmd()
949 ret = prepare_bam_async_desc(nandc, nandc->cmd_chan, in prep_bam_dma_desc_cmd()
961 * Prepares the data descriptor for BAM DMA which will be used for NAND
969 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_data()
972 sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos], in prep_bam_dma_desc_data()
974 bam_txn->rx_sgl_pos++; in prep_bam_dma_desc_data()
976 sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos], in prep_bam_dma_desc_data()
978 bam_txn->tx_sgl_pos++; in prep_bam_dma_desc_data()
985 ret = prepare_bam_async_desc(nandc, nandc->tx_chan, in prep_bam_dma_desc_data()
1009 return -ENOMEM; in prep_adm_dma_desc()
1011 sgl = &desc->adm_sgl; in prep_adm_dma_desc()
1017 desc->dir = DMA_FROM_DEVICE; in prep_adm_dma_desc()
1020 desc->dir = DMA_TO_DEVICE; in prep_adm_dma_desc()
1023 ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir); in prep_adm_dma_desc()
1025 ret = -ENOMEM; in prep_adm_dma_desc()
1034 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
1035 if (nandc->data_crci) { in prep_adm_dma_desc()
1036 periph_conf.crci = nandc->data_crci; in prep_adm_dma_desc()
1042 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
1043 if (nandc->cmd_crci) { in prep_adm_dma_desc()
1044 periph_conf.crci = nandc->cmd_crci; in prep_adm_dma_desc()
1050 ret = dmaengine_slave_config(nandc->chan, &slave_conf); in prep_adm_dma_desc()
1052 dev_err(nandc->dev, "failed to configure dma channel\n"); in prep_adm_dma_desc()
1056 dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0); in prep_adm_dma_desc()
1058 dev_err(nandc->dev, "failed to prepare desc\n"); in prep_adm_dma_desc()
1059 ret = -EINVAL; in prep_adm_dma_desc()
1063 desc->dma_desc = dma_desc; in prep_adm_dma_desc()
1065 list_add_tail(&desc->node, &nandc->desc_list); in prep_adm_dma_desc()
1088 vaddr = nandc->reg_read_buf + nandc->reg_read_pos; in read_reg_dma()
1089 nandc->reg_read_pos += num_regs; in read_reg_dma()
1094 if (nandc->props->is_bam) in read_reg_dma()
1117 struct nandc_regs *regs = nandc->regs; in write_reg_dma()
1124 vaddr = ®s->erased_cw_detect_cfg_set; in write_reg_dma()
1126 vaddr = ®s->erased_cw_detect_cfg_clr; in write_reg_dma()
1138 if (nandc->props->is_bam) in write_reg_dma()
1161 if (nandc->props->is_bam) in read_data_dma()
1179 if (nandc->props->is_bam) in write_data_dma()
1187 * before reading a NAND page.
1195 if (!nandc->props->qpic_v2) in config_nand_page_read()
1204 * before reading each codeword in NAND page.
1210 struct nand_ecc_ctrl *ecc = &chip->ecc; in config_nand_cw_read()
1214 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in config_nand_cw_read()
1217 if (nandc->props->is_bam) in config_nand_cw_read()
1246 * before writing a NAND page.
1254 if (!nandc->props->qpic_v2) in config_nand_page_write()
1261 * before writing each codeword in NAND page.
1277 * the following functions are used within chip->legacy.cmdfunc() to
1284 struct nand_chip *chip = &host->chip; in nandc_param()
1292 if (nandc->props->qpic_v2) in nandc_param()
1312 if (!nandc->props->qpic_v2) in nandc_param()
1316 if (!nandc->props->qpic_v2) { in nandc_param()
1318 (nandc->vld & ~READ_START_VLD)); in nandc_param()
1320 (nandc->cmd1 & ~(0xFF << READ_ADDR)) in nandc_param()
1326 if (!nandc->props->qpic_v2) { in nandc_param()
1327 nandc_set_reg(chip, NAND_DEV_CMD1_RESTORE, nandc->cmd1); in nandc_param()
1328 nandc_set_reg(chip, NAND_DEV_CMD_VLD_RESTORE, nandc->vld); in nandc_param()
1333 if (!nandc->props->qpic_v2) { in nandc_param()
1338 nandc->buf_count = 512; in nandc_param()
1339 memset(nandc->data_buffer, 0xff, nandc->buf_count); in nandc_param()
1343 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, in nandc_param()
1344 nandc->buf_count, 0); in nandc_param()
1347 if (!nandc->props->qpic_v2) { in nandc_param()
1358 struct nand_chip *chip = &host->chip; in erase_block()
1366 host->cfg0_raw & ~(7 << CW_PER_PAGE)); in erase_block()
1367 nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw); in erase_block()
1369 nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus); in erase_block()
1370 nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus); in erase_block()
1387 struct nand_chip *chip = &host->chip; in read_id()
1390 if (column == -1) in read_id()
1397 nandc->props->is_bam ? 0 : DM_EN); in read_id()
1411 struct nand_chip *chip = &host->chip; in reset()
1430 struct bam_transaction *bam_txn = nandc->bam_txn; in submit_descs()
1433 if (nandc->props->is_bam) { in submit_descs()
1434 if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) { in submit_descs()
1435 r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0); in submit_descs()
1440 if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) { in submit_descs()
1441 r = prepare_bam_async_desc(nandc, nandc->tx_chan, in submit_descs()
1447 if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) { in submit_descs()
1448 r = prepare_bam_async_desc(nandc, nandc->cmd_chan, in submit_descs()
1455 list_for_each_entry(desc, &nandc->desc_list, node) in submit_descs()
1456 cookie = dmaengine_submit(desc->dma_desc); in submit_descs()
1458 if (nandc->props->is_bam) { in submit_descs()
1459 bam_txn->last_cmd_desc->callback = qpic_bam_dma_done; in submit_descs()
1460 bam_txn->last_cmd_desc->callback_param = bam_txn; in submit_descs()
1461 if (bam_txn->last_data_desc) { in submit_descs()
1462 bam_txn->last_data_desc->callback = qpic_bam_dma_done; in submit_descs()
1463 bam_txn->last_data_desc->callback_param = bam_txn; in submit_descs()
1464 bam_txn->wait_second_completion = true; in submit_descs()
1467 dma_async_issue_pending(nandc->tx_chan); in submit_descs()
1468 dma_async_issue_pending(nandc->rx_chan); in submit_descs()
1469 dma_async_issue_pending(nandc->cmd_chan); in submit_descs()
1471 if (!wait_for_completion_timeout(&bam_txn->txn_done, in submit_descs()
1473 return -ETIMEDOUT; in submit_descs()
1475 if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE) in submit_descs()
1476 return -ETIMEDOUT; in submit_descs()
1486 list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { in free_descs()
1487 list_del(&desc->node); in free_descs()
1489 if (nandc->props->is_bam) in free_descs()
1490 dma_unmap_sg(nandc->dev, desc->bam_sgl, in free_descs()
1491 desc->sgl_cnt, desc->dir); in free_descs()
1493 dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1, in free_descs()
1494 desc->dir); in free_descs()
1500 /* reset the register read buffer for next NAND operation */
1503 nandc->reg_read_pos = 0; in clear_read_regs()
1509 struct nand_chip *chip = &host->chip; in pre_command()
1512 nandc->buf_count = 0; in pre_command()
1513 nandc->buf_start = 0; in pre_command()
1514 host->use_ecc = false; in pre_command()
1515 host->last_command = command; in pre_command()
1531 struct nand_chip *chip = &host->chip; in parse_erase_write_errors()
1533 struct nand_ecc_ctrl *ecc = &chip->ecc; in parse_erase_write_errors()
1537 num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1; in parse_erase_write_errors()
1541 u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]); in parse_erase_write_errors()
1544 host->status &= ~NAND_STATUS_WP; in parse_erase_write_errors()
1546 if (flash_status & FS_OP_ERR || (i == (num_cw - 1) && in parse_erase_write_errors()
1549 host->status |= NAND_STATUS_FAIL; in parse_erase_write_errors()
1555 struct nand_chip *chip = &host->chip; in post_command()
1561 memcpy(nandc->data_buffer, nandc->reg_read_buf, in post_command()
1562 nandc->buf_count); in post_command()
1574 * Implements chip->legacy.cmdfunc. It's only used for a limited set of
1583 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_command()
1597 nandc->buf_count = 4; in qcom_nandc_command()
1616 host->use_ecc = true; in qcom_nandc_command()
1618 update_rw_regs(host, ecc->steps, true, 0); in qcom_nandc_command()
1634 dev_err(nandc->dev, "failure executing command %d\n", in qcom_nandc_command()
1643 dev_err(nandc->dev, in qcom_nandc_command()
1710 struct nand_chip *chip = &host->chip; in check_flash_errors()
1717 u32 flash = le32_to_cpu(nandc->reg_read_buf[i]); in check_flash_errors()
1720 return -EIO; in check_flash_errors()
1733 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_cw_raw()
1739 host->use_ecc = false; in qcom_nandc_read_cw_raw()
1741 if (nandc->props->qpic_v2) in qcom_nandc_read_cw_raw()
1742 raw_cw = ecc->steps - 1; in qcom_nandc_read_cw_raw()
1745 set_address(host, host->cw_size * cw, page); in qcom_nandc_read_cw_raw()
1749 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_read_cw_raw()
1750 oob_size1 = host->bbm_size; in qcom_nandc_read_cw_raw()
1752 if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { in qcom_nandc_read_cw_raw()
1753 data_size2 = ecc->size - data_size1 - in qcom_nandc_read_cw_raw()
1754 ((ecc->steps - 1) * 4); in qcom_nandc_read_cw_raw()
1755 oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + in qcom_nandc_read_cw_raw()
1756 host->spare_bytes; in qcom_nandc_read_cw_raw()
1758 data_size2 = host->cw_data - data_size1; in qcom_nandc_read_cw_raw()
1759 oob_size2 = host->ecc_bytes_hw + host->spare_bytes; in qcom_nandc_read_cw_raw()
1762 if (nandc->props->is_bam) { in qcom_nandc_read_cw_raw()
1791 dev_err(nandc->dev, "failure to read raw cw %d\n", cw); in qcom_nandc_read_cw_raw()
1802 * equal to the ecc->strength for each CW.
1805 * top-level API can be called with only data buf or OOB buf so use
1806 * chip->data_buf if data buf is null and chip->oob_poi if oob buf
1818 struct nand_chip *chip = &host->chip; in check_for_erased_page()
1820 struct nand_ecc_ctrl *ecc = &chip->ecc; in check_for_erased_page()
1829 oob_buf = chip->oob_poi; in check_for_erased_page()
1832 for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { in check_for_erased_page()
1833 if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { in check_for_erased_page()
1834 data_size = ecc->size - ((ecc->steps - 1) * 4); in check_for_erased_page()
1835 oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; in check_for_erased_page()
1837 data_size = host->cw_data; in check_for_erased_page()
1838 oob_size = host->ecc_bytes_hw; in check_for_erased_page()
1842 cw_data_buf = data_buf + (cw * host->cw_data); in check_for_erased_page()
1843 cw_oob_buf = oob_buf + (cw * ecc->bytes); in check_for_erased_page()
1852 * as not-erased by HW because of a few bitflips in check_for_erased_page()
1855 cw_oob_buf + host->bbm_size, in check_for_erased_page()
1857 0, ecc->strength); in check_for_erased_page()
1859 mtd->ecc_stats.failed++; in check_for_erased_page()
1861 mtd->ecc_stats.corrected += ret; in check_for_erased_page()
1871 * errors. this is equivalent to what 'ecc->correct()' would do.
1876 struct nand_chip *chip = &host->chip; in parse_read_errors()
1879 struct nand_ecc_ctrl *ecc = &chip->ecc; in parse_read_errors()
1886 buf = (struct read_stats *)nandc->reg_read_buf; in parse_read_errors()
1889 for (i = 0; i < ecc->steps; i++, buf++) { in parse_read_errors()
1894 data_len = ecc->size - ((ecc->steps - 1) << 2); in parse_read_errors()
1895 oob_len = ecc->steps << 2; in parse_read_errors()
1897 data_len = host->cw_data; in parse_read_errors()
1901 flash = le32_to_cpu(buf->flash); in parse_read_errors()
1902 buffer = le32_to_cpu(buf->buffer); in parse_read_errors()
1903 erased_cw = le32_to_cpu(buf->erased_cw); in parse_read_errors()
1918 if (host->bch_enabled) { in parse_read_errors()
1951 mtd->ecc_stats.corrected += stat; in parse_read_errors()
1958 oob_buf += oob_len + ecc->bytes; in parse_read_errors()
1962 return -EIO; in parse_read_errors()
1973 * helper to perform the actual page read operation, used by ecc->read_page(),
1974 * ecc->read_oob()
1979 struct nand_chip *chip = &host->chip; in read_page_ecc()
1981 struct nand_ecc_ctrl *ecc = &chip->ecc; in read_page_ecc()
1988 for (i = 0; i < ecc->steps; i++) { in read_page_ecc()
1991 if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { in read_page_ecc()
1992 data_size = ecc->size - ((ecc->steps - 1) << 2); in read_page_ecc()
1993 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + in read_page_ecc()
1994 host->spare_bytes; in read_page_ecc()
1996 data_size = host->cw_data; in read_page_ecc()
1997 oob_size = host->ecc_bytes_hw + host->spare_bytes; in read_page_ecc()
2000 if (nandc->props->is_bam) { in read_page_ecc()
2029 for (j = 0; j < host->bbm_size; j++) in read_page_ecc()
2046 dev_err(nandc->dev, "failure to read page/oob\n"); in read_page_ecc()
2059 struct nand_chip *chip = &host->chip; in copy_last_cw()
2061 struct nand_ecc_ctrl *ecc = &chip->ecc; in copy_last_cw()
2067 size = host->use_ecc ? host->cw_data : host->cw_size; in copy_last_cw()
2070 memset(nandc->data_buffer, 0xff, size); in copy_last_cw()
2072 set_address(host, host->cw_size * (ecc->steps - 1), page); in copy_last_cw()
2073 update_rw_regs(host, 1, true, ecc->steps - 1); in copy_last_cw()
2075 config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1); in copy_last_cw()
2077 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0); in copy_last_cw()
2081 dev_err(nandc->dev, "failed to copy last codeword\n"); in copy_last_cw()
2095 * Since the frequent access will be to the non-boot partitions like rootfs, in qcom_nandc_is_boot_partition()
2103 boot_partition = &host->boot_partitions[host->nr_boot_partitions - 1]; in qcom_nandc_is_boot_partition()
2104 start = boot_partition->page_offset; in qcom_nandc_is_boot_partition()
2105 end = start + boot_partition->page_size; in qcom_nandc_is_boot_partition()
2115 /* Check the other boot partitions starting from the second-last partition */ in qcom_nandc_is_boot_partition()
2116 for (i = host->nr_boot_partitions - 2; i >= 0; i--) { in qcom_nandc_is_boot_partition()
2117 boot_partition = &host->boot_partitions[i]; in qcom_nandc_is_boot_partition()
2118 start = boot_partition->page_offset; in qcom_nandc_is_boot_partition()
2119 end = start + boot_partition->page_size; in qcom_nandc_is_boot_partition()
2133 if (codeword_fixup == host->codeword_fixup) in qcom_nandc_codeword_fixup()
2136 host->codeword_fixup = codeword_fixup; in qcom_nandc_codeword_fixup()
2138 host->cw_data = codeword_fixup ? 512 : 516; in qcom_nandc_codeword_fixup()
2139 host->spare_bytes = host->cw_size - host->ecc_bytes_hw - in qcom_nandc_codeword_fixup()
2140 host->bbm_size - host->cw_data; in qcom_nandc_codeword_fixup()
2142 host->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK); in qcom_nandc_codeword_fixup()
2143 host->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES | in qcom_nandc_codeword_fixup()
2144 host->cw_data << UD_SIZE_BYTES; in qcom_nandc_codeword_fixup()
2146 host->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK; in qcom_nandc_codeword_fixup()
2147 host->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES; in qcom_nandc_codeword_fixup()
2148 host->ecc_buf_cfg = (host->cw_data - 1) << NUM_STEPS; in qcom_nandc_codeword_fixup()
2151 /* implements ecc->read_page() */
2159 if (host->nr_boot_partitions) in qcom_nandc_read_page()
2164 oob_buf = oob_required ? chip->oob_poi : NULL; in qcom_nandc_read_page()
2171 /* implements ecc->read_page_raw() */
2177 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_page_raw()
2179 u8 *data_buf = buf, *oob_buf = chip->oob_poi; in qcom_nandc_read_page_raw()
2181 if (host->nr_boot_partitions) in qcom_nandc_read_page_raw()
2184 for (cw = 0; cw < ecc->steps; cw++) { in qcom_nandc_read_page_raw()
2190 data_buf += host->cw_data; in qcom_nandc_read_page_raw()
2191 oob_buf += ecc->bytes; in qcom_nandc_read_page_raw()
2197 /* implements ecc->read_oob() */
2202 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_oob()
2204 if (host->nr_boot_partitions) in qcom_nandc_read_oob()
2210 host->use_ecc = true; in qcom_nandc_read_oob()
2212 update_rw_regs(host, ecc->steps, true, 0); in qcom_nandc_read_oob()
2214 return read_page_ecc(host, NULL, chip->oob_poi, page); in qcom_nandc_read_oob()
2217 /* implements ecc->write_page() */
2223 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_page()
2227 if (host->nr_boot_partitions) in qcom_nandc_write_page()
2236 oob_buf = chip->oob_poi; in qcom_nandc_write_page()
2238 host->use_ecc = true; in qcom_nandc_write_page()
2239 update_rw_regs(host, ecc->steps, false, 0); in qcom_nandc_write_page()
2242 for (i = 0; i < ecc->steps; i++) { in qcom_nandc_write_page()
2245 if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { in qcom_nandc_write_page()
2246 data_size = ecc->size - ((ecc->steps - 1) << 2); in qcom_nandc_write_page()
2247 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + in qcom_nandc_write_page()
2248 host->spare_bytes; in qcom_nandc_write_page()
2250 data_size = host->cw_data; in qcom_nandc_write_page()
2251 oob_size = ecc->bytes; in qcom_nandc_write_page()
2256 i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0); in qcom_nandc_write_page()
2260 * to oob for the first n - 1 codewords since these oob regions in qcom_nandc_write_page()
2266 oob_buf += host->bbm_size; in qcom_nandc_write_page()
2280 dev_err(nandc->dev, "failure to write page\n"); in qcom_nandc_write_page()
2290 /* implements ecc->write_page_raw() */
2298 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_page_raw()
2302 if (host->nr_boot_partitions) in qcom_nandc_write_page_raw()
2310 oob_buf = chip->oob_poi; in qcom_nandc_write_page_raw()
2312 host->use_ecc = false; in qcom_nandc_write_page_raw()
2313 update_rw_regs(host, ecc->steps, false, 0); in qcom_nandc_write_page_raw()
2316 for (i = 0; i < ecc->steps; i++) { in qcom_nandc_write_page_raw()
2320 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_write_page_raw()
2321 oob_size1 = host->bbm_size; in qcom_nandc_write_page_raw()
2323 if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { in qcom_nandc_write_page_raw()
2324 data_size2 = ecc->size - data_size1 - in qcom_nandc_write_page_raw()
2325 ((ecc->steps - 1) << 2); in qcom_nandc_write_page_raw()
2326 oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + in qcom_nandc_write_page_raw()
2327 host->spare_bytes; in qcom_nandc_write_page_raw()
2329 data_size2 = host->cw_data - data_size1; in qcom_nandc_write_page_raw()
2330 oob_size2 = host->ecc_bytes_hw + host->spare_bytes; in qcom_nandc_write_page_raw()
2356 dev_err(nandc->dev, "failure to write raw page\n"); in qcom_nandc_write_page_raw()
2367 * implements ecc->write_oob()
2369 * the NAND controller cannot write only data or only OOB within a codeword
2371 * chip->oob_poi, and pad the data area with OxFF before writing.
2378 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_oob()
2379 u8 *oob = chip->oob_poi; in qcom_nandc_write_oob()
2383 if (host->nr_boot_partitions) in qcom_nandc_write_oob()
2386 host->use_ecc = true; in qcom_nandc_write_oob()
2390 data_size = ecc->size - ((ecc->steps - 1) << 2); in qcom_nandc_write_oob()
2391 oob_size = mtd->oobavail; in qcom_nandc_write_oob()
2393 memset(nandc->data_buffer, 0xff, host->cw_data); in qcom_nandc_write_oob()
2395 mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob, in qcom_nandc_write_oob()
2396 0, mtd->oobavail); in qcom_nandc_write_oob()
2398 set_address(host, host->cw_size * (ecc->steps - 1), page); in qcom_nandc_write_oob()
2403 nandc->data_buffer, data_size + oob_size, 0); in qcom_nandc_write_oob()
2411 dev_err(nandc->dev, "failure to write oob\n"); in qcom_nandc_write_oob()
2412 return -EIO; in qcom_nandc_write_oob()
2423 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_block_bad()
2426 page = (int)(ofs >> chip->page_shift) & chip->pagemask; in qcom_nandc_block_bad()
2434 host->use_ecc = false; in qcom_nandc_block_bad()
2442 dev_warn(nandc->dev, "error when trying to read BBM\n"); in qcom_nandc_block_bad()
2446 bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_block_bad()
2448 bad = nandc->data_buffer[bbpos] != 0xff; in qcom_nandc_block_bad()
2450 if (chip->options & NAND_BUSWIDTH_16) in qcom_nandc_block_bad()
2451 bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff); in qcom_nandc_block_bad()
2460 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_block_markbad()
2471 memset(nandc->data_buffer, 0x00, host->cw_size); in qcom_nandc_block_markbad()
2473 page = (int)(ofs >> chip->page_shift) & chip->pagemask; in qcom_nandc_block_markbad()
2476 host->use_ecc = false; in qcom_nandc_block_markbad()
2477 set_address(host, host->cw_size * (ecc->steps - 1), page); in qcom_nandc_block_markbad()
2478 update_rw_regs(host, 1, false, ecc->steps - 1); in qcom_nandc_block_markbad()
2482 nandc->data_buffer, host->cw_size, 0); in qcom_nandc_block_markbad()
2490 dev_err(nandc->dev, "failure to update BBM\n"); in qcom_nandc_block_markbad()
2491 return -EIO; in qcom_nandc_block_markbad()
2498 * the three functions below implement chip->legacy.read_byte(),
2499 * chip->legacy.read_buf() and chip->legacy.write_buf() respectively. these
2507 u8 *buf = nandc->data_buffer; in qcom_nandc_read_byte()
2510 if (host->last_command == NAND_CMD_STATUS) { in qcom_nandc_read_byte()
2511 ret = host->status; in qcom_nandc_read_byte()
2513 host->status = NAND_STATUS_READY | NAND_STATUS_WP; in qcom_nandc_read_byte()
2518 if (nandc->buf_start < nandc->buf_count) in qcom_nandc_read_byte()
2519 ret = buf[nandc->buf_start++]; in qcom_nandc_read_byte()
2527 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_read_buf()
2529 memcpy(buf, nandc->data_buffer + nandc->buf_start, real_len); in qcom_nandc_read_buf()
2530 nandc->buf_start += real_len; in qcom_nandc_read_buf()
2537 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_write_buf()
2539 memcpy(nandc->data_buffer + nandc->buf_start, buf, real_len); in qcom_nandc_write_buf()
2541 nandc->buf_start += real_len; in qcom_nandc_write_buf()
2552 dev_warn(nandc->dev, "invalid chip select\n"); in qcom_nandc_select_chip()
2556 * NAND controller page layout info
2560 * |----------------------| |---------------------------------|
2563 * | (516) xx.......yy| | (516-n*4) **(n*4)**xx.......yy|
2565 * |----------------------| |---------------------------------|
2566 * codeword 1,2..n-1 codeword n
2567 * <---(528/532 Bytes)--> <-------(528/532 Bytes)--------->
2579 * the qcom nand controller operates at a sub page/codeword level. each
2583 * the first n - 1 codewords contains 516 bytes of user data, the remaining
2594 * |------------------------------| |---------------------------------------|
2599 * |------------------------------| |---------------------------------------|
2600 * codeword 1,2..n-1 codeword n
2601 * <-------(528/532 Bytes)------> <-----------(528/532 Bytes)----------->
2612 * width) is now accessible. For the first n - 1 codewords, these are dummy Bad
2618 * |-----------| |--------------------|
2623 * |-----------| |--------------------|
2624 * first n - 1 nth OOB region
2637 * dummy/real bad block bytes are grouped as ecc bytes (i.e, ecc->bytes is
2645 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_ooblayout_ecc()
2648 return -ERANGE; in qcom_nand_ooblayout_ecc()
2651 oobregion->length = (ecc->bytes * (ecc->steps - 1)) + in qcom_nand_ooblayout_ecc()
2652 host->bbm_size; in qcom_nand_ooblayout_ecc()
2653 oobregion->offset = 0; in qcom_nand_ooblayout_ecc()
2655 oobregion->length = host->ecc_bytes_hw + host->spare_bytes; in qcom_nand_ooblayout_ecc()
2656 oobregion->offset = mtd->oobsize - oobregion->length; in qcom_nand_ooblayout_ecc()
2667 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_ooblayout_free()
2670 return -ERANGE; in qcom_nand_ooblayout_free()
2672 oobregion->length = ecc->steps * 4; in qcom_nand_ooblayout_free()
2673 oobregion->offset = ((ecc->steps - 1) * ecc->bytes) + host->bbm_size; in qcom_nand_ooblayout_free()
2695 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_attach_chip()
2702 ecc->size = NANDC_STEP_SIZE; in qcom_nand_attach_chip()
2703 wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false; in qcom_nand_attach_chip()
2704 cwperpage = mtd->writesize / NANDC_STEP_SIZE; in qcom_nand_attach_chip()
2711 mtd->oobsize - (cwperpage * 4)); in qcom_nand_attach_chip()
2713 dev_err(nandc->dev, "No valid ECC settings possible\n"); in qcom_nand_attach_chip()
2717 if (ecc->strength >= 8) { in qcom_nand_attach_chip()
2719 host->bch_enabled = true; in qcom_nand_attach_chip()
2723 host->ecc_bytes_hw = 14; in qcom_nand_attach_chip()
2724 host->spare_bytes = 0; in qcom_nand_attach_chip()
2725 host->bbm_size = 2; in qcom_nand_attach_chip()
2727 host->ecc_bytes_hw = 13; in qcom_nand_attach_chip()
2728 host->spare_bytes = 2; in qcom_nand_attach_chip()
2729 host->bbm_size = 1; in qcom_nand_attach_chip()
2737 if (nandc->props->ecc_modes & ECC_BCH_4BIT) { in qcom_nand_attach_chip()
2739 host->bch_enabled = true; in qcom_nand_attach_chip()
2743 host->ecc_bytes_hw = 8; in qcom_nand_attach_chip()
2744 host->spare_bytes = 2; in qcom_nand_attach_chip()
2745 host->bbm_size = 2; in qcom_nand_attach_chip()
2747 host->ecc_bytes_hw = 7; in qcom_nand_attach_chip()
2748 host->spare_bytes = 4; in qcom_nand_attach_chip()
2749 host->bbm_size = 1; in qcom_nand_attach_chip()
2753 host->ecc_bytes_hw = 10; in qcom_nand_attach_chip()
2756 host->spare_bytes = 0; in qcom_nand_attach_chip()
2757 host->bbm_size = 2; in qcom_nand_attach_chip()
2759 host->spare_bytes = 1; in qcom_nand_attach_chip()
2760 host->bbm_size = 1; in qcom_nand_attach_chip()
2766 * we consider ecc->bytes as the sum of all the non-data content in a in qcom_nand_attach_chip()
2771 ecc->bytes = host->ecc_bytes_hw + host->spare_bytes + host->bbm_size; in qcom_nand_attach_chip()
2773 ecc->read_page = qcom_nandc_read_page; in qcom_nand_attach_chip()
2774 ecc->read_page_raw = qcom_nandc_read_page_raw; in qcom_nand_attach_chip()
2775 ecc->read_oob = qcom_nandc_read_oob; in qcom_nand_attach_chip()
2776 ecc->write_page = qcom_nandc_write_page; in qcom_nand_attach_chip()
2777 ecc->write_page_raw = qcom_nandc_write_page_raw; in qcom_nand_attach_chip()
2778 ecc->write_oob = qcom_nandc_write_oob; in qcom_nand_attach_chip()
2780 ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in qcom_nand_attach_chip()
2784 if (nandc->props->is_bam) in qcom_nand_attach_chip()
2787 nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage, in qcom_nand_attach_chip()
2791 if (nandc->props->is_bam) { in qcom_nand_attach_chip()
2792 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nand_attach_chip()
2793 if (!nandc->bam_txn) { in qcom_nand_attach_chip()
2794 dev_err(nandc->dev, in qcom_nand_attach_chip()
2796 return -ENOMEM; in qcom_nand_attach_chip()
2805 host->cw_data = 516; in qcom_nand_attach_chip()
2811 host->cw_size = host->cw_data + ecc->bytes; in qcom_nand_attach_chip()
2812 bad_block_byte = mtd->writesize - host->cw_size * (cwperpage - 1) + 1; in qcom_nand_attach_chip()
2814 host->cfg0 = (cwperpage - 1) << CW_PER_PAGE in qcom_nand_attach_chip()
2815 | host->cw_data << UD_SIZE_BYTES in qcom_nand_attach_chip()
2818 | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS in qcom_nand_attach_chip()
2821 | host->spare_bytes << SPARE_SIZE_BYTES; in qcom_nand_attach_chip()
2823 host->cfg1 = 7 << NAND_RECOVERY_CYCLES in qcom_nand_attach_chip()
2829 | host->bch_enabled << ENABLE_BCH_ECC; in qcom_nand_attach_chip()
2831 host->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE in qcom_nand_attach_chip()
2832 | host->cw_size << UD_SIZE_BYTES in qcom_nand_attach_chip()
2836 host->cfg1_raw = 7 << NAND_RECOVERY_CYCLES in qcom_nand_attach_chip()
2844 host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE in qcom_nand_attach_chip()
2846 | host->cw_data << ECC_NUM_DATA_BYTES in qcom_nand_attach_chip()
2849 | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH; in qcom_nand_attach_chip()
2851 if (!nandc->props->qpic_v2) in qcom_nand_attach_chip()
2852 host->ecc_buf_cfg = 0x203 << NUM_STEPS; in qcom_nand_attach_chip()
2854 host->clrflashstatus = FS_READY_BSY_N; in qcom_nand_attach_chip()
2855 host->clrreadstatus = 0xc0; in qcom_nand_attach_chip()
2856 nandc->regs->erased_cw_detect_cfg_clr = in qcom_nand_attach_chip()
2858 nandc->regs->erased_cw_detect_cfg_set = in qcom_nand_attach_chip()
2861 dev_dbg(nandc->dev, in qcom_nand_attach_chip()
2863 host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg, in qcom_nand_attach_chip()
2864 host->cw_size, host->cw_data, ecc->strength, ecc->bytes, in qcom_nand_attach_chip()
2876 if (nandc->props->is_bam) { in qcom_nandc_unalloc()
2877 if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) in qcom_nandc_unalloc()
2878 dma_unmap_single(nandc->dev, nandc->reg_read_dma, in qcom_nandc_unalloc()
2880 sizeof(*nandc->reg_read_buf), in qcom_nandc_unalloc()
2883 if (nandc->tx_chan) in qcom_nandc_unalloc()
2884 dma_release_channel(nandc->tx_chan); in qcom_nandc_unalloc()
2886 if (nandc->rx_chan) in qcom_nandc_unalloc()
2887 dma_release_channel(nandc->rx_chan); in qcom_nandc_unalloc()
2889 if (nandc->cmd_chan) in qcom_nandc_unalloc()
2890 dma_release_channel(nandc->cmd_chan); in qcom_nandc_unalloc()
2892 if (nandc->chan) in qcom_nandc_unalloc()
2893 dma_release_channel(nandc->chan); in qcom_nandc_unalloc()
2901 ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32)); in qcom_nandc_alloc()
2903 dev_err(nandc->dev, "failed to set DMA mask\n"); in qcom_nandc_alloc()
2909 * data like ID and status, and preforming read-copy-write operations in qcom_nandc_alloc()
2911 * size of a codeword for our nand controller in qcom_nandc_alloc()
2913 nandc->buf_size = 532; in qcom_nandc_alloc()
2915 nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, in qcom_nandc_alloc()
2917 if (!nandc->data_buffer) in qcom_nandc_alloc()
2918 return -ENOMEM; in qcom_nandc_alloc()
2920 nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), in qcom_nandc_alloc()
2922 if (!nandc->regs) in qcom_nandc_alloc()
2923 return -ENOMEM; in qcom_nandc_alloc()
2925 nandc->reg_read_buf = devm_kcalloc(nandc->dev, in qcom_nandc_alloc()
2926 MAX_REG_RD, sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2928 if (!nandc->reg_read_buf) in qcom_nandc_alloc()
2929 return -ENOMEM; in qcom_nandc_alloc()
2931 if (nandc->props->is_bam) { in qcom_nandc_alloc()
2932 nandc->reg_read_dma = in qcom_nandc_alloc()
2933 dma_map_single(nandc->dev, nandc->reg_read_buf, in qcom_nandc_alloc()
2935 sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2937 if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) { in qcom_nandc_alloc()
2938 dev_err(nandc->dev, "failed to DMA MAP reg buffer\n"); in qcom_nandc_alloc()
2939 return -EIO; in qcom_nandc_alloc()
2942 nandc->tx_chan = dma_request_chan(nandc->dev, "tx"); in qcom_nandc_alloc()
2943 if (IS_ERR(nandc->tx_chan)) { in qcom_nandc_alloc()
2944 ret = PTR_ERR(nandc->tx_chan); in qcom_nandc_alloc()
2945 nandc->tx_chan = NULL; in qcom_nandc_alloc()
2946 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2951 nandc->rx_chan = dma_request_chan(nandc->dev, "rx"); in qcom_nandc_alloc()
2952 if (IS_ERR(nandc->rx_chan)) { in qcom_nandc_alloc()
2953 ret = PTR_ERR(nandc->rx_chan); in qcom_nandc_alloc()
2954 nandc->rx_chan = NULL; in qcom_nandc_alloc()
2955 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2960 nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd"); in qcom_nandc_alloc()
2961 if (IS_ERR(nandc->cmd_chan)) { in qcom_nandc_alloc()
2962 ret = PTR_ERR(nandc->cmd_chan); in qcom_nandc_alloc()
2963 nandc->cmd_chan = NULL; in qcom_nandc_alloc()
2964 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2975 nandc->max_cwperpage = 1; in qcom_nandc_alloc()
2976 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nandc_alloc()
2977 if (!nandc->bam_txn) { in qcom_nandc_alloc()
2978 dev_err(nandc->dev, in qcom_nandc_alloc()
2980 ret = -ENOMEM; in qcom_nandc_alloc()
2984 nandc->chan = dma_request_chan(nandc->dev, "rxtx"); in qcom_nandc_alloc()
2985 if (IS_ERR(nandc->chan)) { in qcom_nandc_alloc()
2986 ret = PTR_ERR(nandc->chan); in qcom_nandc_alloc()
2987 nandc->chan = NULL; in qcom_nandc_alloc()
2988 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2994 INIT_LIST_HEAD(&nandc->desc_list); in qcom_nandc_alloc()
2995 INIT_LIST_HEAD(&nandc->host_list); in qcom_nandc_alloc()
2997 nand_controller_init(&nandc->controller); in qcom_nandc_alloc()
2998 nandc->controller.ops = &qcom_nandc_ops; in qcom_nandc_alloc()
3006 /* one time setup of a few nand controller registers */
3012 if (!nandc->props->is_qpic) in qcom_nandc_setup()
3015 if (!nandc->props->qpic_v2) in qcom_nandc_setup()
3020 if (nandc->props->is_bam) { in qcom_nandc_setup()
3037 if (!nandc->props->qpic_v2) { in qcom_nandc_setup()
3038 nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1)); in qcom_nandc_setup()
3039 nandc->vld = NAND_DEV_CMD_VLD_VAL; in qcom_nandc_setup()
3051 struct nand_chip *chip = &host->chip; in qcom_nand_host_parse_boot_partitions()
3054 struct device *dev = nandc->dev; in qcom_nand_host_parse_boot_partitions()
3057 if (!of_find_property(dn, "qcom,boot-partitions", NULL)) in qcom_nand_host_parse_boot_partitions()
3060 partitions_count = of_property_count_u32_elems(dn, "qcom,boot-partitions"); in qcom_nand_host_parse_boot_partitions()
3063 return partitions_count ? partitions_count : -EINVAL; in qcom_nand_host_parse_boot_partitions()
3066 host->nr_boot_partitions = partitions_count / 2; in qcom_nand_host_parse_boot_partitions()
3067 host->boot_partitions = devm_kcalloc(dev, host->nr_boot_partitions, in qcom_nand_host_parse_boot_partitions()
3068 sizeof(*host->boot_partitions), GFP_KERNEL); in qcom_nand_host_parse_boot_partitions()
3069 if (!host->boot_partitions) { in qcom_nand_host_parse_boot_partitions()
3070 host->nr_boot_partitions = 0; in qcom_nand_host_parse_boot_partitions()
3071 return -ENOMEM; in qcom_nand_host_parse_boot_partitions()
3074 for (i = 0, j = 0; i < host->nr_boot_partitions; i++, j += 2) { in qcom_nand_host_parse_boot_partitions()
3075 boot_partition = &host->boot_partitions[i]; in qcom_nand_host_parse_boot_partitions()
3077 ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j, in qcom_nand_host_parse_boot_partitions()
3078 &boot_partition->page_offset); in qcom_nand_host_parse_boot_partitions()
3081 host->nr_boot_partitions = 0; in qcom_nand_host_parse_boot_partitions()
3085 if (boot_partition->page_offset % mtd->writesize) { in qcom_nand_host_parse_boot_partitions()
3088 host->nr_boot_partitions = 0; in qcom_nand_host_parse_boot_partitions()
3089 return -EINVAL; in qcom_nand_host_parse_boot_partitions()
3091 /* Convert offset to nand pages */ in qcom_nand_host_parse_boot_partitions()
3092 boot_partition->page_offset /= mtd->writesize; in qcom_nand_host_parse_boot_partitions()
3094 ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j + 1, in qcom_nand_host_parse_boot_partitions()
3095 &boot_partition->page_size); in qcom_nand_host_parse_boot_partitions()
3098 host->nr_boot_partitions = 0; in qcom_nand_host_parse_boot_partitions()
3102 if (boot_partition->page_size % mtd->writesize) { in qcom_nand_host_parse_boot_partitions()
3105 host->nr_boot_partitions = 0; in qcom_nand_host_parse_boot_partitions()
3106 return -EINVAL; in qcom_nand_host_parse_boot_partitions()
3108 /* Convert size to nand pages */ in qcom_nand_host_parse_boot_partitions()
3109 boot_partition->page_size /= mtd->writesize; in qcom_nand_host_parse_boot_partitions()
3119 struct nand_chip *chip = &host->chip; in qcom_nand_host_init_and_register()
3121 struct device *dev = nandc->dev; in qcom_nand_host_init_and_register()
3124 ret = of_property_read_u32(dn, "reg", &host->cs); in qcom_nand_host_init_and_register()
3126 dev_err(dev, "can't get chip-select\n"); in qcom_nand_host_init_and_register()
3127 return -ENXIO; in qcom_nand_host_init_and_register()
3131 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "qcom_nand.%d", host->cs); in qcom_nand_host_init_and_register()
3132 if (!mtd->name) in qcom_nand_host_init_and_register()
3133 return -ENOMEM; in qcom_nand_host_init_and_register()
3135 mtd->owner = THIS_MODULE; in qcom_nand_host_init_and_register()
3136 mtd->dev.parent = dev; in qcom_nand_host_init_and_register()
3138 chip->legacy.cmdfunc = qcom_nandc_command; in qcom_nand_host_init_and_register()
3139 chip->legacy.select_chip = qcom_nandc_select_chip; in qcom_nand_host_init_and_register()
3140 chip->legacy.read_byte = qcom_nandc_read_byte; in qcom_nand_host_init_and_register()
3141 chip->legacy.read_buf = qcom_nandc_read_buf; in qcom_nand_host_init_and_register()
3142 chip->legacy.write_buf = qcom_nandc_write_buf; in qcom_nand_host_init_and_register()
3143 chip->legacy.set_features = nand_get_set_features_notsupp; in qcom_nand_host_init_and_register()
3144 chip->legacy.get_features = nand_get_set_features_notsupp; in qcom_nand_host_init_and_register()
3149 * helpers don't allow us to read BB from a nand chip with ECC in qcom_nand_host_init_and_register()
3154 chip->legacy.block_bad = qcom_nandc_block_bad; in qcom_nand_host_init_and_register()
3155 chip->legacy.block_markbad = qcom_nandc_block_markbad; in qcom_nand_host_init_and_register()
3157 chip->controller = &nandc->controller; in qcom_nand_host_init_and_register()
3158 chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA | in qcom_nand_host_init_and_register()
3162 host->status = NAND_STATUS_READY | NAND_STATUS_WP; in qcom_nand_host_init_and_register()
3172 if (nandc->props->use_codeword_fixup) { in qcom_nand_host_init_and_register()
3187 struct device *dev = nandc->dev; in qcom_probe_nand_devices()
3188 struct device_node *dn = dev->of_node, *child; in qcom_probe_nand_devices()
3190 int ret = -ENODEV; in qcom_probe_nand_devices()
3196 return -ENOMEM; in qcom_probe_nand_devices()
3205 list_add_tail(&host->node, &nandc->host_list); in qcom_probe_nand_devices()
3215 struct device_node *np = nandc->dev->of_node; in qcom_nandc_parse_dt()
3218 if (!nandc->props->is_bam) { in qcom_nandc_parse_dt()
3219 ret = of_property_read_u32(np, "qcom,cmd-crci", in qcom_nandc_parse_dt()
3220 &nandc->cmd_crci); in qcom_nandc_parse_dt()
3222 dev_err(nandc->dev, "command CRCI unspecified\n"); in qcom_nandc_parse_dt()
3226 ret = of_property_read_u32(np, "qcom,data-crci", in qcom_nandc_parse_dt()
3227 &nandc->data_crci); in qcom_nandc_parse_dt()
3229 dev_err(nandc->dev, "data CRCI unspecified\n"); in qcom_nandc_parse_dt()
3241 struct device *dev = &pdev->dev; in qcom_nandc_probe()
3245 nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL); in qcom_nandc_probe()
3247 return -ENOMEM; in qcom_nandc_probe()
3250 nandc->dev = dev; in qcom_nandc_probe()
3254 dev_err(&pdev->dev, "failed to get device data\n"); in qcom_nandc_probe()
3255 return -ENODEV; in qcom_nandc_probe()
3258 nandc->props = dev_data; in qcom_nandc_probe()
3260 nandc->core_clk = devm_clk_get(dev, "core"); in qcom_nandc_probe()
3261 if (IS_ERR(nandc->core_clk)) in qcom_nandc_probe()
3262 return PTR_ERR(nandc->core_clk); in qcom_nandc_probe()
3264 nandc->aon_clk = devm_clk_get(dev, "aon"); in qcom_nandc_probe()
3265 if (IS_ERR(nandc->aon_clk)) in qcom_nandc_probe()
3266 return PTR_ERR(nandc->aon_clk); in qcom_nandc_probe()
3273 nandc->base = devm_ioremap_resource(dev, res); in qcom_nandc_probe()
3274 if (IS_ERR(nandc->base)) in qcom_nandc_probe()
3275 return PTR_ERR(nandc->base); in qcom_nandc_probe()
3277 nandc->base_phys = res->start; in qcom_nandc_probe()
3278 nandc->base_dma = dma_map_resource(dev, res->start, in qcom_nandc_probe()
3281 if (dma_mapping_error(dev, nandc->base_dma)) in qcom_nandc_probe()
3282 return -ENXIO; in qcom_nandc_probe()
3284 ret = clk_prepare_enable(nandc->core_clk); in qcom_nandc_probe()
3288 ret = clk_prepare_enable(nandc->aon_clk); in qcom_nandc_probe()
3309 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_probe()
3311 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_probe()
3313 dma_unmap_resource(dev, res->start, resource_size(res), in qcom_nandc_probe()
3326 list_for_each_entry(host, &nandc->host_list, node) { in qcom_nandc_remove()
3327 chip = &host->chip; in qcom_nandc_remove()
3335 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_remove()
3336 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_remove()
3338 dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res), in qcom_nandc_remove()
3379 .compatible = "qcom,ipq806x-nand",
3383 .compatible = "qcom,ipq4019-nand",
3387 .compatible = "qcom,ipq6018-nand",
3391 .compatible = "qcom,ipq8074-nand",
3395 .compatible = "qcom,sdx55-nand",
3404 .name = "qcom-nandc",
3413 MODULE_DESCRIPTION("Qualcomm NAND Controller driver");