| /Linux-v5.10/Documentation/devicetree/bindings/pci/ |
| D | pci-iommu.txt | 2 relationship between PCI(e) devices and IOMMU(s).
17 Requester ID. While a given PCI device can only master through one IOMMU, a
18 root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
33 -------------------
35 - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
39 (rid-base,iommu,iommu-base,length).
41 Any RID r in the interval [rid-base, rid-base + length) is associated with
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| /Linux-v5.10/Documentation/devicetree/bindings/misc/ |
| D | fsl,qoriq-mc.txt | 3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
22 the set of possible ICIDs under a root DPRC and how they map to
23 an IOMMU.
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
28 For arm-smmu binding, see:
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| /Linux-v5.10/Documentation/devicetree/bindings/virtio/ |
| D | iommu.txt | 1 * virtio IOMMU PCI device
3 When virtio-iommu uses the PCI transport, its programming interface is
5 device tree statically describes the relation between IOMMU and DMA
6 masters. Therefore, the PCI root complex that hosts the virtio-iommu
7 contains a child node representing the IOMMU device explicitly.
11 - compatible: Should be "virtio,pci-iommu"
12 - reg: PCI address of the IOMMU. As defined in the PCI Bus
13 Binding reference [1], the reg property is a five-cell
18 - #iommu-cells: Each platform DMA master managed by the IOMMU is assigned
20 For virtio-iommu, #iommu-cells must be 1.
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| D | mmio.txt | 3 See https://ozlabs.org/~rusty/virtio-spec/ for more details.
7 - compatible: "virtio,mmio" compatibility string
8 - reg: control registers base address and size including configuration space
9 - interrupts: interrupt generated by the device
11 Required properties for virtio-iommu:
13 - #iommu-cells: When the node corresponds to a virtio-iommu device, it is
14 linked to DMA masters using the "iommus" or "iommu-map"
15 properties [1][2]. #iommu-cells specifies the size of the
16 "iommus" property. For virtio-iommu #iommu-cells must be
21 - iommus: If the device accesses memory through an IOMMU, it should
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| /Linux-v5.10/drivers/gpu/drm/msm/ |
| D | msm_iommu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
8 #include <linux/io-pgtable.h>
36 struct io_pgtable_ops *ops = pagetable->pgtbl_ops; in msm_iommu_pagetable_unmap()
41 unmapped += ops->unmap(ops, iova, 4096, NULL); in msm_iommu_pagetable_unmap()
43 size -= 4096; in msm_iommu_pagetable_unmap()
46 iommu_flush_iotlb_all(to_msm_iommu(pagetable->parent)->domain); in msm_iommu_pagetable_unmap()
48 return (unmapped == size) ? 0 : -EINVAL; in msm_iommu_pagetable_unmap()
55 struct io_pgtable_ops *ops = pagetable->pgtbl_ops; in msm_iommu_pagetable_map()
61 for_each_sg(sgt->sgl, sg, sgt->nents, i) { in msm_iommu_pagetable_map()
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| /Linux-v5.10/drivers/iommu/ |
| D | msm_iommu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
13 #include <linux/io-pgtable.h>
18 #include <linux/iommu.h>
26 #include "msm_iommu_hw-8xxx.h"
55 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
59 ret = clk_enable(iommu->pclk); in __enable_clocks()
63 if (iommu->clk) { in __enable_clocks()
64 ret = clk_enable(iommu->clk); in __enable_clocks()
66 clk_disable(iommu->pclk); in __enable_clocks()
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| D | of_iommu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * OF helpers for IOMMU
9 #include <linux/iommu.h>
23 * of_get_dma_window - Parse *dma-window property and returns 0 if found.
44 return -EINVAL; in of_get_dma_window()
49 snprintf(propname, sizeof(propname), "%sdma-window", prefix); in of_get_dma_window()
50 snprintf(addrname, sizeof(addrname), "%s#dma-address-cells", prefix); in of_get_dma_window()
51 snprintf(sizename, sizeof(sizename), "%s#dma-size-cells", prefix); in of_get_dma_window()
55 return -ENODEV; in of_get_dma_window()
68 prop = of_get_property(dn, "#address-cells", NULL); in of_get_dma_window()
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| /Linux-v5.10/arch/sparc/kernel/ |
| D | iommu.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* iommu.c: Generic sparc64 IOMMU support.
13 #include <linux/dma-map-ops.h>
15 #include <linux/iommu-helper.h>
17 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
29 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
31 (*((STC)->strbuf_flushflag) = 0UL)
33 (*((STC)->strbuf_flushflag) != 0UL)
49 /* Must be invoked under the IOMMU lock. */
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| D | iommu-common.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU mmap management and range allocation functions.
4 * Based almost entirely upon the powerpc iommu allocator.
10 #include <linux/iommu-helper.h>
11 #include <linux/dma-mapping.h>
13 #include <asm/iommu-common.h>
19 static inline bool need_flush(struct iommu_map_table *iommu) in need_flush() argument
21 return ((iommu->flags & IOMMU_NEED_FLUSH) != 0); in need_flush()
24 static inline void set_flush(struct iommu_map_table *iommu) in set_flush() argument
26 iommu->flags |= IOMMU_NEED_FLUSH; in set_flush()
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| D | pci_sun4v.c | 1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/dma-map-ops.h>
20 #include <asm/iommu-common.h>
22 #include <asm/iommu.h>
57 unsigned long prot; /* IOMMU page protections */
71 p->dev = dev; in iommu_batch_start()
72 p->prot = prot; in iommu_batch_start()
73 p->entry = entry; in iommu_batch_start()
74 p->npages = 0; in iommu_batch_start()
77 static inline bool iommu_use_atu(struct iommu *iommu, u64 mask) in iommu_use_atu() argument
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| /Linux-v5.10/drivers/vfio/ |
| D | vfio_iommu_type1.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * VFIO: IOMMU DMA mapping support for Type1 IOMMU
12 * We arbitrarily define a Type1 IOMMU as one matching the below code.
13 * It could be called the x86 IOMMU as it's designed for AMD-Vi & Intel
14 * VT-d, but that makes it harder to re-use as theoretically anyone
15 * implementing a similar IOMMU could make use of this. We expect the
16 * IOMMU to support the IOMMU API and have few to no restrictions around
17 * the IOVA range that can be mapped. The Type1 IOMMU is currently
19 * userpsace pages pinned into memory. We also assume devices and IOMMU
20 * domains are PCI based as the IOMMU API is still centered around a
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| /Linux-v5.10/drivers/vdpa/vdpa_sim/ |
| D | vdpa_sim.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/iommu.h>
21 #include <linux/dma-map-ops.h>
39 MODULE_PARM_DESC(batch_mapping, "Batched mapping 1 -Enable; 0 - Disable");
63 #define VDPASIM_NAME "vdpasim-netdev"
78 struct vhost_iotlb *iommu; member
83 /* spinlock to synchronize iommu table */
87 /* TODO: cross-endian support */
91 (vdpasim->features & (1ULL << VIRTIO_F_VERSION_1)); in vdpasim_is_little_endian()
120 struct vdpasim_virtqueue *vq = &vdpasim->vqs[idx]; in vdpasim_queue_ready()
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| /Linux-v5.10/include/linux/ |
| D | iommu.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
17 #include <uapi/linux/iommu.h>
31 * if the IOMMU page table format is equivalent.
44 /* iommu fault flags */
60 #define __IOMMU_DOMAIN_DMA_API (1U << 1) /* Domain for use in DMA-API
65 * This are the possible domain-types
67 * IOMMU_DOMAIN_BLOCKED - All DMA is blocked, can be used to isolate
69 * IOMMU_DOMAIN_IDENTITY - DMA addresses are system physical addresses
70 * IOMMU_DOMAIN_UNMANAGED - DMA mappings managed by IOMMU-API user, used
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| D | io-pgtable.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <linux/iommu.h>
9 * Public API for use by IOMMU drivers
22 * struct iommu_flush_ops - IOMMU callbacks for TLB and page table management.
50 * struct io_pgtable_cfg - Configuration data for a set of page tables.
53 * action by the low-level page table allocator.
59 * by the IOMMU are coherent with the CPU caches.
68 * even in non-secure state where they should normally be ignored.
71 * IOMMU_NOEXEC flags and map everything with full access, for
73 * format, and/or requires some format-specific default value.
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| /Linux-v5.10/arch/powerpc/boot/dts/fsl/ |
| D | p5020si-post.dtsi | 4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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| D | p3041si-post.dtsi | 4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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| D | p2041si-post.dtsi | 4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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| D | p5040si-post.dtsi | 4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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| /Linux-v5.10/arch/sparc/mm/ |
| D | iommu.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * iommu.c: IOMMU specific routines for memory management.
15 #include <linux/dma-map-ops.h>
25 #include <asm/iommu.h>
59 struct iommu_struct *iommu; in sbus_iommu_init() local
66 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL); in sbus_iommu_init()
67 if (!iommu) { in sbus_iommu_init()
68 prom_printf("Unable to allocate iommu structure\n"); in sbus_iommu_init()
72 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
74 if (!iommu->regs) { in sbus_iommu_init()
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| /Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/ |
| D | gk20a.c | 30 * 1) If an IOMMU unit has been probed, the IOMMU API is used to make memory
32 * 2) If no IOMMU unit is probed, the DMA API is used to allocate physically
35 * In both cases CPU read and writes are performed by creating a write-combined
74 * Used for objects flattened using the IOMMU API
86 /* array of base.mem->size pages (+ dma_addr_ts) */
103 /* Only used if IOMMU if present */
130 return (u64)gk20a_instobj(memory)->mn->offset << 12; in gk20a_instobj_addr()
136 return (u64)gk20a_instobj(memory)->mn->length << 12; in gk20a_instobj_size()
145 struct gk20a_instmem *imem = obj->base.imem; in gk20a_instobj_iommu_recycle_vaddr()
147 WARN_ON(obj->use_cpt); in gk20a_instobj_iommu_recycle_vaddr()
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| /Linux-v5.10/arch/x86/kernel/ |
| D | amd_gart_64.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
9 * See Documentation/core-api/dma-api-howto.rst for the interface specification.
29 #include <linux/iommu-helper.h>
34 #include <linux/dma-direct.h>
35 #include <linux/dma-map-ops.h>
38 #include <asm/iommu.h>
54 * If this is disabled the IOMMU will use an optimized flushing strategy
105 if (offset == -1) { in alloc_iommu()
111 if (offset != -1) { in alloc_iommu()
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| /Linux-v5.10/drivers/iommu/intel/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 # Intel IOMMU support
7 bool "Support for Intel IOMMU using DMA Remapping Devices"
24 bool "Export Intel IOMMU internals in Debugfs"
31 Expose Intel IOMMU internals in Debugfs.
33 This option is -NOT- intended for production environments, and should
34 only be enabled for debugging Intel IOMMU.
37 bool "Support for Shared Virtual Memory with Intel IOMMU"
63 option permits the IOMMU driver to set a unity map for
64 all the OS-visible memory. Hence the driver can continue
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| D | dmar.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2006-2008 Intel Corporation
14 * These routines are used by both DMA-remapping and Interrupt-remapping
22 #include <linux/intel-iommu.h>
29 #include <linux/iommu.h>
47 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
49 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
65 static void free_iommu(struct intel_iommu *iommu);
75 if (drhd->include_all) in dmar_register_drhd_unit()
76 list_add_tail_rcu(&drhd->list, &dmar_drhd_units); in dmar_register_drhd_unit()
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| /Linux-v5.10/arch/arm64/boot/dts/arm/ |
| D | juno-base.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
30 interrupt-names = "mhu_lpri_rx",
32 #mbox-cells = <1>;
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| /Linux-v5.10/lib/ |
| D | iommu-helper.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU helper functions for the free area management
7 #include <linux/iommu-helper.h>
9 unsigned long iommu_area_alloc(unsigned long *map, unsigned long size, in iommu_area_alloc() argument
17 size -= 1; in iommu_area_alloc()
19 index = bitmap_find_next_zero_area(map, size, start, nr, align_mask); in iommu_area_alloc()
22 start = ALIGN(shift + index, boundary_size) - shift; in iommu_area_alloc()
25 bitmap_set(map, index, nr); in iommu_area_alloc()
28 return -1; in iommu_area_alloc()
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