Lines Matching +full:iommu +full:- +full:map
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2006-2008 Intel Corporation
14 * These routines are used by both DMA-remapping and Interrupt-remapping
22 #include <linux/intel-iommu.h>
29 #include <linux/iommu.h>
47 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
49 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
65 static void free_iommu(struct intel_iommu *iommu);
75 if (drhd->include_all) in dmar_register_drhd_unit()
76 list_add_tail_rcu(&drhd->list, &dmar_drhd_units); in dmar_register_drhd_unit()
78 list_add_rcu(&drhd->list, &dmar_drhd_units); in dmar_register_drhd_unit()
88 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE || in dmar_alloc_dev_scope()
89 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT || in dmar_alloc_dev_scope()
90 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) in dmar_alloc_dev_scope()
92 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC && in dmar_alloc_dev_scope()
93 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) { in dmar_alloc_dev_scope()
96 start += scope->length; in dmar_alloc_dev_scope()
130 BUG_ON(dev->is_virtfn); in dmar_alloc_pci_notify_info()
136 if (pci_domain_nr(dev->bus) > U16_MAX) in dmar_alloc_pci_notify_info()
141 for (tmp = dev; tmp; tmp = tmp->bus->self) in dmar_alloc_pci_notify_info()
153 dmar_dev_scope_status = -ENOMEM; in dmar_alloc_pci_notify_info()
158 info->event = event; in dmar_alloc_pci_notify_info()
159 info->dev = dev; in dmar_alloc_pci_notify_info()
160 info->seg = pci_domain_nr(dev->bus); in dmar_alloc_pci_notify_info()
161 info->level = level; in dmar_alloc_pci_notify_info()
163 for (tmp = dev; tmp; tmp = tmp->bus->self) { in dmar_alloc_pci_notify_info()
164 level--; in dmar_alloc_pci_notify_info()
165 info->path[level].bus = tmp->bus->number; in dmar_alloc_pci_notify_info()
166 info->path[level].device = PCI_SLOT(tmp->devfn); in dmar_alloc_pci_notify_info()
167 info->path[level].function = PCI_FUNC(tmp->devfn); in dmar_alloc_pci_notify_info()
168 if (pci_is_root_bus(tmp->bus)) in dmar_alloc_pci_notify_info()
169 info->bus = tmp->bus->number; in dmar_alloc_pci_notify_info()
187 if (info->bus != bus) in dmar_match_pci_path()
189 if (info->level != count) in dmar_match_pci_path()
193 if (path[i].device != info->path[i].device || in dmar_match_pci_path()
194 path[i].function != info->path[i].function) in dmar_match_pci_path()
205 i = info->level - 1; in dmar_match_pci_path()
206 if (bus == info->path[i].bus && in dmar_match_pci_path()
207 path[0].device == info->path[i].device && in dmar_match_pci_path()
208 path[0].function == info->path[i].function) { in dmar_match_pci_path()
209 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n", in dmar_match_pci_path()
224 struct device *tmp, *dev = &info->dev->dev; in dmar_insert_dev_scope()
228 if (segment != info->seg) in dmar_insert_dev_scope()
231 for (; start < end; start += scope->length) { in dmar_insert_dev_scope()
233 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && in dmar_insert_dev_scope()
234 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE) in dmar_insert_dev_scope()
238 level = (scope->length - sizeof(*scope)) / sizeof(*path); in dmar_insert_dev_scope()
239 if (!dmar_match_pci_path(info, scope->bus, path, level)) in dmar_insert_dev_scope()
248 * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch in dmar_insert_dev_scope()
251 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && in dmar_insert_dev_scope()
252 info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) || in dmar_insert_dev_scope()
253 (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE && in dmar_insert_dev_scope()
254 (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in dmar_insert_dev_scope()
255 info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) { in dmar_insert_dev_scope()
257 pci_name(info->dev)); in dmar_insert_dev_scope()
258 return -EINVAL; in dmar_insert_dev_scope()
263 devices[i].bus = info->dev->bus->number; in dmar_insert_dev_scope()
264 devices[i].devfn = info->dev->devfn; in dmar_insert_dev_scope()
281 if (info->seg != segment) in dmar_remove_dev_scope()
285 if (tmp == &info->dev->dev) { in dmar_remove_dev_scope()
302 if (dmaru->include_all) in dmar_pci_bus_add_dev()
305 drhd = container_of(dmaru->hdr, in dmar_pci_bus_add_dev()
308 ((void *)drhd) + drhd->header.length, in dmar_pci_bus_add_dev()
309 dmaru->segment, in dmar_pci_bus_add_dev()
310 dmaru->devices, dmaru->devices_cnt); in dmar_pci_bus_add_dev()
330 if (dmar_remove_dev_scope(info, dmaru->segment, in dmar_pci_bus_del_dev()
331 dmaru->devices, dmaru->devices_cnt)) in dmar_pci_bus_del_dev()
340 dev_set_msi_domain(&pdev->dev, dev_get_msi_domain(&physfn->dev)); in vf_inherit_msi_domain()
352 if (pdev->is_virtfn) { in dmar_pci_bus_notifier()
398 if (dmaru->segment == drhd->segment && in dmar_find_dmaru()
399 dmaru->reg_base_addr == drhd->address) in dmar_find_dmaru()
406 * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
421 dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL); in dmar_parse_one_drhd()
423 return -ENOMEM; in dmar_parse_one_drhd()
429 dmaru->hdr = (void *)(dmaru + 1); in dmar_parse_one_drhd()
430 memcpy(dmaru->hdr, header, header->length); in dmar_parse_one_drhd()
431 dmaru->reg_base_addr = drhd->address; in dmar_parse_one_drhd()
432 dmaru->segment = drhd->segment; in dmar_parse_one_drhd()
433 dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */ in dmar_parse_one_drhd()
434 dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1), in dmar_parse_one_drhd()
435 ((void *)drhd) + drhd->header.length, in dmar_parse_one_drhd()
436 &dmaru->devices_cnt); in dmar_parse_one_drhd()
437 if (dmaru->devices_cnt && dmaru->devices == NULL) { in dmar_parse_one_drhd()
439 return -ENOMEM; in dmar_parse_one_drhd()
444 dmar_free_dev_scope(&dmaru->devices, in dmar_parse_one_drhd()
445 &dmaru->devices_cnt); in dmar_parse_one_drhd()
460 if (dmaru->devices && dmaru->devices_cnt) in dmar_free_drhd()
461 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt); in dmar_free_drhd()
462 if (dmaru->iommu) in dmar_free_drhd()
463 free_iommu(dmaru->iommu); in dmar_free_drhd()
473 if (strnlen(andd->device_name, header->length - 8) == header->length - 8) { in dmar_parse_one_andd()
475 "Your BIOS is broken; ANDD object name is not NUL-terminated\n" in dmar_parse_one_andd()
481 return -EINVAL; in dmar_parse_one_andd()
483 pr_info("ANDD device: %x name: %s\n", andd->device_number, in dmar_parse_one_andd()
484 andd->device_name); in dmar_parse_one_andd()
497 if (drhd->reg_base_addr == rhsa->base_address) { in dmar_parse_one_rhsa()
498 int node = pxm_to_node(rhsa->proximity_domain); in dmar_parse_one_rhsa()
502 drhd->iommu->node = node; in dmar_parse_one_rhsa()
507 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n" in dmar_parse_one_rhsa()
509 rhsa->base_address, in dmar_parse_one_rhsa()
529 switch (header->type) { in dmar_table_print_dmar_entry()
534 (unsigned long long)drhd->address, drhd->flags); in dmar_table_print_dmar_entry()
540 (unsigned long long)rmrr->base_address, in dmar_table_print_dmar_entry()
541 (unsigned long long)rmrr->end_address); in dmar_table_print_dmar_entry()
545 pr_info("ATSR flags: %#x\n", atsr->flags); in dmar_table_print_dmar_entry()
550 (unsigned long long)rhsa->base_address, in dmar_table_print_dmar_entry()
551 rhsa->proximity_domain); in dmar_table_print_dmar_entry()
554 /* We don't print this here because we need to sanity-check in dmar_table_print_dmar_entry()
561 * dmar_table_detect - checks to see if the platform supports DMAR devices
571 pr_warn("Unable to map DMAR\n"); in dmar_table_detect()
575 return ACPI_SUCCESS(status) ? 0 : -ENOENT; in dmar_table_detect()
585 next = (void *)iter + iter->length; in dmar_walk_remapping_entries()
586 if (iter->length == 0) { in dmar_walk_remapping_entries()
588 pr_debug(FW_BUG "Invalid 0-length structure\n"); in dmar_walk_remapping_entries()
593 return -EINVAL; in dmar_walk_remapping_entries()
596 if (cb->print_entry) in dmar_walk_remapping_entries()
599 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) { in dmar_walk_remapping_entries()
602 iter->type); in dmar_walk_remapping_entries()
603 } else if (cb->cb[iter->type]) { in dmar_walk_remapping_entries()
606 ret = cb->cb[iter->type](iter, cb->arg[iter->type]); in dmar_walk_remapping_entries()
609 } else if (!cb->ignore_unhandled) { in dmar_walk_remapping_entries()
611 iter->type); in dmar_walk_remapping_entries()
612 return -EINVAL; in dmar_walk_remapping_entries()
623 dmar->header.length - sizeof(*dmar), cb); in dmar_walk_dmar_table()
627 * parse_dmar_table - parses the DMA reporting table
648 * fixed map. in parse_dmar_table()
660 return -ENODEV; in parse_dmar_table()
662 if (dmar->width < PAGE_SHIFT - 1) { in parse_dmar_table()
664 return -EINVAL; in parse_dmar_table()
667 pr_info("Host address width %d\n", dmar->width + 1); in parse_dmar_table()
687 dev = dev->bus->self; in dmar_pci_device_match()
703 drhd = container_of(dmaru->hdr, in dmar_find_matched_drhd_unit()
707 if (dmaru->include_all && in dmar_find_matched_drhd_unit()
708 drhd->segment == pci_domain_nr(dev->bus)) in dmar_find_matched_drhd_unit()
711 if (dmar_pci_device_match(dmaru->devices, in dmar_find_matched_drhd_unit()
712 dmaru->devices_cnt, dev)) in dmar_find_matched_drhd_unit()
733 drhd = container_of(dmaru->hdr, in dmar_acpi_insert_dev_scope()
738 (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length; in dmar_acpi_insert_dev_scope()
739 scope = ((void *)scope) + scope->length) { in dmar_acpi_insert_dev_scope()
740 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE) in dmar_acpi_insert_dev_scope()
742 if (scope->enumeration_id != device_number) in dmar_acpi_insert_dev_scope()
747 dev_name(&adev->dev), dmaru->reg_base_addr, in dmar_acpi_insert_dev_scope()
748 scope->bus, path->device, path->function); in dmar_acpi_insert_dev_scope()
749 for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp) in dmar_acpi_insert_dev_scope()
751 dmaru->devices[i].bus = scope->bus; in dmar_acpi_insert_dev_scope()
752 dmaru->devices[i].devfn = PCI_DEVFN(path->device, in dmar_acpi_insert_dev_scope()
753 path->function); in dmar_acpi_insert_dev_scope()
754 rcu_assign_pointer(dmaru->devices[i].dev, in dmar_acpi_insert_dev_scope()
755 get_device(&adev->dev)); in dmar_acpi_insert_dev_scope()
758 BUG_ON(i >= dmaru->devices_cnt); in dmar_acpi_insert_dev_scope()
761 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", in dmar_acpi_insert_dev_scope()
762 device_number, dev_name(&adev->dev)); in dmar_acpi_insert_dev_scope()
770 return -ENODEV; in dmar_acpi_dev_scope_init()
773 ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length; in dmar_acpi_dev_scope_init()
774 andd = ((void *)andd) + andd->header.length) { in dmar_acpi_dev_scope_init()
775 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) { in dmar_acpi_dev_scope_init()
780 andd->device_name, in dmar_acpi_dev_scope_init()
783 andd->device_name); in dmar_acpi_dev_scope_init()
788 andd->device_name); in dmar_acpi_dev_scope_init()
791 dmar_acpi_insert_dev_scope(andd->device_number, adev); in dmar_acpi_dev_scope_init()
806 dmar_dev_scope_status = -ENODEV; in dmar_dev_scope_init()
813 if (dev->is_virtfn) in dmar_dev_scope_init()
844 if (ret != -ENODEV) in dmar_table_init()
848 ret = -ENODEV; in dmar_table_init()
880 if (!drhd->address) { in dmar_validate_one_drhd()
882 return -EINVAL; in dmar_validate_one_drhd()
886 addr = ioremap(drhd->address, VTD_PAGE_SIZE); in dmar_validate_one_drhd()
888 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE); in dmar_validate_one_drhd()
890 pr_warn("Can't validate DRHD address: %llx\n", drhd->address); in dmar_validate_one_drhd()
891 return -EINVAL; in dmar_validate_one_drhd()
902 if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) { in dmar_validate_one_drhd()
903 warn_invalid_dmar(drhd->address, " returns all ones"); in dmar_validate_one_drhd()
904 return -EINVAL; in dmar_validate_one_drhd()
932 x86_init.iommu.iommu_init = intel_iommu_init; in detect_intel_iommu()
947 static void unmap_iommu(struct intel_iommu *iommu) in unmap_iommu() argument
949 iounmap(iommu->reg); in unmap_iommu()
950 release_mem_region(iommu->reg_phys, iommu->reg_size); in unmap_iommu()
954 * map_iommu: map the iommu's registers
955 * @iommu: the iommu to map
958 * Memory map the iommu's registers. Start w/ a single page, and
961 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr) in map_iommu() argument
965 iommu->reg_phys = phys_addr; in map_iommu()
966 iommu->reg_size = VTD_PAGE_SIZE; in map_iommu()
968 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) { in map_iommu()
970 err = -EBUSY; in map_iommu()
974 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); in map_iommu()
975 if (!iommu->reg) { in map_iommu()
976 pr_err("Can't map the region\n"); in map_iommu()
977 err = -ENOMEM; in map_iommu()
981 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); in map_iommu()
982 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); in map_iommu()
984 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) { in map_iommu()
985 err = -EINVAL; in map_iommu()
989 if (ecap_vcs(iommu->ecap)) in map_iommu()
990 iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG); in map_iommu()
993 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), in map_iommu()
994 cap_max_fault_reg_offset(iommu->cap)); in map_iommu()
996 if (map_size > iommu->reg_size) { in map_iommu()
997 iounmap(iommu->reg); in map_iommu()
998 release_mem_region(iommu->reg_phys, iommu->reg_size); in map_iommu()
999 iommu->reg_size = map_size; in map_iommu()
1000 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, in map_iommu()
1001 iommu->name)) { in map_iommu()
1003 err = -EBUSY; in map_iommu()
1006 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); in map_iommu()
1007 if (!iommu->reg) { in map_iommu()
1008 pr_err("Can't map the region\n"); in map_iommu()
1009 err = -ENOMEM; in map_iommu()
1017 iounmap(iommu->reg); in map_iommu()
1019 release_mem_region(iommu->reg_phys, iommu->reg_size); in map_iommu()
1024 static int dmar_alloc_seq_id(struct intel_iommu *iommu) in dmar_alloc_seq_id() argument
1026 iommu->seq_id = find_first_zero_bit(dmar_seq_ids, in dmar_alloc_seq_id()
1028 if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) { in dmar_alloc_seq_id()
1029 iommu->seq_id = -1; in dmar_alloc_seq_id()
1031 set_bit(iommu->seq_id, dmar_seq_ids); in dmar_alloc_seq_id()
1032 sprintf(iommu->name, "dmar%d", iommu->seq_id); in dmar_alloc_seq_id()
1035 return iommu->seq_id; in dmar_alloc_seq_id()
1038 static void dmar_free_seq_id(struct intel_iommu *iommu) in dmar_free_seq_id() argument
1040 if (iommu->seq_id >= 0) { in dmar_free_seq_id()
1041 clear_bit(iommu->seq_id, dmar_seq_ids); in dmar_free_seq_id()
1042 iommu->seq_id = -1; in dmar_free_seq_id()
1048 struct intel_iommu *iommu; in alloc_iommu() local
1050 int agaw = -1; in alloc_iommu()
1051 int msagaw = -1; in alloc_iommu()
1054 if (!drhd->reg_base_addr) { in alloc_iommu()
1056 return -EINVAL; in alloc_iommu()
1059 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); in alloc_iommu()
1060 if (!iommu) in alloc_iommu()
1061 return -ENOMEM; in alloc_iommu()
1063 if (dmar_alloc_seq_id(iommu) < 0) { in alloc_iommu()
1065 err = -ENOSPC; in alloc_iommu()
1069 err = map_iommu(iommu, drhd->reg_base_addr); in alloc_iommu()
1071 pr_err("Failed to map %s\n", iommu->name); in alloc_iommu()
1075 err = -EINVAL; in alloc_iommu()
1076 if (cap_sagaw(iommu->cap) == 0) { in alloc_iommu()
1078 iommu->name); in alloc_iommu()
1079 drhd->ignored = 1; in alloc_iommu()
1082 if (!drhd->ignored) { in alloc_iommu()
1083 agaw = iommu_calculate_agaw(iommu); in alloc_iommu()
1085 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n", in alloc_iommu()
1086 iommu->seq_id); in alloc_iommu()
1087 drhd->ignored = 1; in alloc_iommu()
1090 if (!drhd->ignored) { in alloc_iommu()
1091 msagaw = iommu_calculate_max_sagaw(iommu); in alloc_iommu()
1093 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n", in alloc_iommu()
1094 iommu->seq_id); in alloc_iommu()
1095 drhd->ignored = 1; in alloc_iommu()
1096 agaw = -1; in alloc_iommu()
1099 iommu->agaw = agaw; in alloc_iommu()
1100 iommu->msagaw = msagaw; in alloc_iommu()
1101 iommu->segment = drhd->segment; in alloc_iommu()
1103 iommu->node = NUMA_NO_NODE; in alloc_iommu()
1105 ver = readl(iommu->reg + DMAR_VER_REG); in alloc_iommu()
1107 iommu->name, in alloc_iommu()
1108 (unsigned long long)drhd->reg_base_addr, in alloc_iommu()
1110 (unsigned long long)iommu->cap, in alloc_iommu()
1111 (unsigned long long)iommu->ecap); in alloc_iommu()
1114 sts = readl(iommu->reg + DMAR_GSTS_REG); in alloc_iommu()
1116 iommu->gcmd |= DMA_GCMD_IRE; in alloc_iommu()
1118 iommu->gcmd |= DMA_GCMD_TE; in alloc_iommu()
1120 iommu->gcmd |= DMA_GCMD_QIE; in alloc_iommu()
1122 raw_spin_lock_init(&iommu->register_lock); in alloc_iommu()
1129 if (intel_iommu_enabled && !drhd->ignored) { in alloc_iommu()
1130 err = iommu_device_sysfs_add(&iommu->iommu, NULL, in alloc_iommu()
1132 "%s", iommu->name); in alloc_iommu()
1136 iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops); in alloc_iommu()
1138 err = iommu_device_register(&iommu->iommu); in alloc_iommu()
1143 drhd->iommu = iommu; in alloc_iommu()
1144 iommu->drhd = drhd; in alloc_iommu()
1149 unmap_iommu(iommu); in alloc_iommu()
1151 dmar_free_seq_id(iommu); in alloc_iommu()
1153 kfree(iommu); in alloc_iommu()
1157 static void free_iommu(struct intel_iommu *iommu) in free_iommu() argument
1159 if (intel_iommu_enabled && !iommu->drhd->ignored) { in free_iommu()
1160 iommu_device_unregister(&iommu->iommu); in free_iommu()
1161 iommu_device_sysfs_remove(&iommu->iommu); in free_iommu()
1164 if (iommu->irq) { in free_iommu()
1165 if (iommu->pr_irq) { in free_iommu()
1166 free_irq(iommu->pr_irq, iommu); in free_iommu()
1167 dmar_free_hwirq(iommu->pr_irq); in free_iommu()
1168 iommu->pr_irq = 0; in free_iommu()
1170 free_irq(iommu->irq, iommu); in free_iommu()
1171 dmar_free_hwirq(iommu->irq); in free_iommu()
1172 iommu->irq = 0; in free_iommu()
1175 if (iommu->qi) { in free_iommu()
1176 free_page((unsigned long)iommu->qi->desc); in free_iommu()
1177 kfree(iommu->qi->desc_status); in free_iommu()
1178 kfree(iommu->qi); in free_iommu()
1181 if (iommu->reg) in free_iommu()
1182 unmap_iommu(iommu); in free_iommu()
1184 dmar_free_seq_id(iommu); in free_iommu()
1185 kfree(iommu); in free_iommu()
1193 while (qi->desc_status[qi->free_tail] == QI_DONE || in reclaim_free_desc()
1194 qi->desc_status[qi->free_tail] == QI_ABORT) { in reclaim_free_desc()
1195 qi->desc_status[qi->free_tail] = QI_FREE; in reclaim_free_desc()
1196 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH; in reclaim_free_desc()
1197 qi->free_cnt++; in reclaim_free_desc()
1201 static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index) in qi_check_fault() argument
1205 struct q_inval *qi = iommu->qi; in qi_check_fault()
1206 int shift = qi_shift(iommu); in qi_check_fault()
1208 if (qi->desc_status[wait_index] == QI_ABORT) in qi_check_fault()
1209 return -EAGAIN; in qi_check_fault()
1211 fault = readl(iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1219 head = readl(iommu->reg + DMAR_IQH_REG); in qi_check_fault()
1221 struct qi_desc *desc = qi->desc + head; in qi_check_fault()
1224 * desc->qw2 and desc->qw3 are either reserved or in qi_check_fault()
1228 pr_err("VT-d detected invalid descriptor: qw0 = %llx, qw1 = %llx\n", in qi_check_fault()
1229 (unsigned long long)desc->qw0, in qi_check_fault()
1230 (unsigned long long)desc->qw1); in qi_check_fault()
1231 memcpy(desc, qi->desc + (wait_index << shift), in qi_check_fault()
1233 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1234 return -EINVAL; in qi_check_fault()
1243 head = readl(iommu->reg + DMAR_IQH_REG); in qi_check_fault()
1244 head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH; in qi_check_fault()
1246 tail = readl(iommu->reg + DMAR_IQT_REG); in qi_check_fault()
1247 tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH; in qi_check_fault()
1249 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1252 if (qi->desc_status[head] == QI_IN_USE) in qi_check_fault()
1253 qi->desc_status[head] = QI_ABORT; in qi_check_fault()
1254 head = (head - 2 + QI_LENGTH) % QI_LENGTH; in qi_check_fault()
1257 if (qi->desc_status[wait_index] == QI_ABORT) in qi_check_fault()
1258 return -EAGAIN; in qi_check_fault()
1262 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1274 int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc, in qi_submit_sync() argument
1277 struct q_inval *qi = iommu->qi; in qi_submit_sync()
1290 raw_spin_lock_irqsave(&qi->q_lock, flags); in qi_submit_sync()
1296 while (qi->free_cnt < count + 2) { in qi_submit_sync()
1297 raw_spin_unlock_irqrestore(&qi->q_lock, flags); in qi_submit_sync()
1299 raw_spin_lock_irqsave(&qi->q_lock, flags); in qi_submit_sync()
1302 index = qi->free_head; in qi_submit_sync()
1304 shift = qi_shift(iommu); in qi_submit_sync()
1308 memcpy(qi->desc + offset, &desc[i], 1 << shift); in qi_submit_sync()
1309 qi->desc_status[(index + i) % QI_LENGTH] = QI_IN_USE; in qi_submit_sync()
1311 qi->desc_status[wait_index] = QI_IN_USE; in qi_submit_sync()
1317 wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]); in qi_submit_sync()
1322 memcpy(qi->desc + offset, &wait_desc, 1 << shift); in qi_submit_sync()
1324 qi->free_head = (qi->free_head + count + 1) % QI_LENGTH; in qi_submit_sync()
1325 qi->free_cnt -= count + 1; in qi_submit_sync()
1331 writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); in qi_submit_sync()
1333 while (qi->desc_status[wait_index] != QI_DONE) { in qi_submit_sync()
1341 rc = qi_check_fault(iommu, index, wait_index); in qi_submit_sync()
1345 raw_spin_unlock(&qi->q_lock); in qi_submit_sync()
1347 raw_spin_lock(&qi->q_lock); in qi_submit_sync()
1351 qi->desc_status[(index + i) % QI_LENGTH] = QI_DONE; in qi_submit_sync()
1354 raw_spin_unlock_irqrestore(&qi->q_lock, flags); in qi_submit_sync()
1356 if (rc == -EAGAIN) in qi_submit_sync()
1365 void qi_global_iec(struct intel_iommu *iommu) in qi_global_iec() argument
1375 qi_submit_sync(iommu, &desc, 1, 0); in qi_global_iec()
1378 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm, in qi_flush_context() argument
1389 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_context()
1392 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, in qi_flush_iotlb() argument
1400 if (cap_write_drain(iommu->cap)) in qi_flush_iotlb()
1403 if (cap_read_drain(iommu->cap)) in qi_flush_iotlb()
1413 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_iotlb()
1416 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, in qi_flush_dev_iotlb() argument
1422 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1; in qi_flush_dev_iotlb()
1435 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_dev_iotlb()
1438 /* PASID-based IOTLB invalidation */
1439 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, in qi_flush_piotlb() argument
1445 * npages == -1 means a PASID-selective invalidation, otherwise, in qi_flush_piotlb()
1446 * a positive value for Page-selective-within-PASID invalidation. in qi_flush_piotlb()
1454 if (npages == -1) { in qi_flush_piotlb()
1465 addr &= ~(align - 1); in qi_flush_piotlb()
1476 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_piotlb()
1479 /* PASID-based device IOTLB Invalidate */
1480 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, in qi_flush_dev_iotlb_pasid() argument
1483 unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1); in qi_flush_dev_iotlb_pasid()
1493 * range. VT-d spec 6.5.2.6. in qi_flush_dev_iotlb_pasid()
1500 pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n", in qi_flush_dev_iotlb_pasid()
1512 desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1, in qi_flush_dev_iotlb_pasid()
1520 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_dev_iotlb_pasid()
1523 void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, in qi_flush_pasid_cache() argument
1530 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_pasid_cache()
1536 void dmar_disable_qi(struct intel_iommu *iommu) in dmar_disable_qi() argument
1542 if (!ecap_qis(iommu->ecap)) in dmar_disable_qi()
1545 raw_spin_lock_irqsave(&iommu->register_lock, flags); in dmar_disable_qi()
1547 sts = readl(iommu->reg + DMAR_GSTS_REG); in dmar_disable_qi()
1554 while ((readl(iommu->reg + DMAR_IQT_REG) != in dmar_disable_qi()
1555 readl(iommu->reg + DMAR_IQH_REG)) && in dmar_disable_qi()
1556 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time))) in dmar_disable_qi()
1559 iommu->gcmd &= ~DMA_GCMD_QIE; in dmar_disable_qi()
1560 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in dmar_disable_qi()
1562 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, in dmar_disable_qi()
1565 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in dmar_disable_qi()
1571 static void __dmar_enable_qi(struct intel_iommu *iommu) in __dmar_enable_qi() argument
1575 struct q_inval *qi = iommu->qi; in __dmar_enable_qi()
1576 u64 val = virt_to_phys(qi->desc); in __dmar_enable_qi()
1578 qi->free_head = qi->free_tail = 0; in __dmar_enable_qi()
1579 qi->free_cnt = QI_LENGTH; in __dmar_enable_qi()
1585 if (ecap_smts(iommu->ecap)) in __dmar_enable_qi()
1588 raw_spin_lock_irqsave(&iommu->register_lock, flags); in __dmar_enable_qi()
1591 writel(0, iommu->reg + DMAR_IQT_REG); in __dmar_enable_qi()
1593 dmar_writeq(iommu->reg + DMAR_IQA_REG, val); in __dmar_enable_qi()
1595 iommu->gcmd |= DMA_GCMD_QIE; in __dmar_enable_qi()
1596 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in __dmar_enable_qi()
1599 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); in __dmar_enable_qi()
1601 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in __dmar_enable_qi()
1606 * interrupt-remapping. Also used by DMA-remapping, which replaces
1609 int dmar_enable_qi(struct intel_iommu *iommu) in dmar_enable_qi() argument
1614 if (!ecap_qis(iommu->ecap)) in dmar_enable_qi()
1615 return -ENOENT; in dmar_enable_qi()
1620 if (iommu->qi) in dmar_enable_qi()
1623 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC); in dmar_enable_qi()
1624 if (!iommu->qi) in dmar_enable_qi()
1625 return -ENOMEM; in dmar_enable_qi()
1627 qi = iommu->qi; in dmar_enable_qi()
1633 desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, in dmar_enable_qi()
1634 !!ecap_smts(iommu->ecap)); in dmar_enable_qi()
1637 iommu->qi = NULL; in dmar_enable_qi()
1638 return -ENOMEM; in dmar_enable_qi()
1641 qi->desc = page_address(desc_page); in dmar_enable_qi()
1643 qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC); in dmar_enable_qi()
1644 if (!qi->desc_status) { in dmar_enable_qi()
1645 free_page((unsigned long) qi->desc); in dmar_enable_qi()
1647 iommu->qi = NULL; in dmar_enable_qi()
1648 return -ENOMEM; in dmar_enable_qi()
1651 raw_spin_lock_init(&qi->q_lock); in dmar_enable_qi()
1653 __dmar_enable_qi(iommu); in dmar_enable_qi()
1658 /* iommu interrupt handling. Most stuff are MSI-like. */
1678 "non-zero reserved fields in RTP",
1679 "non-zero reserved fields in CTP",
1680 "non-zero reserved fields in PTE",
1688 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */
1691 "SM: Non-zero reserved field set in Root Entry",
1692 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */
1695 "SM: Non-zero reserved field set in the Context Entry",
1700 "SM: PRE field in Context-Entry is clear",
1701 "SM: RID_PASID field error in Context-Entry",
1702 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */
1705 "SM: Non-zero reserved field set in PASID Directory Entry",
1706 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */
1709 "SM: Non-zero reserved field set in PASID Table Entry",
1710 "SM: Invalid Scalable-Mode PASID Table Entry",
1713 "Unknown", "Unknown",/* 0x5E-0x5F */
1714 …"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x…
1715 …"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x…
1716 "SM: Error attempting to access first-level paging entry",
1717 "SM: Present bit in first-level paging entry is clear",
1718 "SM: Non-zero reserved field set in first-level paging entry",
1719 "SM: Error attempting to access FL-PML4 entry",
1720 "SM: First-level entry address beyond MGAW in Nested translation",
1721 "SM: Read permission error in FL-PML4 entry in Nested translation",
1722 "SM: Read permission error in first-level paging entry in Nested translation",
1723 "SM: Write permission error in first-level paging entry in Nested translation",
1724 "SM: Error attempting to access second-level paging entry",
1725 "SM: Read/Write permission error in second-level paging entry",
1726 "SM: Non-zero reserved field set in second-level paging entry",
1727 "SM: Invalid second-level page table pointer",
1728 "SM: A/D bit update needed in second-level entry when set up in no snoop",
1729 "Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */
1730 "SM: Address in first-level translation is not canonical",
1731 "SM: U/S set 0 for first-level translation with user privilege",
1734 "SM: Second-level entry address beyond the max",
1737 "SM: Invalid address-interrupt address",
1738 …"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x…
1739 "SM: A/D bit update needed in first-level entry when set up in no snoop",
1744 "Detected reserved fields in the decoded interrupt-remapped request",
1745 "Interrupt index exceeded the interrupt-remapping table size",
1747 "Error accessing interrupt-remapping table pointed by IRTA_REG",
1750 "Blocked an interrupt request due to source-id verification failure",
1755 if (fault_reason >= 0x20 && (fault_reason - 0x20 < in dmar_get_fault_reason()
1758 return irq_remap_fault_reasons[fault_reason - 0x20]; in dmar_get_fault_reason()
1759 } else if (fault_reason >= 0x30 && (fault_reason - 0x30 < in dmar_get_fault_reason()
1762 return dma_remap_sm_fault_reasons[fault_reason - 0x30]; in dmar_get_fault_reason()
1773 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq) in dmar_msi_reg() argument
1775 if (iommu->irq == irq) in dmar_msi_reg()
1777 else if (iommu->pr_irq == irq) in dmar_msi_reg()
1785 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); in dmar_msi_unmask() local
1786 int reg = dmar_msi_reg(iommu, data->irq); in dmar_msi_unmask()
1790 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_unmask()
1791 writel(0, iommu->reg + reg); in dmar_msi_unmask()
1793 readl(iommu->reg + reg); in dmar_msi_unmask()
1794 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_unmask()
1799 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); in dmar_msi_mask() local
1800 int reg = dmar_msi_reg(iommu, data->irq); in dmar_msi_mask()
1804 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_mask()
1805 writel(DMA_FECTL_IM, iommu->reg + reg); in dmar_msi_mask()
1807 readl(iommu->reg + reg); in dmar_msi_mask()
1808 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_mask()
1813 struct intel_iommu *iommu = irq_get_handler_data(irq); in dmar_msi_write() local
1814 int reg = dmar_msi_reg(iommu, irq); in dmar_msi_write()
1817 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_write()
1818 writel(msg->data, iommu->reg + reg + 4); in dmar_msi_write()
1819 writel(msg->address_lo, iommu->reg + reg + 8); in dmar_msi_write()
1820 writel(msg->address_hi, iommu->reg + reg + 12); in dmar_msi_write()
1821 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_write()
1826 struct intel_iommu *iommu = irq_get_handler_data(irq); in dmar_msi_read() local
1827 int reg = dmar_msi_reg(iommu, irq); in dmar_msi_read()
1830 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_read()
1831 msg->data = readl(iommu->reg + reg + 4); in dmar_msi_read()
1832 msg->address_lo = readl(iommu->reg + reg + 8); in dmar_msi_read()
1833 msg->address_hi = readl(iommu->reg + reg + 12); in dmar_msi_read()
1834 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_read()
1837 static int dmar_fault_do_one(struct intel_iommu *iommu, int type, in dmar_fault_do_one() argument
1847 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index %llx [fault reason %02d] %s\n", in dmar_fault_do_one()
1863 struct intel_iommu *iommu = dev_id; in dmar_fault() local
1871 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_fault()
1872 fault_status = readl(iommu->reg + DMAR_FSTS_REG); in dmar_fault()
1881 reg = cap_fault_reg_offset(iommu->cap); in dmar_fault()
1894 data = readl(iommu->reg + reg + in dmar_fault()
1904 data = readl(iommu->reg + reg + in dmar_fault()
1909 guest_addr = dmar_readq(iommu->reg + reg + in dmar_fault()
1915 writel(DMA_FRCD_F, iommu->reg + reg + in dmar_fault()
1918 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_fault()
1921 /* Using pasid -1 if pasid is not present */ in dmar_fault()
1922 dmar_fault_do_one(iommu, type, fault_reason, in dmar_fault()
1923 pasid_present ? pasid : -1, in dmar_fault()
1927 if (fault_index >= cap_num_fault_regs(iommu->cap)) in dmar_fault()
1929 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_fault()
1933 iommu->reg + DMAR_FSTS_REG); in dmar_fault()
1936 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_fault()
1940 int dmar_set_interrupt(struct intel_iommu *iommu) in dmar_set_interrupt() argument
1947 if (iommu->irq) in dmar_set_interrupt()
1950 irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu); in dmar_set_interrupt()
1952 iommu->irq = irq; in dmar_set_interrupt()
1955 return -EINVAL; in dmar_set_interrupt()
1958 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu); in dmar_set_interrupt()
1967 struct intel_iommu *iommu; in enable_drhd_fault_handling() local
1972 for_each_iommu(iommu, drhd) { in enable_drhd_fault_handling()
1974 int ret = dmar_set_interrupt(iommu); in enable_drhd_fault_handling()
1978 (unsigned long long)drhd->reg_base_addr, ret); in enable_drhd_fault_handling()
1979 return -1; in enable_drhd_fault_handling()
1985 dmar_fault(iommu->irq, iommu); in enable_drhd_fault_handling()
1986 fault_status = readl(iommu->reg + DMAR_FSTS_REG); in enable_drhd_fault_handling()
1987 writel(fault_status, iommu->reg + DMAR_FSTS_REG); in enable_drhd_fault_handling()
1994 * Re-enable Queued Invalidation interface.
1996 int dmar_reenable_qi(struct intel_iommu *iommu) in dmar_reenable_qi() argument
1998 if (!ecap_qis(iommu->ecap)) in dmar_reenable_qi()
1999 return -ENOENT; in dmar_reenable_qi()
2001 if (!iommu->qi) in dmar_reenable_qi()
2002 return -ENOENT; in dmar_reenable_qi()
2007 dmar_disable_qi(iommu); in dmar_reenable_qi()
2010 * invalidation requests now, it's safe to re-enable queued in dmar_reenable_qi()
2013 __dmar_enable_qi(iommu); in dmar_reenable_qi()
2027 return dmar->flags & 0x1; in dmar_ir_support()
2048 list_del(&dmaru->list); in dmar_free_unused_resources()
2062 * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
2086 int ret = -ENODEV; in dmar_walk_dsm_resource()
2102 return -ENODEV; in dmar_walk_dsm_resource()
2107 start = (struct acpi_dmar_header *)obj->buffer.pointer; in dmar_walk_dsm_resource()
2108 ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback); in dmar_walk_dsm_resource()
2122 return -ENODEV; in dmar_hp_add_drhd()
2144 if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) { in dmar_hp_remove_drhd()
2145 for_each_active_dev_scope(dmaru->devices, in dmar_hp_remove_drhd()
2146 dmaru->devices_cnt, i, dev) in dmar_hp_remove_drhd()
2147 return -EBUSY; in dmar_hp_remove_drhd()
2163 list_del_rcu(&dmaru->list); in dmar_hp_release_drhd()
2272 return -ENXIO; in dmar_device_hotplug()
2299 * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table
2316 ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN); in dmar_platform_optin()