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/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dpci-iommu.txt2 relationship between PCI(e) devices and IOMMU(s).
17 Requester ID. While a given PCI device can only master through one IOMMU, a
18 root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
33 -------------------
35 - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
39 (rid-base,iommu,iommu-base,length).
41 Any RID r in the interval [rid-base, rid-base + length) is associated with
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Dapple,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <kettenis@openbsd.org>
22 the standard "reset-gpios" and "max-link-speed" properties appear on
34 - enum:
35 - apple,t8103-pcie
36 - apple,t6000-pcie
37 - const: apple,pcie
43 reg-names:
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/Linux-v6.1/arch/sparc/kernel/
Dpci_sun4v.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/dma-map-ops.h>
20 #include <asm/iommu-common.h>
22 #include <asm/iommu.h>
57 unsigned long prot; /* IOMMU page protections */
71 p->dev = dev; in iommu_batch_start()
72 p->prot = prot; in iommu_batch_start()
73 p->entry = entry; in iommu_batch_start()
74 p->npages = 0; in iommu_batch_start()
77 static inline bool iommu_use_atu(struct iommu *iommu, u64 mask) in iommu_use_atu() argument
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Diommu-common.c1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU mmap management and range allocation functions.
4 * Based almost entirely upon the powerpc iommu allocator.
10 #include <linux/iommu-helper.h>
11 #include <linux/dma-mapping.h>
13 #include <asm/iommu-common.h>
19 static inline bool need_flush(struct iommu_map_table *iommu) in need_flush() argument
21 return ((iommu->flags & IOMMU_NEED_FLUSH) != 0); in need_flush()
24 static inline void set_flush(struct iommu_map_table *iommu) in set_flush() argument
26 iommu->flags |= IOMMU_NEED_FLUSH; in set_flush()
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Dpci.c1 // SPDX-License-Identifier: GPL-2.0
41 volatile int pci_poke_cpu = -1;
62 pci_poke_cpu = -1; in pci_config_read8()
84 pci_poke_cpu = -1; in pci_config_read16()
106 pci_poke_cpu = -1; in pci_config_read32()
127 pci_poke_cpu = -1; in pci_config_write8()
146 pci_poke_cpu = -1; in pci_config_write16()
165 pci_poke_cpu = -1; in pci_config_write32()
201 /* The of_device layer has translated all of the assigned-address properties
213 addrs = of_get_property(node, "assigned-addresses", &proplen); in pci_parse_of_addrs()
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/Linux-v6.1/drivers/of/
Ddevice.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-direct.h> /* for bus_dma_region */
10 #include <linux/dma-map-ops.h>
21 * of_match_device - Tell if a struct device matches an of_device_id list
31 if (!matches || !dev->of_node || dev->of_node_reused) in of_match_device()
33 return of_match_node(matches, dev->of_node); in of_match_device()
39 BUG_ON(ofdev->dev.of_node == NULL); in of_device_add()
43 ofdev->name = dev_name(&ofdev->dev); in of_device_add()
44 ofdev->id = PLATFORM_DEVID_NONE; in of_device_add()
51 set_dev_node(&ofdev->dev, of_node_to_nid(ofdev->dev.of_node)); in of_device_add()
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/Linux-v6.1/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.txt3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
22 the set of possible ICIDs under a root DPRC and how they map to
23 an IOMMU.
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
28 For arm-smmu binding, see:
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/Linux-v6.1/arch/powerpc/boot/dts/fsl/
Dp5020si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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Dp3041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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Dp2041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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Dp5040si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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Dp4080si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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Dt1040si-post.dtsi4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
35 #include <dt-bindings/thermal/thermal.h>
38 compatible = "fsl,bman-fbpr";
39 alloc-ranges = <0 0 0x10000 0>;
43 compatible = "fsl,qman-fqd";
44 alloc-ranges = <0 0 0x10000 0>;
48 compatible = "fsl,qman-pfdr";
49 alloc-ranges = <0 0 0x10000 0>;
53 #address-cells = <2>;
54 #size-cells = <1>;
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/Linux-v6.1/arch/arm64/boot/dts/nvidia/
Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/power/tegra234-powergate.h>
9 #include <dt-bindings/reset/tegra234-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
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/Linux-v6.1/drivers/vfio/
Dvfio_iommu_type1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * VFIO: IOMMU DMA mapping support for Type1 IOMMU
12 * We arbitrarily define a Type1 IOMMU as one matching the below code.
13 * It could be called the x86 IOMMU as it's designed for AMD-Vi & Intel
14 * VT-d, but that makes it harder to re-use as theoretically anyone
15 * implementing a similar IOMMU could make use of this. We expect the
16 * IOMMU to support the IOMMU API and have few to no restrictions around
17 * the IOVA range that can be mapped. The Type1 IOMMU is currently
19 * userspace pages pinned into memory. We also assume devices and IOMMU
20 * domains are PCI based as the IOMMU API is still centered around a
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/Linux-v6.1/drivers/iommu/
Dof_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OF helpers for IOMMU
9 #include <linux/iommu.h>
26 struct fwnode_handle *fwnode = &iommu_spec->np->fwnode; in of_iommu_xlate()
30 if ((ops && !ops->of_xlate) || in of_iommu_xlate()
31 !of_device_is_available(iommu_spec->np)) in of_iommu_xlate()
34 ret = iommu_fwspec_init(dev, &iommu_spec->np->fwnode, ops); in of_iommu_xlate()
38 * The otherwise-empty fwspec handily serves to indicate the specific in of_iommu_xlate()
39 * IOMMU device we're waiting for, which will be useful if we ever get in of_iommu_xlate()
40 * a proper probe-ordering dependency mechanism in future. in of_iommu_xlate()
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/Linux-v6.1/Documentation/devicetree/bindings/iommu/
Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
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/Linux-v6.1/arch/arm64/boot/dts/marvell/
Dcn9130-crb-A.dts1 // SPDX-License-Identifier: GPL-2.0+
6 #include "cn9130-crb.dtsi"
9 model = "Marvell Armada CN9130-CRB-A";
14 num-lanes = <4>;
15 num-viewport = <8>;
21 iommu-map =
25 iommu-map-mask = <0x031f>;
30 usb-phy = <&cp0_usb3_0_phy0>;
31 phy-names = "usb";
36 usb-phy = <&cp0_usb3_0_phy1>;
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Darmada-7040.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-ap806-quad.dtsi"
10 #include "armada-70x0.dtsi"
14 compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
15 "marvell,armada-ap806";
19 iommu-map =
23 iommu-map-mask = <0x031f>;
Dcn9130-crb-B.dts1 // SPDX-License-Identifier: GPL-2.0+
6 #include "cn9130-crb.dtsi"
9 model = "Marvell Armada CN9130-CRB-B";
14 num-lanes = <1>;
15 num-viewport = <8>;
18 iommu-map =
22 iommu-map-mask = <0x031f>;
27 sata-port@0 {
36 usb-phy = <&cp0_usb3_0_phy0>;
37 phy-names = "usb";
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Darmada-8040.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-ap806-quad.dtsi"
10 #include "armada-80x0.dtsi"
14 compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
15 "marvell,armada-ap806";
19 iommu-map =
23 iommu-map-mask = <0x031f>;
/Linux-v6.1/drivers/iommu/intel/
Ddmar.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2006-2008 Intel Corporation
14 * These routines are used by both DMA-remapping and Interrupt-remapping
28 #include <linux/iommu.h>
33 #include "iommu.h"
48 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
50 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
66 static void free_iommu(struct intel_iommu *iommu);
74 if (drhd->include_all) in dmar_register_drhd_unit()
75 list_add_tail_rcu(&drhd->list, &dmar_drhd_units); in dmar_register_drhd_unit()
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/Linux-v6.1/arch/sparc/include/asm/
Diommu-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 unsigned long *map; member
35 extern void iommu_tbl_pool_init(struct iommu_map_table *iommu,
43 struct iommu_map_table *iommu,
46 unsigned long mask,
49 extern void iommu_tbl_range_free(struct iommu_map_table *iommu,
/Linux-v6.1/arch/arm64/boot/dts/arm/
Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
31 #mbox-cells = <1>;
33 clock-names = "apb_pclk";
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/Linux-v6.1/arch/powerpc/include/asm/
Diommu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 #include <linux/dma-map-ops.h>
19 #include <asm/pci-bridge.h>
20 #include <asm/asm-const.h>
24 #define IOMMU_PAGE_MASK_4K (~((1 << IOMMU_PAGE_SHIFT_4K) - 1))
27 #define IOMMU_PAGE_SIZE(tblptr) (ASM_CONST(1) << (tblptr)->it_page_shift)
28 #define IOMMU_PAGE_MASK(tblptr) (~((1 << (tblptr)->it_page_shift) - 1))
38 * uaddr is a linear map address.
48 * returns old TCE and DMA direction mask.
93 unsigned long it_size; /* Size of iommu table in entries */
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