Lines Matching +full:iommu +full:- +full:map +full:- +full:mask
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - const: qcom,smmu-v2
33 - description: Qcom SoCs implementing "arm,mmu-500"
35 - enum:
36 - qcom,qcm2290-smmu-500
37 - qcom,sc7180-smmu-500
38 - qcom,sc7280-smmu-500
39 - qcom,sc8180x-smmu-500
40 - qcom,sc8280xp-smmu-500
41 - qcom,sdm845-smmu-500
42 - qcom,sdx55-smmu-500
43 - qcom,sdx65-smmu-500
44 - qcom,sm6350-smmu-500
45 - qcom,sm6375-smmu-500
46 - qcom,sm8150-smmu-500
47 - qcom,sm8250-smmu-500
48 - qcom,sm8350-smmu-500
49 - qcom,sm8450-smmu-500
50 - const: arm,mmu-500
51 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
53 - enum:
54 - qcom,sc7180-smmu-v2
55 - qcom,sdm845-smmu-v2
56 - const: qcom,adreno-smmu
57 - const: qcom,smmu-v2
58 - description: Marvell SoCs implementing "arm,mmu-500"
60 - const: marvell,ap806-smmu-500
61 - const: arm,mmu-500
62 - description: NVIDIA SoCs that require memory controller interaction
63 and may program multiple ARM MMU-500s identically with the memory
67 - enum:
68 - nvidia,tegra186-smmu
69 - nvidia,tegra194-smmu
70 - nvidia,tegra234-smmu
71 - const: nvidia,smmu-500
72 - items:
73 - const: arm,mmu-500
74 - const: arm,smmu-v2
75 - items:
76 - enum:
77 - arm,mmu-400
78 - arm,mmu-401
79 - const: arm,smmu-v1
80 - enum:
81 - arm,smmu-v1
82 - arm,smmu-v2
83 - arm,mmu-400
84 - arm,mmu-401
85 - arm,mmu-500
86 - cavium,smmu-v2
92 '#global-interrupts':
96 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
98 '#iommu-cells':
101 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
102 value of 1, each IOMMU specifier represents a distinct stream ID emitted
106 2, where the second cell of the IOMMU specifier represents an SMR mask to
114 Interrupt list, with the first #global-interrupts entries corresponding to
122 dma-coherent:
130 calxeda,smmu-secure-config-access:
134 access to SMMU configuration registers. In this case non-secure aliases of
137 stream-match-mask:
140 For SMMUs supporting stream matching and using #iommu-cells = <1>,
141 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
142 be programmed into the SMRn.MASK field of every stream match register
144 Stream ID (e.g. for certain MMU-500 configurations given globally unique
146 using stream matching with #iommu-cells = <2>, and may be ignored if
149 clock-names:
151 - const: bus
152 - const: iface
156 - description: bus clock required for downstream bus access and for the
158 - description: interface clock required to access smmu's registers
161 power-domains:
164 nvidia,memory-controller:
171 will be used and it is not guaranteed that IOMMU translations will be
176 - compatible
177 - reg
178 - '#global-interrupts'
179 - '#iommu-cells'
180 - interrupts
185 - if:
190 - nvidia,tegra186-smmu
191 - nvidia,tegra194-smmu
192 - nvidia,tegra234-smmu
201 # IOMMU attachment.
203 - nvidia,memory-controller
210 - |+
212 smmu1: iommu@ba5e0000 {
213 compatible = "arm,smmu-v1";
215 #global-interrupts = <2>;
222 #iommu-cells = <1>;
233 smmu2: iommu@ba5f0000 {
234 compatible = "arm,smmu-v1";
236 #global-interrupts = <2>;
243 #iommu-cells = <2>;
258 /* ARM MMU-500 with 10-bit stream ID input configuration */
259 smmu3: iommu@ba600000 {
260 compatible = "arm,mmu-500", "arm,smmu-v2";
262 #global-interrupts = <2>;
269 #iommu-cells = <1>;
270 /* always ignore appended 5-bit TBU number */
271 stream-match-mask = <0x7c00>;
275 /* bus whose child devices emit one unique 10-bit stream
277 iommu-map = <0 &smmu3 0 0x400>;
282 - |+
283 /* Qcom's arm,smmu-v2 implementation */
284 #include <dt-bindings/interrupt-controller/arm-gic.h>
285 #include <dt-bindings/interrupt-controller/irq.h>
286 smmu4: iommu@d00000 {
287 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
290 #global-interrupts = <1>;
294 #iommu-cells = <1>;
295 power-domains = <&mmcc 0>;
299 clock-names = "bus", "iface";