Lines Matching +full:iommu +full:- +full:map +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/dma-map-ops.h>
20 #include <asm/iommu-common.h>
22 #include <asm/iommu.h>
57 unsigned long prot; /* IOMMU page protections */
71 p->dev = dev; in iommu_batch_start()
72 p->prot = prot; in iommu_batch_start()
73 p->entry = entry; in iommu_batch_start()
74 p->npages = 0; in iommu_batch_start()
77 static inline bool iommu_use_atu(struct iommu *iommu, u64 mask) in iommu_use_atu() argument
79 return iommu->atu && mask > DMA_BIT_MASK(32); in iommu_use_atu()
83 static long iommu_batch_flush(struct iommu_batch *p, u64 mask) in iommu_batch_flush() argument
85 struct pci_pbm_info *pbm = p->dev->archdata.host_controller; in iommu_batch_flush()
86 u64 *pglist = p->pglist; in iommu_batch_flush()
88 unsigned long devhandle = pbm->devhandle; in iommu_batch_flush()
89 unsigned long prot = p->prot; in iommu_batch_flush()
90 unsigned long entry = p->entry; in iommu_batch_flush()
91 unsigned long npages = p->npages; in iommu_batch_flush()
101 if (!iommu_use_atu(pbm->iommu, mask)) { in iommu_batch_flush()
108 pr_err_ratelimited("%s: IOMMU map of [%08lx:%08llx:%lx:%lx:%lx] failed with status %ld\n", in iommu_batch_flush()
114 return -1; in iommu_batch_flush()
118 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num; in iommu_batch_flush()
126 pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n", in iommu_batch_flush()
131 return -1; in iommu_batch_flush()
135 npages -= num; in iommu_batch_flush()
139 p->entry = entry; in iommu_batch_flush()
140 p->npages = 0; in iommu_batch_flush()
145 static inline void iommu_batch_new_entry(unsigned long entry, u64 mask) in iommu_batch_new_entry() argument
149 if (p->entry + p->npages == entry) in iommu_batch_new_entry()
151 if (p->entry != ~0UL) in iommu_batch_new_entry()
152 iommu_batch_flush(p, mask); in iommu_batch_new_entry()
153 p->entry = entry; in iommu_batch_new_entry()
157 static inline long iommu_batch_add(u64 phys_page, u64 mask) in iommu_batch_add() argument
161 BUG_ON(p->npages >= PGLIST_NENTS); in iommu_batch_add()
163 p->pglist[p->npages++] = phys_page; in iommu_batch_add()
164 if (p->npages == PGLIST_NENTS) in iommu_batch_add()
165 return iommu_batch_flush(p, mask); in iommu_batch_add()
171 static inline long iommu_batch_end(u64 mask) in iommu_batch_end() argument
175 BUG_ON(p->npages >= PGLIST_NENTS); in iommu_batch_end()
177 return iommu_batch_flush(p, mask); in iommu_batch_end()
184 u64 mask; in dma_4v_alloc_coherent() local
187 struct iommu *iommu; in dma_4v_alloc_coherent() local
204 nid = dev->archdata.numa_node; in dma_4v_alloc_coherent()
212 iommu = dev->archdata.iommu; in dma_4v_alloc_coherent()
213 mask = dev->coherent_dma_mask; in dma_4v_alloc_coherent()
214 if (!iommu_use_atu(iommu, mask)) in dma_4v_alloc_coherent()
215 tbl = &iommu->tbl; in dma_4v_alloc_coherent()
217 tbl = &iommu->atu->tbl; in dma_4v_alloc_coherent()
220 (unsigned long)(-1), 0); in dma_4v_alloc_coherent()
225 *dma_addrp = (tbl->table_map_base + (entry << IO_PAGE_SHIFT)); in dma_4v_alloc_coherent()
237 long err = iommu_batch_add(first_page + (n * PAGE_SIZE), mask); in dma_4v_alloc_coherent()
242 if (unlikely(iommu_batch_end(mask) < 0L)) in dma_4v_alloc_coherent()
268 list_for_each_entry(pdev, &bus_dev->devices, bus_list) { in dma_4v_iotsb_bind()
269 if (pdev->subordinate) { in dma_4v_iotsb_bind()
272 pdev->subordinate); in dma_4v_iotsb_bind()
274 bus = bus_dev->number; in dma_4v_iotsb_bind()
275 device = PCI_SLOT(pdev->devfn); in dma_4v_iotsb_bind()
276 fun = PCI_FUNC(pdev->devfn); in dma_4v_iotsb_bind()
317 npages -= num; in dma_4v_iommu_demap()
326 struct iommu *iommu; in dma_4v_free_coherent() local
334 iommu = dev->archdata.iommu; in dma_4v_free_coherent()
335 pbm = dev->archdata.host_controller; in dma_4v_free_coherent()
336 atu = iommu->atu; in dma_4v_free_coherent()
337 devhandle = pbm->devhandle; in dma_4v_free_coherent()
339 if (!iommu_use_atu(iommu, dvma)) { in dma_4v_free_coherent()
340 tbl = &iommu->tbl; in dma_4v_free_coherent()
341 iotsb_num = 0; /* we don't care for legacy iommu */ in dma_4v_free_coherent()
343 tbl = &atu->tbl; in dma_4v_free_coherent()
344 iotsb_num = atu->iotsb->iotsb_num; in dma_4v_free_coherent()
346 entry = ((dvma - tbl->table_map_base) >> IO_PAGE_SHIFT); in dma_4v_free_coherent()
359 struct iommu *iommu; in dma_4v_map_page() local
362 u64 mask; in dma_4v_map_page() local
369 iommu = dev->archdata.iommu; in dma_4v_map_page()
370 atu = iommu->atu; in dma_4v_map_page()
376 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK); in dma_4v_map_page()
379 mask = *dev->dma_mask; in dma_4v_map_page()
380 if (!iommu_use_atu(iommu, mask)) in dma_4v_map_page()
381 tbl = &iommu->tbl; in dma_4v_map_page()
383 tbl = &atu->tbl; in dma_4v_map_page()
386 (unsigned long)(-1), 0); in dma_4v_map_page()
391 bus_addr = (tbl->table_map_base + (entry << IO_PAGE_SHIFT)); in dma_4v_map_page()
406 long err = iommu_batch_add(base_paddr, mask); in dma_4v_map_page()
410 if (unlikely(iommu_batch_end(mask) < 0L)) in dma_4v_map_page()
433 struct iommu *iommu; in dma_4v_unmap_page() local
447 iommu = dev->archdata.iommu; in dma_4v_unmap_page()
448 pbm = dev->archdata.host_controller; in dma_4v_unmap_page()
449 atu = iommu->atu; in dma_4v_unmap_page()
450 devhandle = pbm->devhandle; in dma_4v_unmap_page()
452 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); in dma_4v_unmap_page()
457 iotsb_num = 0; /* we don't care for legacy iommu */ in dma_4v_unmap_page()
458 tbl = &iommu->tbl; in dma_4v_unmap_page()
460 iotsb_num = atu->iotsb->iotsb_num; in dma_4v_unmap_page()
461 tbl = &atu->tbl; in dma_4v_unmap_page()
463 entry = (bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT; in dma_4v_unmap_page()
478 struct iommu *iommu; in dma_4v_map_sg() local
481 u64 mask; in dma_4v_map_sg() local
487 iommu = dev->archdata.iommu; in dma_4v_map_sg()
488 if (nelems == 0 || !iommu) in dma_4v_map_sg()
489 return -EINVAL; in dma_4v_map_sg()
490 atu = iommu->atu; in dma_4v_map_sg()
505 outs->dma_length = 0; in dma_4v_map_sg()
514 mask = *dev->dma_mask; in dma_4v_map_sg()
515 if (!iommu_use_atu(iommu, mask)) in dma_4v_map_sg()
516 tbl = &iommu->tbl; in dma_4v_map_sg()
518 tbl = &atu->tbl; in dma_4v_map_sg()
520 base_shift = tbl->table_map_base >> IO_PAGE_SHIFT; in dma_4v_map_sg()
525 slen = s->length; in dma_4v_map_sg()
531 /* Allocate iommu entries for that segment */ in dma_4v_map_sg()
535 &handle, (unsigned long)(-1), 0); in dma_4v_map_sg()
539 pr_err_ratelimited("iommu_alloc failed, iommu %p paddr %lx npages %lx\n", in dma_4v_map_sg()
544 iommu_batch_new_entry(entry, mask); in dma_4v_map_sg()
547 dma_addr = tbl->table_map_base + (entry << IO_PAGE_SHIFT); in dma_4v_map_sg()
548 dma_addr |= (s->offset & ~IO_PAGE_MASK); in dma_4v_map_sg()
552 while (npages--) { in dma_4v_map_sg()
553 err = iommu_batch_add(paddr, mask); in dma_4v_map_sg()
562 * - allocated dma_addr isn't contiguous to previous allocation in dma_4v_map_sg()
565 (outs->dma_length + s->length > max_seg_size) || in dma_4v_map_sg()
573 outs->dma_length += s->length; in dma_4v_map_sg()
579 outs->dma_address = dma_addr; in dma_4v_map_sg()
580 outs->dma_length = slen; in dma_4v_map_sg()
588 err = iommu_batch_end(mask); in dma_4v_map_sg()
597 outs->dma_length = 0; in dma_4v_map_sg()
604 if (s->dma_length != 0) { in dma_4v_map_sg()
607 vaddr = s->dma_address & IO_PAGE_MASK; in dma_4v_map_sg()
608 npages = iommu_num_pages(s->dma_address, s->dma_length, in dma_4v_map_sg()
613 s->dma_length = 0; in dma_4v_map_sg()
620 return -EINVAL; in dma_4v_map_sg()
629 struct iommu *iommu; in dma_4v_unmap_sg() local
637 iommu = dev->archdata.iommu; in dma_4v_unmap_sg()
638 pbm = dev->archdata.host_controller; in dma_4v_unmap_sg()
639 atu = iommu->atu; in dma_4v_unmap_sg()
640 devhandle = pbm->devhandle; in dma_4v_unmap_sg()
645 while (nelems--) { in dma_4v_unmap_sg()
646 dma_addr_t dma_handle = sg->dma_address; in dma_4v_unmap_sg()
647 unsigned int len = sg->dma_length; in dma_4v_unmap_sg()
657 iotsb_num = 0; /* we don't care for legacy iommu */ in dma_4v_unmap_sg()
658 tbl = &iommu->tbl; in dma_4v_unmap_sg()
660 iotsb_num = atu->iotsb->iotsb_num; in dma_4v_unmap_sg()
661 tbl = &atu->tbl; in dma_4v_unmap_sg()
663 entry = ((dma_handle - tbl->table_map_base) >> shift); in dma_4v_unmap_sg()
676 struct iommu *iommu = dev->archdata.iommu; in dma_4v_supported() local
680 if (device_mask < iommu->dma_addr_mask) in dma_4v_supported()
700 dp = pbm->op->dev.of_node; in pci_sun4v_scan_bus()
701 prop = of_find_property(dp, "66mhz-capable", NULL); in pci_sun4v_scan_bus()
702 pbm->is_66mhz_capable = (prop != NULL); in pci_sun4v_scan_bus()
703 pbm->pci_bus = pci_scan_one_pbm(pbm, parent); in pci_sun4v_scan_bus()
709 struct iommu_map_table *iommu) in probe_existing_entries() argument
715 devhandle = pbm->devhandle; in probe_existing_entries()
716 for (pool_nr = 0; pool_nr < iommu->nr_pools; pool_nr++) { in probe_existing_entries()
717 pool = &(iommu->pools[pool_nr]); in probe_existing_entries()
718 for (i = pool->start; i <= pool->end; i++) { in probe_existing_entries()
731 __set_bit(i, iommu->map); in probe_existing_entries()
741 struct atu *atu = pbm->iommu->atu; in pci_sun4v_atu_alloc_iotsb()
751 err = -ENOMEM; in pci_sun4v_atu_alloc_iotsb()
754 atu->iotsb = iotsb; in pci_sun4v_atu_alloc_iotsb()
757 table_size = (atu->size / IO_PAGE_SIZE) * 8; in pci_sun4v_atu_alloc_iotsb()
761 err = -ENOMEM; in pci_sun4v_atu_alloc_iotsb()
764 iotsb->table = table; in pci_sun4v_atu_alloc_iotsb()
765 iotsb->ra = __pa(table); in pci_sun4v_atu_alloc_iotsb()
766 iotsb->dvma_size = atu->size; in pci_sun4v_atu_alloc_iotsb()
767 iotsb->dvma_base = atu->base; in pci_sun4v_atu_alloc_iotsb()
768 iotsb->table_size = table_size; in pci_sun4v_atu_alloc_iotsb()
769 iotsb->page_size = IO_PAGE_SIZE; in pci_sun4v_atu_alloc_iotsb()
772 err = pci_sun4v_iotsb_conf(pbm->devhandle, in pci_sun4v_atu_alloc_iotsb()
773 iotsb->ra, in pci_sun4v_atu_alloc_iotsb()
774 iotsb->table_size, in pci_sun4v_atu_alloc_iotsb()
775 iotsb->page_size, in pci_sun4v_atu_alloc_iotsb()
776 iotsb->dvma_base, in pci_sun4v_atu_alloc_iotsb()
782 iotsb->iotsb_num = iotsb_num; in pci_sun4v_atu_alloc_iotsb()
784 err = dma_4v_iotsb_bind(pbm->devhandle, iotsb_num, pbm->pci_bus); in pci_sun4v_atu_alloc_iotsb()
802 struct atu *atu = pbm->iommu->atu; in pci_sun4v_atu_init()
810 ranges = of_get_property(pbm->op->dev.of_node, "iommu-address-ranges", in pci_sun4v_atu_init()
813 pr_err(PFX "No iommu-address-ranges\n"); in pci_sun4v_atu_init()
814 return -EINVAL; in pci_sun4v_atu_init()
817 page_size = of_get_property(pbm->op->dev.of_node, "iommu-pagesizes", in pci_sun4v_atu_init()
820 pr_err(PFX "No iommu-pagesizes\n"); in pci_sun4v_atu_init()
821 return -EINVAL; in pci_sun4v_atu_init()
824 /* There are 4 iommu-address-ranges supported. Each range is pair of in pci_sun4v_atu_init()
834 atu->ranges = (struct atu_ranges *)ranges; in pci_sun4v_atu_init()
835 atu->base = atu->ranges[3].base; in pci_sun4v_atu_init()
836 atu->size = ATU_64_SPACE_SIZE; in pci_sun4v_atu_init()
845 /* Create ATU iommu map. in pci_sun4v_atu_init()
848 dma_mask = (roundup_pow_of_two(atu->size) - 1UL); in pci_sun4v_atu_init()
849 num_iotte = atu->size / IO_PAGE_SIZE; in pci_sun4v_atu_init()
851 atu->tbl.table_map_base = atu->base; in pci_sun4v_atu_init()
852 atu->dma_addr_mask = dma_mask; in pci_sun4v_atu_init()
853 atu->tbl.map = kzalloc(map_size, GFP_KERNEL); in pci_sun4v_atu_init()
854 if (!atu->tbl.map) in pci_sun4v_atu_init()
855 return -ENOMEM; in pci_sun4v_atu_init()
857 iommu_tbl_pool_init(&atu->tbl, num_iotte, IO_PAGE_SHIFT, in pci_sun4v_atu_init()
868 struct iommu *iommu = pbm->iommu; in pci_sun4v_iommu_init() local
873 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL); in pci_sun4v_iommu_init()
878 printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n", in pci_sun4v_iommu_init()
880 return -EINVAL; in pci_sun4v_iommu_init()
883 dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL); in pci_sun4v_iommu_init()
888 /* Setup initial software IOMMU state. */ in pci_sun4v_iommu_init()
889 spin_lock_init(&iommu->lock); in pci_sun4v_iommu_init()
890 iommu->ctx_lowest_free = 1; in pci_sun4v_iommu_init()
891 iommu->tbl.table_map_base = dma_offset; in pci_sun4v_iommu_init()
892 iommu->dma_addr_mask = dma_mask; in pci_sun4v_iommu_init()
894 /* Allocate and initialize the free area map. */ in pci_sun4v_iommu_init()
897 iommu->tbl.map = kzalloc(sz, GFP_KERNEL); in pci_sun4v_iommu_init()
898 if (!iommu->tbl.map) { in pci_sun4v_iommu_init()
899 printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n"); in pci_sun4v_iommu_init()
900 return -ENOMEM; in pci_sun4v_iommu_init()
902 iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT, in pci_sun4v_iommu_init()
906 sz = probe_existing_entries(pbm, &iommu->tbl); in pci_sun4v_iommu_init()
909 pbm->name, sz); in pci_sun4v_iommu_init()
943 * For MSI-X bits 31:0 are the data from the MSI packet.
945 * bits 39:32 is the bus/device/fn of the msg target-id
948 * For INTx the low order 2-bits are:
949 * 00 - INTA
950 * 01 - INTB
951 * 10 - INTC
952 * 11 - INTD
964 err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head); in pci_sun4v_get_head()
966 return -ENXIO; in pci_sun4v_get_head()
968 limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); in pci_sun4v_get_head()
970 return -EFBIG; in pci_sun4v_get_head()
983 ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * in pci_sun4v_dequeue_msi()
984 (pbm->msiq_ent_count * in pci_sun4v_dequeue_msi()
988 if ((ep->version_type & MSIQ_TYPE_MASK) == 0) in pci_sun4v_dequeue_msi()
991 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT; in pci_sun4v_dequeue_msi()
994 return -EINVAL; in pci_sun4v_dequeue_msi()
996 *msi = ep->msi_data; in pci_sun4v_dequeue_msi()
998 err = pci_sun4v_msi_setstate(pbm->devhandle, in pci_sun4v_dequeue_msi()
999 ep->msi_data /* msi_num */, in pci_sun4v_dequeue_msi()
1002 return -ENXIO; in pci_sun4v_dequeue_msi()
1005 ep->version_type &= ~MSIQ_TYPE_MASK; in pci_sun4v_dequeue_msi()
1009 (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry))) in pci_sun4v_dequeue_msi()
1020 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head); in pci_sun4v_set_head()
1022 return -EINVAL; in pci_sun4v_set_head()
1030 if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid, in pci_sun4v_msi_setup()
1033 return -ENXIO; in pci_sun4v_msi_setup()
1034 if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE)) in pci_sun4v_msi_setup()
1035 return -ENXIO; in pci_sun4v_msi_setup()
1036 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID)) in pci_sun4v_msi_setup()
1037 return -ENXIO; in pci_sun4v_msi_setup()
1045 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid); in pci_sun4v_msi_teardown()
1047 return -ENXIO; in pci_sun4v_msi_teardown()
1049 pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID); in pci_sun4v_msi_teardown()
1059 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); in pci_sun4v_msiq_alloc()
1060 alloc_size = (pbm->msiq_num * q_size); in pci_sun4v_msiq_alloc()
1066 return -ENOMEM; in pci_sun4v_msiq_alloc()
1069 pbm->msi_queues = (void *) pages; in pci_sun4v_msiq_alloc()
1071 for (i = 0; i < pbm->msiq_num; i++) { in pci_sun4v_msiq_alloc()
1075 err = pci_sun4v_msiq_conf(pbm->devhandle, in pci_sun4v_msiq_alloc()
1076 pbm->msiq_first + i, in pci_sun4v_msiq_alloc()
1077 base, pbm->msiq_ent_count); in pci_sun4v_msiq_alloc()
1084 err = pci_sun4v_msiq_info(pbm->devhandle, in pci_sun4v_msiq_alloc()
1085 pbm->msiq_first + i, in pci_sun4v_msiq_alloc()
1092 if (ret1 != base || ret2 != pbm->msiq_ent_count) { in pci_sun4v_msiq_alloc()
1095 base, pbm->msiq_ent_count, in pci_sun4v_msiq_alloc()
1105 return -EINVAL; in pci_sun4v_msiq_alloc()
1113 for (i = 0; i < pbm->msiq_num; i++) { in pci_sun4v_msiq_free()
1114 unsigned long msiqid = pbm->msiq_first + i; in pci_sun4v_msiq_free()
1116 (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0); in pci_sun4v_msiq_free()
1119 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); in pci_sun4v_msiq_free()
1120 alloc_size = (pbm->msiq_num * q_size); in pci_sun4v_msiq_free()
1123 pages = (unsigned long) pbm->msi_queues; in pci_sun4v_msiq_free()
1127 pbm->msi_queues = NULL; in pci_sun4v_msiq_free()
1134 unsigned int irq = sun4v_build_irq(pbm->devhandle, devino); in pci_sun4v_msiq_build_irq()
1137 return -ENOMEM; in pci_sun4v_msiq_build_irq()
1139 if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID)) in pci_sun4v_msiq_build_irq()
1140 return -EINVAL; in pci_sun4v_msiq_build_irq()
1141 if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE)) in pci_sun4v_msiq_build_irq()
1142 return -EINVAL; in pci_sun4v_msiq_build_irq()
1171 struct device_node *dp = op->dev.of_node; in pci_sun4v_pbm_init()
1174 pbm->numa_node = of_node_to_nid(dp); in pci_sun4v_pbm_init()
1176 pbm->pci_ops = &sun4v_pci_ops; in pci_sun4v_pbm_init()
1177 pbm->config_space_reg_bits = 12; in pci_sun4v_pbm_init()
1179 pbm->index = pci_num_pbms++; in pci_sun4v_pbm_init()
1181 pbm->op = op; in pci_sun4v_pbm_init()
1183 pbm->devhandle = devhandle; in pci_sun4v_pbm_init()
1185 pbm->name = dp->full_name; in pci_sun4v_pbm_init()
1187 printk("%s: SUN4V PCI Bus Module\n", pbm->name); in pci_sun4v_pbm_init()
1188 printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node); in pci_sun4v_pbm_init()
1200 pci_sun4v_scan_bus(pbm, &op->dev); in pci_sun4v_pbm_init()
1203 * we can still continue using legacy iommu. in pci_sun4v_pbm_init()
1205 if (pbm->iommu->atu) { in pci_sun4v_pbm_init()
1208 kfree(pbm->iommu->atu); in pci_sun4v_pbm_init()
1209 pbm->iommu->atu = NULL; in pci_sun4v_pbm_init()
1214 pbm->next = pci_pbm_root; in pci_sun4v_pbm_init()
1226 struct iommu *iommu; in pci_sun4v_probe() local
1229 int i, err = -ENODEV; in pci_sun4v_probe()
1232 dp = op->dev.of_node; in pci_sun4v_probe()
1267 err = -ENODEV; in pci_sun4v_probe()
1272 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff; in pci_sun4v_probe()
1274 err = -ENOMEM; in pci_sun4v_probe()
1293 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); in pci_sun4v_probe()
1294 if (!iommu) { in pci_sun4v_probe()
1295 printk(KERN_ERR PFX "Could not allocate pbm iommu\n"); in pci_sun4v_probe()
1299 pbm->iommu = iommu; in pci_sun4v_probe()
1300 iommu->atu = NULL; in pci_sun4v_probe()
1306 iommu->atu = atu; in pci_sun4v_probe()
1313 dev_set_drvdata(&op->dev, pbm); in pci_sun4v_probe()
1318 kfree(iommu->atu); in pci_sun4v_probe()
1319 kfree(pbm->iommu); in pci_sun4v_probe()
1331 .compatible = "SUNW,sun4v-pci",